Traffic Light Controller

A synchronous FSM-based traffic light controller for a single road, written in Verilog / SystemVerilog.

Author: Ashraful Hasan Bhuiyan

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Overview

Cycles a single road's signal through three states in fixed order:

RED → YELLOW → GREEN → RED → ...

Built on a counter + comparator + FSM datapath. State durations are parameters, not hardcoded values.

Requirements

Item	Specification
Clock	Synchronous clk
Reset	Active-high, asynchronous rst
Start behavior	Idle after reset until start is pressed; then runs continuously
RED duration	50 clock cycles
GREEN duration	50 clock cycles)
YELLOW duration	5 clock cycles
State control	FSM drives transitions; internal counter tracks elapsed cycles per state
Output	Exactly one of RED, YELLOW, GREEN asserted at any time

Design Task Breakdown

1. ASM (Algorithmic State Machine) state diagram
2. State transition logic
3. Counter / timer logic
4. Output logic
5. RTL module implementation in Verilog / SystemVerilog
6. Testbench covering the full RED -> YELLOW -> GREEN sequence

Architecture

FSM State Diagram

Four states - IDLE, RED, YELLOW, GREEN - with counter-driven transitions.

ASM Chart

• Decision boxes check cnt_eq_50 / cnt_eq_5 to decide when to leave the current state.
• Each state box drives choices for transitions and asserts output signals (red_light, yellow_light, green_light).

Top-Level Interface

Integrates traffic_light_ctrl_top with inputs (clk, arst_n, start) and outputs (red_light, yellow_light, green_light).

Micro-Architecture

Datapath and control signals connect the counter, comparator, and FSM to drive the light outputs.

File List

File / Path	Description
rtl/counter.v	Cycle counter for timing each state
rtl/comparator.v	Compares counter value against thresholds (cnt_eq_50, cnt_eq_5)
rtl/traffic_light_ctrl_fsm.v	FSM for state transitions and output logic
rtl/traffic_light_ctrl_top.v	Top-level module integrating counter, comparator, FSM
tb/traffic_light_ctrl_tb.v	Testbench for the full RED → YELLOW → GREEN sequence
sim/compile.f	File list containing all source files for compilation
sim/Makefile	Makefile supporting Vivado (xsim) and Cadence (ncsim) flows
sim/run_vivado.sh	Bash script for running Vivado simulation flow
sim/run_nc.sh	Bash script for running NC-Sim simulation flow

How to Run Simulation

Navigate to the simulation directory first:

cd sim

1. Vivado Simulator (xsim) Flow (Default)

Using Makefile:

# Full simulation flow (compile + elaborate + sim)
make

# Or step-by-step
make compile
make elaborate
make sim

# Launch waveform GUI
make gui

Using Bash Script (run_vivado.sh):

# Batch mode
./run_vivado.sh

# GUI mode
./run_vivado.sh gui

2. Cadence NC-Sim (ncsim) Flow

You can run NC-Sim using either the Makefile or the provided bash script:

Using Makefile:

# Full NC-Sim flow
make SIM=nc

# Shortcut
make nc

# Step-by-step with NC-Sim
make SIM=nc compile
make SIM=nc elaborate
make SIM=nc sim
make SIM=nc gui

Using Bash Script (run_nc.sh):

# Batch mode
./run_nc.sh

# GUI mode
./run_nc.sh gui

3. Cleaning Build Artifacts

To remove generated log files and simulation artifacts:

# Using Makefile
make clean

# Using bash scripts
./run_vivado.sh clean
./run_nc.sh clean

Notes

• File paths for compilation are managed central in sim/compile.f.
• State durations are parameters, so retiming for simulation or different real-world timing is a one-line change.
• Design idles after reset until start is asserted, then free-runs through the sequence indefinitely.