Add compiler-derived compute and HBM latency models

[YuxuanHan0326]

Summary

Adds a compiler-derived analytical latency path covering both compute execution and HBM service.

Data flow

Final compiler schedule
→ symbolic CostTrace
→ compute timing
→ physical DMA traffic
→ HBM V4
→ stage-wise roofline latency

Main changes

• Compiler-trace compute timing providers
• Stage, resource, opcode, and operand-variant breakdowns
• Configured main timing and explicit experimental ideal-II1 timing
• Generic HBM V4 physical-request model
• Exact affine sufficient-statistics aggregation
• Stage-wise compute/memory roofline
• Semantic caching and compressed long-context evaluation

Validation

• Detailed and compressed compute/DMA totals are identical
• HBM grouped and scalar backends preserve traffic exactly
• HBM V4 holdout median error: 3.48%
• HBM V4 holdout P95 error: 18.10%
• Qwen3-32B 90k×8 cold evaluation: 19.31 s
• Long-context warm evaluation is sub-millisecond with a semantic cache hit

Dependency

Depends on PR AICrossSim/PLENA_Compiler#71

The Compiler branch commit is already available in the official repository, so this PR can be reviewed and tested before the Compiler PR is merged.

Compatibility

The existing closed-form latency backend remains available and unchanged.

[GeorgeWu1204]

LGTM, ty