Add action-based analytical power modeling

[YuxuanHan0326]

Summary

Adds an action-based analytical power model on top of compiler CostTrace and HBM V4 traffic.

Main changes

• Action-family dynamic-energy accounting
• Matrix, Vector, Scalar, control, SRAM, and HBM-controller breakdowns
• Ideal hierarchical clock-gating estimate
• Ungated clock-power upper bound
• External HBM3E traffic and background energy
• Empirical low/nominal/high activity envelope
• Versioned calibration and physical-property inputs

Validation

• CostTrace action-family coverage: 100%
• Main-compatible power holdout median error: 7.47%
• Main-compatible power holdout P95 error: 22.13%
• Detailed and compressed traces produce identical action totals
• Ideal clock energy never exceeds the ungated result

Dependencies

• Add symbolic final-schedule CostTrace backend PLENA_Compiler#71
• Add compiler-derived compute and HBM latency models #103

This is a stacked PR. Its base is the analytical-latency branch so reviewers initially see only the Power changes.

Scope

This model excludes multi-chip links, package, cooling, CTS, SRAM leakage, and signoff-level physical effects.