openrisc

All CPU and MCU documentation in one place

Online OR1K Emulator running Linux

mor1kx - an OpenRISC 1000 processor IP core

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

Ada-language framework

Generating the call graph from elf binary file

Multi-Processor System on Chip verified with UVM/OSVVM/FV

System on Chip verified with UVM/OSVVM/FV

OpenRISC processor IP core based on Tomasulo algorithm

An OpenRISC 1000 Instruction Set Simulator

OpenRISC 1000 processor module for IDA 7.x

Processing Unit verified with UVM/OSVVM/FV

Lisp-based stackless interpreter and platform, including microthreading. Features taken from Lisp and Erlang.

A curated awesome list of royalty-free, open-source CPU design and architecture resources (RISC-V, OpenRISC).

OpenCpuX wrapper for the or1kiss OpenRISC ISS

Processing Unit with OpenRISC-32 / OpenRISC-64

Multi-Processor System on Chip with OpenRISC-32 / OpenRISC-64

A custom 64-bit single-core RISC-V processor designed from scratch in SystemVerilog. Built with a modular architecture intended to serve as a building block for future multi-core scaling.

This project is a modified verison of the OpenRISC 1200 open-source processor, designed to estimate the feasibility of using an On-Chip Software Obfuscator to reduce the controllability over software activated Hardware Trojans.