Refactored Check-in - #336
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- Add CgraRTL_relu4x4_test_from_yaml.py: ReLU kernel test on 4x4 Mesh CGRA using relu.yaml compiled kernel config (II=5, 32 iterations) - Fix script_generator.py: swap STORE src_operands to match MemUnitRTL hardware expectation (in0=address, in1=data vs YAML order [data, addr])
…flag Bug #1 - CrossbarRTL all-or-nothing: Stale prologued data blocked entire crossbar - Mask recv_valid_vector, exclude prologued from send/recv_required_vector - Gate changed: recv_valid_or_prologue_allowing_vector Bug #2 - PhiRTL shared first flag: Multiple PHI_START on same tile failed - Detect iteration wrap via ctrl_addr, clear s.first only at boundaries - Added prev_ctrl_addr tracking Tests: ReLU 379 cycles (pass), SpMV 759 cycles (pass)
# Conflicts: # mem/register_cluster/RegisterBankRTL.py
Co-authored-by: Jackcuii <113412207+Jackcuii@users.noreply.github.com>
Co-authored-by: Jackcuii <113412207+Jackcuii@users.noreply.github.com>
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Hi Sir Tan @tancheng I think it is ok ~ Let us wait for the tests. Please check if there are anything else we need to modify 🤓 |
Thank you Sir Tan~ Finally we merge it hahaha |
Thank you Bohan @Jackcuii~! Plz make another PR that only contains the register-related changes, so we can check-in the missing test (I forgot which one is still blocked by the register-related fixes). |
Sure! I think the blocked ones are gemm and gemv. I need first identify the root cause of the diff ~ |
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