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Allow zero identity add predicate #308

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Allow zero identity add predicate #308

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00b4b02
Allow zero identity add predicate
guosran Jun 25, 2026
91ca140
Merge remote-tracking branch 'origin/master' into pr-adder-zero
guosran Jul 14, 2026
bd7abd7
Allow SUB with predicated zero operand
guosran Jul 16, 2026
28d570a
Explain zero identity predicate
guosran Jul 16, 2026
ca73e31
Clarify zero identity predicate
guosran Jul 16, 2026
93f5665
Merge branch 'master' into fix/adder-zero-predicate
guosran Jul 23, 2026
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37 changes: 31 additions & 6 deletions fu/single/AdderRTL.py
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Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,23 @@ def comb_logic():
if s.recv_opt.val:
if s.recv_opt.msg.operation == OPT_ADD:
s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload + s.recv_in[s.in1_idx].msg.payload
s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \
s.recv_in[s.in1_idx].msg.predicate & \
s.reached_vector_factor
# Treat a predicated-off zero as the additive identity: a zero value with
# predicate=0 is a neutral placeholder, not a missing contributing
# operand. Example: (value=7,pred=1) + (value=0,pred=0) should
# produce pred=1, while (value=7,pred=1) + (value=5,pred=0) stays
# pred=0.
if s.recv_in[s.in0_idx].msg.predicate & s.recv_in[s.in1_idx].msg.predicate:
s.send_out[0].msg.predicate @= s.reached_vector_factor
elif s.recv_in[s.in0_idx].msg.predicate & \
~s.recv_in[s.in1_idx].msg.predicate & \

@tancheng tancheng Jun 26, 2026

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Why s.recv_in[s.in1_idx].msg.predicate won't affect output's predicate?

(s.recv_in[s.in1_idx].msg.payload == s.const_zero.payload):
s.send_out[0].msg.predicate @= s.reached_vector_factor
elif s.recv_in[s.in1_idx].msg.predicate & \
~s.recv_in[s.in0_idx].msg.predicate & \
(s.recv_in[s.in0_idx].msg.payload == s.const_zero.payload):
s.send_out[0].msg.predicate @= s.reached_vector_factor
else:
s.send_out[0].msg.predicate @= 0
s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val
s.send_out[0].val @= s.recv_all_val
s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy
Expand Down Expand Up @@ -99,9 +113,20 @@ def comb_logic():

elif s.recv_opt.msg.operation == OPT_SUB:
s.send_out[0].msg.payload @= s.recv_in[s.in0_idx].msg.payload - s.recv_in[s.in1_idx].msg.payload
s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \
s.recv_in[s.in1_idx].msg.predicate & \
s.reached_vector_factor
# Same identity rule for SUB: subtracting an inactive zero keeps
# the active operand live; subtracting an inactive nonzero does not.
if s.recv_in[s.in0_idx].msg.predicate & s.recv_in[s.in1_idx].msg.predicate:
s.send_out[0].msg.predicate @= s.reached_vector_factor
elif s.recv_in[s.in0_idx].msg.predicate & \
~s.recv_in[s.in1_idx].msg.predicate & \
(s.recv_in[s.in1_idx].msg.payload == s.const_zero.payload):
s.send_out[0].msg.predicate @= s.reached_vector_factor
elif s.recv_in[s.in1_idx].msg.predicate & \
~s.recv_in[s.in0_idx].msg.predicate & \
(s.recv_in[s.in0_idx].msg.payload == s.const_zero.payload):
s.send_out[0].msg.predicate @= s.reached_vector_factor
else:
s.send_out[0].msg.predicate @= 0
s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val
s.send_out[0].val @= s.recv_all_val
s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy
Expand Down
28 changes: 28 additions & 0 deletions fu/single/test/AdderRTL_test.py
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Original file line number Diff line number Diff line change
Expand Up @@ -100,3 +100,31 @@ def test_alu():
src_const, src_opt, sink_out)
run_sim(th)

def test_add_false_predicate_zero_is_identity():
FU = AdderRTL
DataType = mk_data(16, 1)
num_inports = 2
num_outports = 1
ConfigType = mk_ctrl(num_inports, num_outports)
FuInType = mk_bits(clog2(num_inports + 1))

data_mem_size = 8
ctrl_mem_size = 8
DataAddrType = mk_bits(clog2(data_mem_size))
CtrlAddrType = mk_bits(clog2(ctrl_mem_size))
CgraPayloadType = mk_cgra_payload(DataType, DataAddrType, ConfigType, CtrlAddrType)
IntraCgraPktType = mk_intra_cgra_pkt(1, 1, 1, CgraPayloadType)

pickRegister = [FuInType(x + 1) for x in range(num_inports)]
src_in0 = [DataType(5, 1), DataType(5, 1), DataType(0, 0)]
src_in1 = [DataType(0, 0), DataType(2, 0), DataType(7, 1)]
src_const = [DataType(0, 0)]
sink_out = [DataType(5, 1), DataType(7, 0), DataType(7, 1)]
src_opt = [ConfigType(OPT_ADD, pickRegister),
ConfigType(OPT_ADD, pickRegister),
ConfigType(OPT_ADD, pickRegister)]

th = TestHarness(FU, IntraCgraPktType, DataType, ConfigType, num_inports,
num_outports, data_mem_size, src_in0, src_in1,
src_const, src_opt, sink_out)
run_sim(th)
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