Needed Packages for Simple Addition

[Lee404notfound]

Hey,
I'm currently working on getting a feeling for how the CGRA works. I'm using a verilated Model from the CgraRTL_fir_2x2_test.py . Now I want to understand the ISA for the different packages: What would be the minimum of packages needed to perform a simple addition of two values. I don't really want to send the data across a lot, it would suffice to perform everything in tile 0.

Thanks a lot in advance!

[yyan7223]

You can start with:

VectorCGRA/tile/test/TileRTL_test.py

Lines 106 to 221 in df45072

	def test_tile_alu(cmdline_opts):
	num_tile_inports = 4
	num_tile_outports = 4
	num_fu_inports = 4
	num_fu_outports = 2
	num_routing_outports = num_fu_inports + num_tile_outports
	ctrl_mem_size = 3
	data_mem_size_global = 16
	num_cgra_rows = 1
	num_cgra_columns = 1
	num_cgras = num_cgra_rows * num_cgra_columns
	num_tiles = 4
	num_commands = NUM_CMDS
	num_ctrl_operations = NUM_OPTS
	num_registers_per_reg_bank = 16
	TileInType = mk_bits(clog2(num_tile_inports + num_fu_inports + 1))
	FuInType = mk_bits(clog2(num_fu_inports + 1))
	FuOutType = mk_bits(clog2(num_fu_outports + 1))
	pick_register0 = [FuInType(0) for x in range(num_fu_inports)]
	pick_register1 = [FuInType(1), FuInType(2), FuInType(0), FuInType(0)]
	DUT = TileRTL
	FunctionUnit = FlexibleFuRTL
	# FuList = [AdderRTL, MulRTL, MemUnitRTL]
	FuList = [AdderRTL,
	MulRTL,
	LogicRTL,
	ShifterRTL,
	PhiRTL,
	CompRTL,
	GrantRTL,
	MemUnitRTL,
	SelRTL,
	ThreeMulAdderShifterRTL,
	VectorMulComboRTL,
	VectorAdderComboRTL]
	# 64-bit to satisfy the default bitwidth of vector FUs.
	data_nbits = 64
	DataType = mk_data(data_nbits, 1)
	PredicateType = mk_predicate(1, 1)
	cgra_id_nbits = 1
	addr_nbits = clog2(data_mem_size_global)
	predicate_nbits = 1
	CtrlType = mk_ctrl(num_fu_inports,
	num_fu_outports,
	num_tile_inports,
	num_tile_outports,
	num_registers_per_reg_bank)
	CtrlAddrType = mk_bits(clog2(ctrl_mem_size))
	DataAddrType = mk_bits(addr_nbits)
	CgraPayloadType = mk_cgra_payload(DataType,
	DataAddrType,
	CtrlType,
	CtrlAddrType)
	IntraCgraPktType = mk_intra_cgra_pkt(num_cgra_columns,
	num_cgra_rows,
	num_tiles,
	CgraPayloadType)
	src_ctrl_pkt = [
	# src dst src_cgra_id dst_cgra_id cgra_src/dst_x/y
	IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0,
	payload = CgraPayloadType(CMD_CONFIG, ctrl_addr = 0,
	ctrl = CtrlType(OPT_ADD,
	[FuInType(1), FuInType(2), FuInType(0), FuInType(0)],
	[TileInType(0), TileInType(0), TileInType(0), TileInType(0),
	TileInType(4), TileInType(3), TileInType(0), TileInType(0)],
	[FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(1),
	FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)]))),
	IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0,
	payload = CgraPayloadType(CMD_CONFIG, ctrl_addr = 1,
	ctrl = CtrlType(OPT_SUB,
	[FuInType(1), FuInType(2), FuInType(0), FuInType(0)],
	[TileInType(0), TileInType(0), TileInType(0), TileInType(0),
	TileInType(4), TileInType(1), TileInType(0), TileInType(0)],
	[FuOutType(1), FuOutType(0), FuOutType(0), FuOutType(1),
	FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0)]))),
	# For constant 5, 7.
	IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_CONST, data = DataType(5, 1))),
	IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_CONST, data = DataType(7, 1))),
	IntraCgraPktType(0, 0, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_LAUNCH))]
	src_data = [[DataType(3, 1)],
	[],
	[DataType(4, 1)],
	[DataType(5, 1), DataType(7, 1)]]
	sink_out = [
	# Nothing at cycle 0; 7 - 3 = 4 at cycle 1.
	[ DataType(4, 1)],
	[],
	[],
	# 5 + 4 = 9 at cycle 0; 7 - 3 = 4 at cycle 1.
	[DataType(9, 1), DataType(4, 1)]]
	# src dst src/dst cgra x/y
	complete_signal_sink_out = [IntraCgraPktType(0, num_tiles, 0, 0, 0, 0, 0, 0, payload = CgraPayloadType(CMD_COMPLETE))]
	# IntraCgraPktType(0, 0, num_tiles, 0, 0, ctrl_action = CMD_COMPLETE)]
	th = TestHarness(DUT, FunctionUnit, FuList,
	IntraCgraPktType,
	ctrl_mem_size,
	data_mem_size_global, num_fu_inports, num_fu_outports,
	num_tile_inports, num_tile_outports,
	num_registers_per_reg_bank, src_data,
	src_ctrl_pkt, sink_out, num_tiles, complete_signal_sink_out)
	th.elaborate()
	th.dut.set_metadata(VerilogVerilatorImportPass.vl_Wno_list,
	['UNSIGNED', 'UNOPTFLAT', 'WIDTH', 'WIDTHCONCAT',
	'ALWCOMBORDER'])
	th = config_model_with_cmdline_opts(th, cmdline_opts, duts = ['dut'])
	run_sim(th)

[tancheng]

Hey, I'm currently working on getting a feeling for how the CGRA works. I'm using a verilated Model from the CgraRTL_fir_2x2_test.py . Now I want to understand the ISA for the different packages: What would be the minimum of packages needed to perform a simple addition of two values. I don't really want to send the data across a lot, it would suffice to perform everything in tile 0.

Thanks a lot in advance!

I think you might need to understand one FIR kernel, and then create your own test.
Your test probably contains a few steps:

• Preload data into SRAM (CPU issue store request)
• ld A
• ld B
• C = A + B
• st C
• Check data (CPU issue read request)

[byte-bob]

Thanks for the fast responses!
We are trying to follow our packages and the trace with GTK Wave and still can't figure out what we're missing on. We can find the signals for the OPT type and the signal with the whole package, but not the ones with the values inside the tile.
For example for "Preload data into SRAM (CPU issue store request)" we are using 12(CMD_STORE_REQUEST), 0 (OPT_START) and leaving the payload empty. For "ld A" we are using 3(OPT_CONFIG), 12(OPT_LD) and as payload any number.

[tancheng]

I think it would be helpful if your pytest file can be provided.

Or are you starting from a verilog testbench?

[byte-bob]

We are attempting to extend the tb.cpp main method from this issue and send the packages one after the other, where we set the bits for OPT, CMD and payload.

[tancheng]

We can find the signals for the OPT type and the signal with the whole package, but not the ones with the values inside the tile.

@byte-bob can you elaborate a little bit? We can see data is stored correctly, but cannot see the operations in tile's config memory?

Hi @yyan7223, can you help on this issue?

[yyan7223]

@byte-bob @Lee404notfound I suggest that you firstly follow those steps to setup VectorCGRA in a docker container.
Then use commands to generate the vcd file, and check it using the GTK Wave.
Feel free to schedule a google meeting, my email is yyf305016@163.com.

[byte-bob]

Thanks for the offer, we will think about it.

We are using the verilog code generated by this py-test by following those steps and extended it with the tb.cpp. And currently we want a simple addition of two values.

In gtk wave we can find in "tile_0" the signal "recv_pkt_from_controller_msg" with the whole 214 bit package, but we can't find the signal where the payload value is stored from the "ld A"-step. With "CMD_CONST" we can find our value in "const_mem" and later with "OPT_ADD_CONST" we found the value in "send_out_message", we are assuming that it did a 0 + const.

Which CMD do I need for a ld-operation and where can I find the value in the trace later?

Sorry for the confusion, we know what we're doing is a bit different from the intended way of this repository.

[yyan7223]

OPT_LD is for the ld-operation, you can find the value in element.from_mem_rdata.

[byte-bob]

Thanks!
Now we can see the value in "element.from_mem_rdata" but it's in fu7. Do we have to tell the cgra to load it into fu0 or does the cgra do it automatically when it gets a package with, for example, an add operation?

[yyan7223]

VectorCGRA/cgra/test/CgraRTL_fir_2x2_test.py

Lines 152 to 163 in dfb47f2

	FuList = [AdderRTL,
	MulRTL,
	LogicRTL,
	ShifterRTL,
	PhiRTL,
	CompRTL,
	GrantRTL,
	MemUnitRTL,
	SelRTL,
	RetRTL,
	FourIncCmpNotGrantRTL,
	]

You can move MemUnitRTL to the start of the list, then it will be the fu0

[Lee404notfound]

Thanks, but I think there's a misunderstanding. What we meant was, how do we (or the cgra) load the value that is in fu7 (the MemUnit) into the AdderRTL (which currently is fu0)?

[yyan7223]

Thanks, but I think there's a misunderstanding. What we meant was, how do we (or the cgra) load the value that is in fu7 (the MemUnit) into the AdderRTL (which currently is fu0)?

You can route the memory access result back to register_cluster using fu_crossbar, then read from the register_cluster and send it to the AdderRTL at next clock cycle.

[Lee404notfound]

Thanks, we played around with the values a bit, but still could not get it to work. I think to better explain our problem, we are sharing the edited testbench that we are using (the original is linked in the first message of this issue). We know that it may seem too complicated and naive, since were setting the bits for the packages manually. This is the progress we had before trying out different values for fu_xbar_outport, that is why the function for setting this is missing. So when executing the value 3 is in FU7 and the package with opt ADD lands in FU0. So the same issue from before persists.

[yyan7223]

Please provide a python testbench if possible.