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Add an AVX-512 variant of Transpose - #218
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FL_ORDER reverses the 3 bits of the order, so the transpose only changes
the sequence of the 10 bits of the element index. The AVX-512 kernels
hold the 1024 elements in 512-bit registers, where some index bits give
the register number and the other bits give the lane. A const fn plan
moves the bits with vpermt2b/d/q on register pairs, and with 256-bit
inserts on load and extracts on store where they save a permute level.
u16 uses the byte permute, because vpermt2w takes three micro-ops on
Intel.
transpose_avx512 and untranspose_avx512 take the fearless_simd Avx512
token (the Ice Lake feature set, which includes AVX-512 F, BW and VBMI).
The Transpose impl uses them before AVX2 when the level has them.
Median time per 1024-value chunk, 64-byte aligned buffers, transpose /
untranspose, AVX2 -> AVX-512:
Granite Rapids Sapphire Rapids Zen 4 Zen 5
u8 33->25 / 38->32 36->28 / 41->34 29->21 / 35->23 21->10 / 30->10
u16 50->42 / 55->46 54->46 / 60->49 40->39 / 41->39 28->18 / 30->16
u32 66->44 / 68->44 71->44 / 74->43 46->60 / 46->60 39->30 / 44->30
u64 78->74 / 77->74 91->81 / 91->78 90->107 / 85->107 75->60 / 77->59
Zen 4 runs 512-bit shuffles at half rate, so u32 and u64 are slower
there than with AVX2.
Signed-off-by: Robert Kruszewski <github@robertk.io>
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Median ns per 1024-value chunk on EC2 (c8i, c7i, c7a, c8a), 64-byte aligned buffers, transpose / untranspose, AVX2 → AVX-512: