Issues

• Verilog - Hierarchical reference inside labeled generete

  verilog
  nickg/nvc#1680 · Filter by author Anselmo95 opened on Oct 6, 2026
  1

• Verilog - mismatched error positions

  verilog
  nickg/nvc#1678 · Filter by author Blebowski opened on Oct 6, 2026

• Verilog - MIN_TYP_MAX expression

  verilog
  nickg/nvc#1677 · Filter by author Blebowski opened on Oct 6, 2026

• Verilog "deassign" statement

  verilog
  nickg/nvc#1676 · Filter by author Blebowski opened on Oct 6, 2026

• nvc --do creates always an empty work library

  nickg/nvc#1675 · Filter by author am9417 opened on Oct 6, 2026
  2

• Compilation of Xilinx Microblaze

  nickg/nvc#1671 · Filter by author Ford2003 opened on Oct 1, 2026
  1

• [BUG] VHDL-2019 conditional expressions break when adding parentheses

  2019
  nickg/nvc#1669 · Filter by author jobtijhuis opened on Sep 29, 2026
  4

• Logic operation between different length vectors undetected

  nickg/nvc#1666 · Filter by author gfcwfzkm opened on Sep 23, 2026
  1

• using expressions over ports as actuals to nested entity instantiations results in undefined values

  nickg/nvc#1662 · Filter by author rcgoodfellow opened on Sep 19, 2026
  

• block rule in a coverage spec file only matches the nearest named scope, not the whole entity subtree

  nickg/nvc#1654 · Filter by author lzulberti opened on Sep 6, 2026
  1

• Assertion failed: error_count() > 0, file ../src/vlog/vlog-symtab.c, line 287

  verilog
  nickg/nvc#1650 · Filter by author avelure opened on Aug 27, 2026

• *nvc --install* in Windows

  nickg/nvc#1646 · Filter by author DRubioG opened on Aug 24, 2026

• Mixed simulation question

  verilogwishlist
  nickg/nvc#1642 · Filter by author DRubioG opened on Aug 14, 2026
  1

• Non-locally static choice error in array aggregate with multiple associations

  wishlist
  nickg/nvc#1637 · Filter by author svn-inventas opened on Aug 10, 2026
  1

• Code coverage pragma bug

  nickg/nvc#1635 · Filter by author Blebowski opened on Aug 8, 2026

• VHDL-2008: Packages in processes and variables in those packages

  2008
  nickg/nvc#1633 · Filter by author bpadalino opened on Aug 7, 2026

• Check-synthesis improvements

  wishlist
  nickg/nvc#1631 · Filter by author Blebowski opened on Aug 3, 2026

• --cover-export --format=cobertura: allow setting <source> and attribute classes to the defining file (GitLab integration).

  nickg/nvc#1630 · Filter by author tasgomes opened on Jul 31, 2026
  2

• System Verilog Enums

  nickg/nvc#1628 · Filter by author Blebowski opened on Jul 29, 2026

• Coverage does not work when elaborating multiple tops

  nickg/nvc#1623 · Filter by author Blebowski opened on Jul 24, 2026

• VHPI and Verilog

  verilogvhpi
  nickg/nvc#1618 · Filter by author oscargus opened on Jul 20, 2026
  6

• Using VHDL from Verilog

  verilog
  nickg/nvc#1617 · Filter by author oscargus opened on Jul 20, 2026

• Record aggregate others after a named nested-record field uses the wrong vector width

  nickg/nvc#1589 · Filter by author SiliSiliBoy opened on Jun 23, 2026
  3

• Foreign VHPI function with an unconstrained array parameter crashes if the unconstrained array type is declared in the same hierarchy

  vhpi
  nickg/nvc#1586 · Filter by author dalex78 opened on Jun 19, 2026

• Signal 11 (SEGV_MAPERR) when accessing a record element which has no association in its instantiation.

  nickg/nvc#1584 · Filter by author MartinHanl opened on Jun 19, 2026