ggml : enable INT8 convrot on HIP for RDNA3/RDNA4/CDNA - #6
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Remove the blanket GGML_USE_HIP exclusion from the INT8 tensorwise convrot ops and scope the capability check to GPUs with working integer GEMM support (turing_mma_available, amd_wmma_available, amd_mfma_available). RDNA2 stays excluded: hipBLASLt INT8 is broken there. vendors/hip.h: map CUDA_R_8I, CUDA_R_32I, CUBLAS_COMPUTE_32I and __shfl_down_sync to their HIP equivalents. HIP's masked shuffle templates require a 64-bit mask, so route to the maskless intrinsic like the other __shfl_*_sync mappings. Verified on gfx1100 (Windows ROCm 7.1): ggml tests/test-int8-convrot passes, and CPU-vs-GPU output is bit-exact at real model shapes (K=3840/10240, N up to 11520, 8104 rows).
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Removes the blanket GGML_USE_HIP exclusion; MUSA guards unchanged.
Capability check now accepts turing_mma_available (NVIDIA Turing+), amd_wmma_available (RDNA3/3.5/4), or amd_mfma_available (CDNA), instead of NVIDIA-only.
RDNA2 stays excluded: hipBLASLt INT8 GEMM is broken there (HIPBLAS_STATUS_INVALID_VALUE via torch._int_mm on gfx1030; ref the ComfyUI-INT8-Fast-ROCM investigation).
RDNA2 would need a custom DP4A kernel, which is out of scope here.
vendors/hip.h: map CUDA_R_8I / CUDA_R_32I / CUBLAS_COMPUTE_32I to their HIPBLAS equivalents, and add the missing __shfl_down_sync -> maskless __shfl_down mapping (HIP's masked-shuffle template requires a 64-bit mask, so CUDA-style 0xffffffff fails to compile; same convention as the existing __shfl_sync/__shfl_up_sync/__shfl_xor_sync mappings).
The kernels themselves are arch-neutral SIMT (no changes needed); only the gates and vendor mappings were missing.
Verification (RX 7900 XTX / gfx1100, Windows, ROCm 7.1):
Not yet verified: CDNA hardware, Linux.
Related: ggml-org/llama.cpp#26914 (upstream int8 convrot proposal), leejet/stable-diffusion.cpp#1857.
LLM Disclose: YES, used GLM-5.3 for the grunt work