If the design is built with current versions of Vivado, e.g. 2025.1, multiple accesses to the bram from the PS will lock up the bus and hang the system. A solution to this is to replace axi_bram.vhd with the Xilinx AXI Bram Controller and Block Memory Generator IP. There are some good discussions of AXI issues on the blog that has this post: https://zipcpu.com/blog/2021/05/22/vhdlaxil.html. Fundamentally, it seems getting AXI right is not as easy as one might think.
If the design is built with current versions of Vivado, e.g. 2025.1, multiple accesses to the bram from the PS will lock up the bus and hang the system. A solution to this is to replace axi_bram.vhd with the Xilinx AXI Bram Controller and Block Memory Generator IP. There are some good discussions of AXI issues on the blog that has this post: https://zipcpu.com/blog/2021/05/22/vhdlaxil.html. Fundamentally, it seems getting AXI right is not as easy as one might think.