feat(pt2): add torch.compile support for FlagGems kernels used by vLLM 0.24 - #6013
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Make the FlagGems kernels that vLLM 0.24 routes into its compiled graph
(RMSNorm, fused-add RMSNorm, SiLU/GELU-and-mul, in-place RoPE, MoE
primitives, MHC) traceable by Dynamo/Inductor without re-implementing any
kernel in torch.
* flag_gems/pt2/: `torch.library.triton_op` + `wrap_triton` contracts that
launch the ORIGINAL LibEntry `.jit_function` / Autotuner objects; declarative
`CompileOpSpec` manifest; pointwise families materialised outside the graph.
* utils/pointwise_dynamic.py: `PointwiseKernelMaterialization` + `materialize()`
so PT2 can obtain the generated JITFunction without reaching into wrapper
globals; codegen emits `program_id`/`num_programs` by name.
* utils/codegen_config_utils.py: `get_heuristics_for_num_warps_fn()`.
* ops/rms_norm.py, fused/fused_add_rms_norm.py, fused/rotary_embedding.py:
import `program_id` by name instead of the `ext.` module alias — Inductor's
user-kernel closure dump drops non-triton module aliases and the subprocess
recompile fails with NameError('ext is not defined') (REPRO on torch 2.11).
* modules/{activation,normalization,rotary_embedding}.py: drop bare
`logger.debug` on the entry paths Dynamo traces (Unsupported: logging.Logger
method). Debug-only; numerics and control flow unchanged.
Eager execution is byte-identical (verified torch.equal on all four hot ops).
Same design as the 0.20.2 delivery; pt2/ contracts are hunk-identical to it.
Signed-off-by: JiaryCoder <jiary.zhang@icloud.com>
Expand program_id and num_programs helpers at the compile-facing kernel and pointwise codegen call sites. Keep the int64 conversion explicit and remove helper imports so generated kernels depend only on triton.language for grid indices. Validation: repository pre-commit checks passed; all 13 replacements preserve the AST after expanding the original helpers; 27 pointwise source-generation combinations passed syntax and AST equivalence checks. GPU compilation and numerical tests were not run on this host.
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PR Category
Other
Type of Change
New Feature
Description
为 FlagGems 中会被 vLLM 0.24 及 vLLM 0.20.2 编译路径直接追踪的 kernel 提供透明的 torch.compile
契约(PT2 contracts),不修改任何 kernel 数学实现。
背景:vLLM 0.24 的
custom_ops=all会以 fullgraph AOT 追踪CustomOp.forward_oot。当前 FlagGems 的公开启动器在该路径上不可追踪,会在
profile_run阶段中断:LibEntry.run(Unsupported method call: __getitem__)、入口处的裸logger.debug(
logging.Logger method not supported)、以及 kernel 内的ext.模块别名(Inductor 对非 triton 模块的闭包 dump 会丢失该别名,子进程重编译报
NameError('ext is not defined');torch 2.11 上可复现)。改动:
flag_gems/pt2/(新增)——torch.library.triton_op+wrap_triton包裹原始
LibEntry.jit_function/ Autotuner 对象:RMSNorm、fused-add RMSNorm、pointwise 族(SiLU/GELU-and-mul)、in-place RoPE、MoE 基础算子(
topk_softmax、moe_sum、grouped-topk 路由)、MHC。附声明式CompileOpSpecmanifest;pointwise 的 plan 在图外物化。
utils/pointwise_dynamic.py——新增PointwiseKernelMaterialization与materialize();codegen 直接生成tl.program_id(0).to(tl.int64)/tl.num_programs(0).to(tl.int64),保留原 helper 的 64 位整数语义。utils/codegen_config_utils.py——新增get_heuristics_for_num_warps_fn()。ops/rms_norm.py、fused/fused_add_rms_norm.py、fused/rotary_embedding.py——ext.program_id(0)改为tl.program_id(0).to(tl.int64),移除对应 helper 导入;显式区分 Triton 原生函数和 FlagGems 原有的 64 位封装。
modules/{activation,normalization,rotary_embedding}.py——删除入口路径上的裸
logger.debug(仅日志,数值/控制流不变)。eager 行为与之前完全一致(
torch.equal验证)。设计与pt2/契约内容与内部0.20.2 交付件(
flaggems_pt2_final_20260901)逐字节一致,仅按本仓 lint 要求(black/isort)做格式整理并更新部分注释。
Issue
Related PR:
Progress
Validation for the explicit int64 follow-up
本次追加提交涉及 4 个文件、13 处调用或代码生成模板。展开原 helper 函数体后,
修改前后的 AST 一致;pointwise 的 27 种生成组合通过源码语法与 AST 等价检查。
仓库配置的 pre-commit 检查通过(Flake8、isort、black、black-jupyter、空白及文件结尾检查)。
当前机器没有 PyTorch/Triton,未重新执行 GPU 数值、torch.compile 或端到端测试;
下方性能及 parity 数据来自此前的验证。
Performance
未改动任何 kernel 数学实现;本 PR 不引入性能变化。compile 模式下 eager/compiled
parity(rms_norm、fused_add_rms_norm、silu_and_mul、gelu_and_mul、rope(in-place)、
topk_softmax、moe_sum,bf16,NVIDIA,torch 2.11 / triton 3.6)max|diff| = 0.0。
端到端(经 vllm-plugin-FL):MiniCPM5-1B TP=2、
custom_ops=all冷编译 14.2 s,51/51 PIECEWISE + 51/51 FULL CUDA graph 捕获;Qwen3.6-35B-A3B eager vs compile
tie-aware cross-phase 16/16 位置逐位一致。