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[libc] Set Root PAS in AArch64 baremetal page tables - #1037

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[libc] Set Root PAS in AArch64 baremetal page tables#1037
MarkMurrayARM wants to merge 4 commits into
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MarkMurrayARM:llvmlibc-crt0-rme-root-pas

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@MarkMurrayARM

@MarkMurrayARM MarkMurrayARM commented Sep 3, 2026

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Set descriptor bit 11 for AArch64 baremetal normal-memory block mappings so FEAT_RME interprets them as Root PAS rather than Secure PAS. Keep NS clear and leave R-profile mappings unchanged.

@MarkMurrayARM
MarkMurrayARM requested a review from a team as a code owner September 3, 2026 09:04
Comment thread arm-software/embedded/llvmlibc-support/crt0/memory_8a.h Outdated
Comment thread arm-software/embedded/llvmlibc-support/crt0/memory_8a.h Outdated
@MarkMurrayARM MarkMurrayARM changed the title Llvmlibc crt0 rme root pas [libc] Set Root PAS in AArch64 baremetal page tables Sep 3, 2026
@voltur01

voltur01 commented Sep 3, 2026

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Thank you for addressing my comments!

@smithp35 smithp35 left a comment

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Only one comment nit. Otherwise LGTM

unsigned long image_attrs = 0x405; // Index = 1, AF=1
// Page occupied by the image. AArch64 A-profile startup can run at EL3 on
// FVPs or real hardware. With FEAT_RME, descriptor bit 11 is NSE rather than
// nG; NS=0,NSE=1 selects Root PAS for EL3 execution. Without RME, setting

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From what I can tell at EL2 and EL3 all translations are global. Without RME the bit is Res(0) but should be ignored by the hardware. With RME at EL3 bit 11 is the NSE bit. At EL0 and EL1 the bit is used for NG.

Perhaps alter the comment to:
"At EL3 with FEAT_RME, descriptor bit 11 is NSE, otherwise it is RES(0) and ignored by the hardware. At EL0 and EL1 bit 11 is non-global, but as we don't change ASID this has no effect."

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LGTM thanks for the update.

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3 participants