mt6572-mainline release#51
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Add a header for the resets on the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
Add a header for the clocks on the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
Add a header for the pinctrl on the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
Add a header for the IOMMU ports on the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
Add a header for the power domains on the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
mt6572's I2C controllers have two physically separate APDMA channel register blocks per bus: TX at the DMA base address declared in the SoC DTSI's second reg entry, and RX at a different address that the driver previously assumed was reachable at a fixed offset from TX. Add mediatek,mt6572-i2c to the compatible enum, document the third reg entry for the RX DMA channel, and conditionally require exactly three reg entries when the compatible is mediatek,mt6572-i2c (every other SoC still requires two). The driver-side support for the third reg entry lands in a follow-up patch. Signed-off-by: Custom Firmware <gabin278@gmail.com>
Add support for the watchdog reset controller on the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
XXX: probably unsquash Signed-off-by: rva3 <rva333@protonmail.com>
Add pinctrl driver for the mt6572 SoC. Co-developed-by: Custom Firmware <gabin278@gmail.com> Signed-off-by: rva3 <rva333@protonmail.com>
XXX: fixup other pds Signed-off-by: rva3 <rva333@protonmail.com>
The mt65xx SoC family uses an earlier version of the SMI, which we refer to as gen 0. Unlike gen 1 or gen 2, gen 0 requires simultaneous access to two distinct MMIO ranges: an AO base for IOMMU configuration and ext base for OSTD, FIFO, and bandwidth limiter setup. Remove the union in struct mtk_smi to allow simultaneous use of smi_ao_base and base. Refactor the probe function into a switch statement to handle the different generation requirements cleanly. Signed-off-by: rva3 <rva333@protonmail.com>
Add platform data for the SMI common on the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
The mt65xx SoC family utilizes a larb design that incorporates features from both gen 1 and gen 2 architectures. Introduce a specific configuration callback for this generation, which implements the port security configuration typical for gen 1 while including the ostd settings found in gen 2. Additionally, add a bandwidth calibration flag for some of the gen 0 SoCs. Signed-off-by: rva3 <rva333@protonmail.com>
Add platform data for the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
The mt65xx SoC family utilizes an earlier version of the IOMMU which shares the same v1 architecture but has minor hardware differences compared to mt2701. Introduce mtk_iommu_type to distinguish between mt2701 and mt65xx variants and apply the necessary logic. Signed-off-by: rva3 <rva333@protonmail.com>
Add platform data for the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
Signed-off-by: rva3 <rva333@protonmail.com>
XXX: fixme Signed-off-by: rva3 <rva333@protonmail.com>
Add platform data for the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
XXX: maybe we should drop this?.. Signed-off-by: rva3 <rva333@protonmail.com>
Add platform data for the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
The RDMA SIZE_CON0 and SIZE_CON1 values vary across different SoCs. Prepare for supporting new SoCs by moving these values into the mtk_disp_rdma_data and updating existing SoC data to use their respective values. Signed-off-by: rva3 <rva333@protonmail.com>
The RDMA uses different values for memory formats. Currently, these are hardcoded using macros. Move the format conversion logic into function pointer instead of raw call. This allows other SoCs to provide their own mapping logic without breaking others. Also drop useless parameter in the rdma_fmt_convert method. Signed-off-by: rva3 <rva333@protonmail.com>
Add support for the display RDMA in the mt6572 SoC. This requires setting size_con0 and size_con1 registers to zero, unlike other SoCs. Signed-off-by: rva3 <rva333@protonmail.com>
Add platform data for the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
Add platform data for the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
Signed-off-by: rva3 <rva333@protonmail.com>
Add a minimal MIPI-DSI panel driver for the OriseTech OTM8018B IC supporting BOYI and DJN vendors. Co-developed-by: rva3 <rva333@protonmail.com> [rva3: add multiple panels support] Signed-off-by: rva3 <rva333@protonmail.com> Signed-off-by: Custom Firmware <gabin278@gmail.com>
There's SoCs like mt6572 which have only 2 sensors. Signed-off-by: rva3 <rva333@protonmail.com>
The auxadc thermal system on MT67XX and MT68XX SoCs seems to sit in between versions V1 and V2. The efuse layout is mostly V1, but it has additional entries for the likes of ADC_OE which is only seen otherwise in the V2 layout. The downstream driver's version of raw_to_mcelsius uses a modified formula of the V2 one, but there is a VTS value for each sensor, slightly adjusted values and slope correction. Add support for this. Signed-off-by: bengris32 <bengris32@protonmail.ch>
… cell Some MediaTek SoCs, such as the mt6572, lack a dedicated ID cell to distinguish the chip variant. However, they have a performance level efuse that can be used to determine the exact chip variant. To handle this, introduce a 'dt_compat' field and an associated macro to filter the SoC data table by the machine compatible property. This prevents data collisions if a different chip shares the same efuse cell value. Additionally, because the register containing the PTP level may pack other unrelated configuration bits, introduce a 'cell_mask' array to mask out the required bits during matching. Also add support for the mt6572 SoC variants using the new macro and bitmask filtering. Signed-off-by: rva3 <rva333@protonmail.com>
Add support for the "915" chip ID (a gt9xx-legacy variant found on MediaTek MT6572-based phones such as the Prestigio MultiPhone PAP5500 DUO). The chip identifies as ID="915", firmware version 0x1040, and uses the gt911-family 186-byte config layout (8-bit checksum at config[184], fresh bit at config[185]). Three chip-specific workarounds are required: 1. Split goodix_i2c_read() into two single-msg transfers with a 50us gap. The mainline goodix.c read path uses a 2-msg i2c_transfer() that on mtk-i2c emits a HW repeated-START between the address write and the data read. This chip variant NACKs the address-phase byte after the repeated-START. The GT911 Programming Guide v0.1 section 2.2 documents the canonical read sequence as Stop+Start, with the Stop optional but a fresh Start mandatory; splitting forces mtk-i2c to emit exactly that pattern. The dual-APDMA fix earlier in this series does not remove the need for the split: verified empirically by reverting only the split with the rest of the series applied, the chip-ID read at reg 0x8140 fails with -ETIMEDOUT. 2. Hold reset low for at least 2ms before sampling the I2C address strap. The GT911 spec gives T3 (reset-deassert to address-latch) as >100us, which is marginal on this variant. BSP uses 2ms, so do the same. 3. On "915" the chip boots in a non-scanning state until the host rewrites its config with config_fresh=1. Re-send the chip's own read-back config with the fresh bit set on probe so it transitions to running mode. Signed-off-by: Custom Firmware <gabin278@gmail.com>
Move PWR_*_BIT macros from the driver to the heade. This allows these definitions to be reused by platsmp code for the CPU power management. Signed-off-by: rva3 <rva333@protonmail.com>
Add .cpu_can_disable, .cpu_disable, .cpu_die and .cpu_kill hooks to mt6589_smp_ops. The core power state is managed via the SPM. Also update mtk_boot_secondary to support waking up powered-down cores. Signed-off-by: rva3 <rva333@protonmail.com>
Add support for hotplug for the second core on the mt6572 SoC. Signed-off-by: rva3 <rva333@protonmail.com>
The official company name is MediaTek Inc. Change the devicetree info to reflect real name.
The mc3236 is used in low-cost android tablets. Introduce new platform data struct with chip_id, product_id and scale values for the chip. Signed-off-by: rva3 <rva333@protonmail.com>
The Rohm RPR-0400 is an older sibling of the RPR-0521 found on some MT6572-class boards (e.g. Prestigio MultiPhone PAP5500 DUO). It shares the broad register layout - control registers starting at 0x40 and 16-bit little-endian PS / ALS data at 0x44 / 0x46 / 0x48 - but uses a different control-register split and exposes no readable ID register. This driver supports polled IIO reads of proximity (in_proximity_raw) and the two ambient-light photodiode channels (in_intensity_both_raw, in_intensity_ir_raw). Runtime PM puts the chip in standby when idle. Downstream lux computation is left to userspace. Signed-off-by: Custom Firmware <gabin278@gmail.com>
Co-developed-by: Custom Firmware <gabin278@gmail.com> Signed-off-by: rva3 <rva333@protonmail.com>
XXX: unsquash Signed-off-by: rva3 <rva333@protonmail.com>
XXX: unsquash Signed-off-by: rva3 <rva333@protonmail.com>
Signed-off-by: rva3 <rva333@protonmail.com>
Add a board DTS for the Prestigio MultiPhone PAP5500 DUO, an
MT6572-based phone.
What's wired up:
- 512 MB LPDDR2 DRAM, 4 GB eMMC (mmc0), microSD slot (mmc1).
- UART0 console at 921600.
- MT6323 PMIC with its regulators.
- USB OTG (musb on t-phy0).
- Battery: simple-battery with the OCV-capacity curve from BSP.
- Haptic: regulator-haptic on the vibrator rail.
- Display: OriseTech OTM8018B MIPI-DSI panel via mediatek-drm.
- Touch: Goodix GT911 on I2C-1 0x5D, INT on GPIO 129 (alt-2
EINT1), reset on GPIO 57.
- Volume rocker keypad; PMIC home key disabled.
- mt6323keys for the PMIC-side power button.
VGP1 is intentionally not regulator-always-on. The stock firmware
leaves VGP1 off at boot and powers it on at touch-driver probe so
the chip's first VDD ramp happens with driver-controlled INT and
reset pins. With always-on, the chip POR's at boot with floating
pins and is wedged off its expected I2C address on first probe.
The touchscreen and panel nodes request VGP1 explicitly via their
*-supply phandles.
Pin assignments and chip presence confirmed against the stock
Android kernel via mtgpio sysfs and a small disassembly of the
stock vmlinux (touch INT pin number and EINT input number come
from gtp_reset_guitar / tpd_i2c_probe in the running BSP image).
Signed-off-by: Custom Firmware <gabin278@gmail.com>
Signed-off-by: rva3 <rva333@protonmail.com>
XXX: verify if we actually need this... Signed-off-by: rva3 <rva333@protonmail.com>
Co-developed-by: Custom Firmware <gabin278@gmail.com> Signed-off-by: rva3 <rva333@protonmail.com>
Signed-off-by: rva3 <rva333@protonmail.com>
This is needed for cases where bootloader didn't clear it, which leads to handler being stuck. Signed-off-by: Dinolek <git@dinolek.me>
Some SoCs may be fused with different PTP level for the GPU. The standard way to handle different OPP entries is 'opp-supported-hw' property. Add support for the NVMEM cell parsing and using OPP config based on the actual hardware speedbin. Signed-off-by: rva3 <rva333@protonmail.com>
The MediaTek mt6323 PMIC includes an AUXADC used for battery voltage, temperature, and other internal measurements. Add the devicetree binding documentation and the associated header file defining the ADC channel constants. Also change description to the 'MT6350 series and similar' because the binding already includes more than mt635x series PMICs. Signed-off-by: Roman Vivchar <rva333@protonmail.com>
The mt6323 AUXADC is a 15-bit ADC used for system monitoring. This driver provides support for reading various channels including battery and charger voltages, battery and chip temperature, current sensing and accessory detection. Add a driver for the AUXADC found in the MediaTek mt6323 PMIC. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
The mt6323 PMIC includes an AUXADC. Register the AUXADC in the mt6323 devices array to allow the corresponding driver to probe using compatible string. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
Add the devicetree node for the mt6323 AUXADC. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
Add support for the EFUSE controller found in the Mediatek MT6323 PMIC. The MT6323 EFUSE stores 24 bytes of hardware-related data, such as thermal sensor calibration values. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
The mt6323 PMIC includes an EFUSE. Register the EFUSE in the mt6323 devices array to allow the corresponding driver to probe using compatible string. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
Add a new driver to support thermal monitoring on MediaTek PMICs. The driver retrieves calibration data from EFUSE, calculates the temperature using a linear interpolation, and registers the device with the thermal framework. Initial support is added for the mt6323 PMIC. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
The mt6323 PMIC temperature can be measured using AUXADC channel. Register the thermal in the mt6323 devices array to allow the corresponding driver to probe using compatible string. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
Add the efuse node for the mt6323 efuse. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
Add the devicetree node for the mt6323 thermal. Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation) Signed-off-by: Roman Vivchar <rva333@protonmail.com>
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for reference