TeamYogaBlade2 Linux 6.16 Release by akku1139 · Pull Request #48 · TeamYogaBlade2/linux

akku1139 · 2026-06-21T14:06:08Z

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…0-F)

… reserved_memory node

This reverts commit 7e0b29a.

This reverts commit 0533855.

* pinctrl: mediatek: init mt6320 driver * dt-bindings: soc: mediatek: pwrap: Add compatible for MT6589 SoC * arm: dts: mediatek: mt6589: add pwrap node * arm: dts: mediatek: mt6589: add pwrap reset * arm: dts: mediatek: mt6589: add pwrap-bridge reset * wip: soc: mediatek: pwrap: add mt6589 support * wip: soc: mediatek: pwrap: fix mt6589 * wip: soc: mediatek: pwrap: mt6589 and mt6320 porting * wip: soc: mediatek: pwrap: add mt6320 regs * wip: soc: mediatek: pwrap: add mt6589 regs * soc: mediatek: pwrap: rename PWRAP_MT8135_BRIDGE_* to PWRAP_BRIDGE_* because MT6589 also have these registers * soc: mediatek: pwrap: fix dew_regs for MT6589 * soc: mediatek: pwrap: add more PERI_PWRAP_BRIDGE registers MT6589 and MT8135 have PWRAP bridge registers with the same name and address. * soc: mediatek: pwrap: fix pwrap_regs for MT6589 The unique registers of MT8135 are the same as those of MT6589, so they have been made common. PWRAP_DVFS_ADR0 to PWRAP_DVFS_WDATA7 were in the MT8173 part, but these registers are used in many SoCs, not just the MT6589. * soc: mediatek: pwrap: mt6589 cleanup * soc: mediatek: pwrap: fix MT6320 regops * mfd: mt6320: add register index based on: https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/core/include/mach/mt_pmic.h#L56-L549 * arm: dts: mediatek: mt6589-lenovo-blade: add pmic * dt-bindings: soc: mediatek: pwrap: PMIC peripherals for MT6589 * dt-bindings: mfd: mediatek: add MT6320 binding * arm: configs: lenovo-blade: enable PWAP * soc: mediatek: fix mt6589/mt6320 * clk: mediatek: reindex mt6589 clocks * dt-bindings: mfd: mediatek: move mt6320 * mfd: mt6397: Add initial support for MT6320 (maybe broken) * pinctrl: mediatek: add MT6320 support * arm: configs: lenovo-blade: add CONFIG_MFD_MT6397 * arm: dts: lenovo-blade: add MT6320 Pinctrl * dt-bindings: reset: mt6589: format * mfd: mt6397-core: add MT6320 * mfd: mt6397-core: add mt6320 includes * mfd: mt6397-core: add mt6320 rtc defs * dt-bindings: mfd: mt6397: add mediatek,mt6320-rtc * arm: dts: mediatek: mt6589-lenovo-blade: add rtc * mfd: mt6320: add irq enum * mdf: rtc-mt6397: add mt6320 support * dt-bindings: input: mediatek,pmic-keys: add mediatek,mt6320-keys * mfd: mt6397-core: add mt6320-keys * arm: dts: mediatek: mt6589-lenovo-blade: add mt6320keys * mfd: mt6320: fix syntax * mfd: mt6397-core: fix mt6320 rtc * mfd: mt6397: Properly fix CID of MT6328, MT6331 and MT6332 CIDs set for MT6328, MT6331 and MT6332 are not appropriate. Many Android downstream kernels define CID as below, MT6328: #define PMIC6328_E1_CID_CODE 0x2810 #define PMIC6328_E2_CID_CODE 0x2820 #define PMIC6328_E3_CID_CODE 0x2830 MT6331/MT6332: #define PMIC6331_E1_CID_CODE 0x3110 #define PMIC6331_E2_CID_CODE 0x3120 #define PMIC6331_E3_CID_CODE 0x3130 #define PMIC6332_E1_CID_CODE 0x3210 #define PMIC6332_E2_CID_CODE 0x3220 #define PMIC6332_E3_CID_CODE 0x3230 The current configuration incorrectly uses the revision code as the CID. Therefore, the driver cannot detect the same PMIC of different revisions. (E1/E2 for MT6328, E1/E3 for MT6331/MT6332) Based on these, the CID of MT6328, MT6331 and MT6332 should be corrected. Additionally, the incorrect MT6331/MT6332 CID overlaps with the MT6320's actual CID: #define PMIC6320_E1_CID_CODE 0x1020 #define PMIC6320_E2_CID_CODE 0x2020 This causes a conflict in the switch-case statement of mt6397-irq.c, this prevents adding support for MT6320. Link: https://github.com/parthibx24/android_kernel_mediatek_k35/blob/4853d1fd9e40563573fa6d6b32b75d571a95e2b7/drivers/misc/mediatek/power/mt6735/pmic.h#L10-L12 Link: https://github.com/meizuosc/m75/blob/80ef1d26c5d73e131d064138ed09ff5a2be2bed8/mediatek/platform/mt6595/kernel/core/include/mach/pmic_mt6331_6332_sw.h#L9-L15 Link: https://github.com/toffyjan/android_Ticwatch_S_mooneye/blob/4f2a73b26f3821afc452cdce660cdbc73daf4e4a/arch/arm/mach-mt2601/include/mach/pmic_mt6320_sw.h#L29-L30 Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com> * mfd: mt6320: fix * arm: dts: mediatek: split mt6320 * arm: dts: mediatek: mt6320: add license header * arm: configs: lenovo-blade: add CONFIG_POWER_RESET_MT6323 * arm: dts: mediatek: mt6320: fix fix * arm: dts: mediatek: mt6320: fix fix fix * arm: configs: lenovo-blade: add CONFIG_PINCTRL_MT6320 * pinctrl: mt6320: Add pinfunc header file for mt6320 * dt-bindings: mfd: mt6397: add mediatek,mt6320-regulator * mfd: mt6397-core: add mt6320-regulator * arm: configs: lenovo-blade: add needed * Input: mtk-pmic-keys: add mt6320 support * WIP: MT6320 regulator * regulator: mt6320: add header * regulator: mt6320: replace based on mt6323 * wip: regulator: mt6320: early porting * regulator: mt6320: todo note * soc: mediatek: mtk-pmic-wrap: drop pwrap_mt6589_init_soc_specific same as pwrap_mt8135_init_soc_specific, only watchdog timeout is different Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com> * regulator: mt6320: by Claude * regulator: mt6320: Claude 2 * regulator: mt6320: Claude 3 Assisted-by: DeepSeek V4 Pro Assisted-by: Claude Sonnet 4.6 Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com> --------- Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>

Some MediaTek SoCs split their I2C APDMA into two physically separate channels per bus, each with its own register block using TX-side offsets regardless of direction. mt6572 is one such SoC. The existing driver assumes a single unified APDMA channel where RX and TX live at RX_*/TX_* offsets within the same block, which is correct for the SoCs already in mainline but cannot reach the RX channel on dual-channel SoCs. Add a per-SoC compatible flag dma_separate_rx plus a second ioremap pointer pdmabase_rx for the RX channel. When the flag is clear (every currently supported SoC), pdmabase_rx aliases pdmabase and the RX-direction offsets collapse back to OFFSET_RX_MEM_ADDR / OFFSET_RX_LEN / OFFSET_RX_4G_MODE — byte-for-byte identical writes to the pre-patch code path. No behaviour change for unified-DMA SoCs. When the flag is set, the driver ioremaps the third reg entry as the RX channel and routes RX writes through that block using OFFSET_TX_* offsets (the RX channel uses the same TX-style register layout in its own block). DMA_START_EN is issued on the RX channel for read transfers; the TX channel still starts WR/WRRD paths as before. No SoC opts into this layout in this commit. Co-developed-by: rva3 <rva333@protonmail.com> [rva3: fix DMA enable for WRRD] Signed-off-by: rva3 <rva333@protonmail.com> Signed-off-by: Custom Firmware <gabin278@gmail.com>

MediaTek mt65xx family SoCs have no auto restart, however, they still support the WRRD mode in the hardware. Because auto_restart is set to 0, the WRRD mode will be never enabled, leading to read errors using i2cget with explicit register. Fix this by removing auto_restart check from the WRRD enable path. Signed-off-by: rva3 <rva333@protonmail.com>