TeamYogaBlade2 · akku1139 · Jan 2, 2026 · Mar 4, 2026 · Mar 8, 2026 · Mar 3, 2026
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -23,6 +23,7 @@ properties:
           - enum:
               - mediatek,mt2701-mmsys
               - mediatek,mt2712-mmsys
+              - mediatek,mt6589-dispsys
               - mediatek,mt6765-mmsys
               - mediatek,mt6779-mmsys
               - mediatek,mt6795-mmsys

diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml
@@ -28,7 +28,6 @@ properties:
               - mediatek,mt2712-mfgcfg
               - mediatek,mt2712-vdecsys
               - mediatek,mt2712-vencsys
-              - mediatek,mt6589-dispsys
               - mediatek,mt6589-imgsys
               - mediatek,mt6589-mfgsys
               - mediatek,mt6589-vdecsys

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -24,6 +24,7 @@ properties:
     oneOf:
       - enum:
           - mediatek,mt2701-dsi
+          - mediatek,mt6589-dsi
           - mediatek,mt7623-dsi
           - mediatek,mt8167-dsi
           - mediatek,mt8173-dsi

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -23,6 +23,7 @@ properties:
     oneOf:
       - enum:
           - mediatek,mt2701-disp-ovl
+          - mediatek,mt6589-disp-ovl
           - mediatek,mt8173-disp-ovl
           - mediatek,mt8183-disp-ovl
           - mediatek,mt8192-disp-ovl

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -25,6 +25,7 @@ properties:
     oneOf:
       - enum:
           - mediatek,mt2701-disp-rdma
+          - mediatek,mt6589-disp-rdma
           - mediatek,mt8173-disp-rdma
           - mediatek,mt8183-disp-rdma
           - mediatek,mt8195-disp-rdma

diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml
@@ -28,8 +28,12 @@ properties:
 
         # AU Optronics Corporation 8.0" WUXGA TFT LCD panel
       - auo,b080uan01
+        # BOE Technology 10.1" WXGA panel with Himax HX8896-A01 TCON
+      - boe,hx8896-a01
         # Boe Corporation 8.0" WUXGA TFT LCD panel
       - boe,tv080wum-nl0
+        # CMI 10.1" WXGA panel with Himax HX8896-A01 TCON
+      - innolux,hx8896-a01
         # Innolux P079ZCA 7.85" 768x1024 TFT LCD panel
       - innolux,p079zca
         # JDI FHD_R63452 1080x1920 5.2" IPS LCD Panel

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -72,6 +72,7 @@ properties:
       - enum:
           - mediatek,mt2701-m4u  # generation one
           - mediatek,mt2712-m4u  # generation two
+          - mediatek,mt6589-m4u
           - mediatek,mt6779-m4u  # generation two
           - mediatek,mt6795-m4u  # generation two
           - mediatek,mt6893-iommu-mm         # generation two

diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -31,6 +31,7 @@ properties:
       - enum:
           - mediatek,mt2701-smi-common
           - mediatek,mt2712-smi-common
+          - mediatek,mt6589-smi-common
           - mediatek,mt6779-smi-common
           - mediatek,mt6795-smi-common
           - mediatek,mt6893-smi-common
@@ -51,9 +52,6 @@ properties:
           - const: mediatek,mt7623-smi-common
           - const: mediatek,mt2701-smi-common
 
-  reg:
-    maxItems: 1
-
   power-domains:
     maxItems: 1
 
@@ -86,6 +84,24 @@ required:
   - clock-names
 
 allOf:
+  - if:  # Generation 0 HW (mt6589)
+      properties:
+        compatible:
+          contains:
+            const: mediatek,mt6589-smi-common
+    then:
+      properties:
+        reg:
+          items:
+            - description: SMI AO base
+            - description: SMI base
+          minItems: 2
+          maxItems: 2
+    else:
+      properties:
+        reg:
+          maxItems: 1
+
   - if:  # only for gen1 HW
       properties:
         compatible:

diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -19,6 +19,7 @@ properties:
       - enum:
           - mediatek,mt2701-smi-larb
           - mediatek,mt2712-smi-larb
+          - mediatek,mt6589-smi-larb
           - mediatek,mt6779-smi-larb
           - mediatek,mt6795-smi-larb
           - mediatek,mt6893-smi-larb

diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -26,6 +26,7 @@ properties:
     enum:
       - mediatek,mt2701-disp-mutex
       - mediatek,mt2712-disp-mutex
+      - mediatek,mt6589-disp-mutex
       - mediatek,mt6795-disp-mutex
       - mediatek,mt8167-disp-mutex
       - mediatek,mt8173-disp-mutex

diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi
@@ -13,5 +13,44 @@
 		height = <800>;
 		stride = <(1280 * 2)>;
 		format = "r5g6b5";
+		//status = "disabled";
+	};
+
+	reg_panel: regulator-panel {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.2V";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+};
+
+&dsi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	panel@0 {
+		compatible = "boe,hx8896-a01";
+		/*
+		 * or innolux,hx8896-a01
+		 * TODO: panel mux
+		 */
+		reg = <0>;
+		power-supply = <&reg_panel>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&dsi_out>;
+			};
+		};
+	};
+
+	port {
+		dsi_out: endpoint {
+			remote-endpoint = <&panel_in>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/clock/mt6589-clk.h>
 #include <dt-bindings/reset/mt6589-resets.h>
 #include <dt-bindings/pinctrl/mt6589-pinfunc.h>
+#include <dt-bindings/memory/mt6589-larb-port.h>
 #include <dt-bindings/power/mt6589-power.h>
 
 / {
@@ -384,6 +385,16 @@
 			clock-names = "system-clk", "rtc-clk";
 		};
 
+		mipi_tx0: dsi-phy@10012000 {
+			compatible = "mediatek,mt7623-mipi-tx",
+				     "mediatek,mt2701-mipi-tx";
+			reg = <0x10012000 0x90>;
+			clocks = <&dispsys CLK_DISP1_DSI_DIGITAL_LANE>; // uart_clk
+			clock-output-names = "mipi_tx0_pll";
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+		};
+
 		pwrap: pwrap@1000f000 {
 			compatible = "mediatek,mt6589-pwrap";
 			reg = <0x1000f000 0x1000>,
@@ -407,6 +418,33 @@
 			reg = <0x10200100 0x1c>;
 		};
 
+		smi_common: smi@10202000 {
+			compatible = "mediatek,mt6589-smi-common";
+			reg = <0x10202000 0x1000>, <0x1000e000 0x1000>;
+			clocks = <&infracfg CLK_INFRA_SMI>,
+				 <&infracfg CLK_INFRA_SMI>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		iommu: iommu@10205000 {
+			compatible = "mediatek,mt6589-m4u";
+			reg = <0x10205000 0x200>,
+			      <0x10205200 0x600>,
+			      <0x10205800 0x600>;
+			reg-names = "global", "m4u0", "m4u1";
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
+			interrupt-names = "m4u0", "m4u1", "m4ul2", "m4ul2-sec";
+			clocks = <&infracfg CLK_INFRA_M4U>;
+			clock-names = "bclk";
+			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+					 <&larb3>, <&larb4>;
+			#iommu-cells = <1>;
+		};
+
 		gic: interrupt-controller@10211000 {
 			compatible = "arm,cortex-a7-gic";
 			interrupt-controller;
@@ -536,6 +574,119 @@
 			clock-names = "source", "hclk";
 			status = "disabled";
 		};
+
+		ovl: ovl@14003000 {
+			compatible = "mediatek,mt6589-disp-ovl";
+			reg = <0x14003000 0x1000>;
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&dispsys CLK_DISP0_OVL_ENGINE>,
+				 <&dispsys CLK_DISP0_OVL_SMI>;
+			iommus = <&iommu MT6589_M4U_PORT_OVL_CH0>,
+				 <&iommu MT6589_M4U_PORT_OVL_CH1>,
+				 <&iommu MT6589_M4U_PORT_OVL_CH2>,
+				 <&iommu MT6589_M4U_PORT_OVL_CH3>;
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		rdma0: rdma@14006000 {
+			compatible = "mediatek,mt6589-disp-rdma";
+			reg = <0x14006000 0x1000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&dispsys CLK_DISP0_RDMA0_ENGINE>,
+				 <&dispsys CLK_DISP0_RDMA0_SMI>,
+				 <&dispsys CLK_DISP0_RDMA0_OUTPUT>;
+			iommus = <&iommu MT6589_M4U_PORT_RDMA0>;
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		rdma1: rdma@14007000 {
+			compatible = "mediatek,mt6589-disp-rdma";
+			reg = <0x14007000 0x1000>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&dispsys CLK_DISP0_RDMA1_ENGINE>,
+				 <&dispsys CLK_DISP0_RDMA1_SMI>,
+				 <&dispsys CLK_DISP0_RDMA1_OUTPUT>;
+			iommus = <&iommu MT6589_M4U_PORT_RDMA1>;
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		mutex: mutex@14011000 {
+			compatible = "mediatek,mt6589-disp-mutex";
+			reg = <0x14011000 0x1000>;
+			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
+			/* not found in clock list */
+			clocks = <&clk26m>;
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		dsi: dsi@1400d000 {
+			compatible = "mediatek,mt6589-dsi";
+			reg = <0x1400d000 0x1000>;
+			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&dispsys CLK_DISP1_DSI_ENGINE>,
+				 <&dispsys CLK_DISP1_DSI_DIGITAL>,
+				 <&mipi_tx0>;
+			clock-names = "engine", "digital", "hs";
+			phys = <&mipi_tx0>;
+			phy-names = "dphy";
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+			status = "disabled";
+		};
+
+		larb0: larb@17001000 {
+			compatible = "mediatek,mt6589-smi-larb";
+			reg = <0x17001000 0x1000>;
+			mediatek,smi = <&smi_common>;
+			mediatek,larb-id = <0>;
+			clocks = <&vencsys CLK_VENC_VEN>,
+				 <&vencsys CLK_VENC_VEN>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		larb1: larb@16010000 {
+			compatible = "mediatek,mt6589-smi-larb";
+			reg = <0x16010000 0x1000>;
+			mediatek,smi = <&smi_common>;
+			mediatek,larb-id = <1>;
+			clocks = <&vdecsys CLK_VDEC0_VDE>,
+				 <&vdecsys CLK_VDEC1_SMI>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		larb2: larb@14010000 {
+			compatible = "mediatek,mt6589-smi-larb";
+			reg = <0x14010000 0x1000>;
+			mediatek,smi = <&smi_common>;
+			mediatek,larb-id = <2>;
+			clocks = <&dispsys CLK_DISP0_LARB2_SMI>,
+				 <&dispsys CLK_DISP0_LARB2_SMI>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		larb3: larb@15001000 {
+			compatible = "mediatek,mt6589-smi-larb";
+			reg = <0x15001000 0x1000>;
+			mediatek,smi = <&smi_common>;
+			mediatek,larb-id = <3>;
+			clocks = <&imgsys CLK_IMAGE_LARB3_SMI>,
+				 <&imgsys CLK_IMAGE_LARB3_SMI>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
+
+		larb4: larb@15002000 {
+			compatible = "mediatek,mt6589-smi-larb";
+			reg = <0x15002000 0x1000>;
+			mediatek,smi = <&smi_common>;
+			mediatek,larb-id = <4>;
+			clocks = <&imgsys CLK_IMAGE_LARB4_SMI>,
+				 <&imgsys CLK_IMAGE_LARB4_SMI>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT6589_POWER_DOMAIN_DIS>; /* maybe */
+		};
 	};
 };
 

diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig
@@ -31,14 +31,23 @@ CONFIG_ARM_CPUIDLE=y
 
 ## IOMMU
 CONFIG_IOMMU_SUPPORT=y
-# MediaTek M4U
-#CONFIG_MTK_IOMMU=y
+CONFIG_MTK_IOMMU_V1=y
+
+## SMI
+CONFIG_MEMORY=y
+CONFIG_MTK_SMI=y
 
 ## Display
+CONFIG_DRM=y
+CONFIG_DRM_SIMPLEDRM=y
+CONFIG_DRM_MEDIATEK=y
+CONFIG_DRM_PANEL=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_PHY_MTK_MIPI_DSI=y
+CONFIG_MTK_MMSYS=y
 
-## Framebuffer
 CONFIG_FB=y
-CONFIG_FB_SIMPLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 
 ## Clock