Simplify dev builds - #776
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A commit adding an ID for the i219 in iPXE breaks the interface. It was reapplied during iPXE rebase, and needs to be reverted again. Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reapply the commit, guarding against NUC BOX which doesn't work well with it. Upstream-Status: Pending Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reapply the commit, guarding against NUC BOX which doesn't work well with it. Upstream-Status: Pending Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reapply the commit, guarding against NUC BOX which doesn't work well with it. Upstream-Status: Pending Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
… probing Set ROM_I2C_EN to expose the I2C USB-PD configuration EEPROM for probing within OS. This will allow later deployment of a patched binary to it, resolving USB-C power supply overdraw issues. Upstream-Status: Pending Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
…resume Some FSPs do not program CPU features on S3 resume. Most likely they were built with gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume set to FALSE by default. It was later fixed to be TRUE by default, but the FSPs did not pull this change. However, IoT FSPs provide an UPD to override this PCD. Use it to ensure the CPU features are programmed on S3 resume if FSP MP init is used and S3 resume is supported. TEST=Perform suspend/resume test with FWTS on ODROID-H4. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Inappropriate [custom edk2 fork] Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested by booting into Ubuntu 24.04 on a NovaCustom V540TU and checking the state of the DescriptorWriteable EFI variable via efivarfs. Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: Ife03e252f41a58af269f44c8e99e9c627c51c79d Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Don't issue HMRFPO if Capsule Update is enabled, as HMRFPO causes a global reset which corrupts capsules. Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I2dc0384360c1028d547c572f47f8a767abc61fe2 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [custom configs] Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I523690e69d4b11a9978ef07dd88f40e69acbd43a Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: Ib89a01b2e67b246aecb59f45f309c86c963144ff Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
SPC741D8-2L2T/BCM is a Xeon SP 4th/5th gen (Eagle Stream) platform with: - 1 SPR socket, 8 DDR5 DIMMs each - 4x PCIe 5.0 / CXL 1.1 x16 slots - 2x MCIO PCIe 5.0 x8 and 1 MCIO on PCH - 2x M.2 PCH PCIe slots - 2x 10 Gbit/s NIC and 2x 1 Gbit/s i210 NIC It has an AST2600 BMC for remote management and most SuperIO functions such as serial and an additional Nuvoton NCT6796D-E for others. Working: - All CPU cores of a 4/5th-gen Xeon SP are available at full speed - All 8 memory DIMMs (KSM48R40BS8KMM-16HMR) with 32 bit execution - All 4 PCIe slots - On-board USB ports - Video output via the AST2600 (on-board VGA) - M.2 devices Untested: - TPM header Not working: - Serial port I/O, related to the AST2600 SuperIO not being located at the default address of 0x2E (it uses 0x4E instead). - PC speaker (buzzer), for the same reason. - M.2 SSDs only use PCIe 3.0 x2, however, they should be capable of PCIe 3.0 x4 speeds, which can be observed using the vendor firmware. - Using more than 1 DIMM with 64 bit execution (the FSP temp_ram_exit function never returns) TEST=build/boot to Linux 6.12 using mainline edk2 Upstream-Status: Backport [CB:87747] Change-Id: I5b00a6f4ee68f71203940644860bf095615a9412 Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu> Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu> Co-authored-by: Felix Zimmer <felix.zimmer@student.kit.edu> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I7b09ce21b1b0a299d9f14b8d6867e65a6ef1d55a Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ is still needed due to Intel FSP repo does not ship all header files. TEST=Build and boot on intel/archercity CRB Upstream-Status: Backport [CB:80360] Change-Id: I778d3535c273dff653330518653bdefcb45e66f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80360 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
This register, called PCCS1IORE in the Emmitsburg EDS, controls which I/O ports are routed to peripherals connected to eSPI CS1#. Reference: Intel Emmitsburg EDS Rev2p0 (#606161) Upstream-Status: Pending Change-Id: I6e58cd48259566e084af7b1fc03c3824a205b741 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Enable routing serial ports and ports 4E / 4F to the BMC located on the secondary eSPI bus. This enables the serial ports connected to the COM header on the board and BMC Serial-over-LAN. Upstream-Status: Pending Change-Id: I32d88c0dd02311560ca932a36582c93f1bb99ffa Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I890b90d6f42f9f7e548edbd066738acabe5edd4e Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I63b83e4e8ef17752d94e2cc5083e6daf111f90d0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I8ace270541984c5564144402102135c2f16ff238 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I712cfca42dc13505bc276fcff4f44b28d9d5acd3 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I86a8ba1400b7e8c2d86599f30a3e0a619bfe4da0 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: If37c778ee99842f671a6174a4bfb7bc2f7fb9d2a Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: Ie2f328c8568a4dd404744470298e752467f0d481 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Necessary for SMM_BWP. Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I638a6774f508744ea630c4741916299a8dd63b54 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I9e67484866e218209d66c9ff705019c1d2a4bbb5 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
…ging Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I51ba9d95a7dcb994d8a60582b5707411fd25ce4e Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I1be6e74e8d6b460923610f8b0c3a426896f92e51 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Co-authored-by: Filip Lewiński <filip.lewinski@3mdeb.com> Change-Id: I31313845471c39d316857a24715e844d6792c01b Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: Ic7cf27b77cf400470e986959fcca3de076817207 Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: I95a14e91685df2afbcdd8cdb9fc6343613efd0e3 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: Id9dc5ebadde78ba424c8fea7f5d61cc641c33909 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested with an ARC A310 GPU: Memory at 500000000 (64-bit, prefetchable) [size=4G] Upstream-Status: Pending Change-Id: Ie4d02ed15f1561ad05405b5167796483fd70c1a4 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Customer has requested disabling the capability. Fixes compatibility with certain Samsung NVMe SSDs. Upstream-Status: Pending Change-Id: I997c372d1e17a954f6d28f55c9cc55a50ceb82df Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
This is the root port that the NVMe disk uses after updating the descriptors. Upstream-Status: Pending Change-Id: I634e4d311d9599847430488270102314f9241a94 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
This is the root port that the NVMe disk uses after updating the descriptors. Upstream-Status: Pending Change-Id: I5b64cf27d3dac5cf1bf5c2c6d682528e94a6628e Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
This is the root port that the NVMe disk uses after updating the descriptors. Upstream-Status: Pending Change-Id: Id5e8b2a6e953f64d2a60fb1cf3caa8dcdd71d238 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: Id528285d339bfe00fd1863f1ea4f6cf3c36f8dd7 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Similarly to CB:29395, which has added toolchain for POSTCAR, this is done for the purpose of making it possible to link vboot2 library in SMM. Until now SMM has been using options for ramstage, so using that as a default and updating the uses in src/cpu/x86/smm/Makefile.mk Upstream-Status: Backport [CB:92023] Change-Id: I20f2378eaf69b11b09a3d85d305e17110cf3c7ee Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92023 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The verification happens only when CMOS options backend is in use and SMM queries an option (this implicitly loads `cmos.layout` from CBFS). CB:89691 has added an exception for SMM since apparently nobody is using CBFS verification and CMOS options backend at the same time, but the exception introduced a security risk which this change resolves by permitting linking to vboot library in SMM. Upstream-Status: Backport [CB:92024] Change-Id: If3e5c92cb3e8bca8ea7600343f676dd895f02d41 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92024 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's not very useful in practice, yet requires an ugly include. Upstream-Status: Backport [CB:92027] Change-Id: Idb239c88c63cfd57b9586d519799db9d0d855eea Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92027 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:89691 incorrectly updated the line which was meant to check specifically for "COREBOOT", thus accidentally permitting creation of images with "COREBOOT_TS" but no "COREBOOT". Upstream-Status: Backport [CB:92026] Change-Id: I0a2daa9fab29a3dd52683aabca299ad2c26d1302 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92026 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 7c7feca ("CBFS verification: support Top Swap redundancy") added an optional `type` parameter to `_cbfs_unverified_area_alloc()` to match `_cbfs_alloc()` and permit uniform use of both functions, but did it via copy&paste. Properly extract the duplicated part to its own function. Upstream-Status: Backport [CB:92028] Change-Id: I6383fcb0ee9e8e4714b38972b471718cbada8cbf Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92028 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 7c7feca ("CBFS verification: support Top Swap redundancy") forced reset of metadata cache before processing every region to make it possible to process slots A and B in a single invocation of cbfstool when Top Swap (TS) redundancy is enabled. The slots use separate bootblock copies each with its own metadata anchor, so cache cannot be blindly reused. This change invalidates the cache only when a transition from a TS to a non-TS (or vice versa) region is detected, which is achieved by tracking what is currently in the cache. Additionally, make the function fail if TOPSWAP region is not found. Upstream-Status: Backport [CB:92025] Change-Id: I37da5585ceffdaa243c6b77471637d2457134768 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/92025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
… FSPs The option controls setting `ScsEmmcEnabled` and `ScsEmmcHs400Enabled` in FSPs. `ScsEmmcHs400Enabled` can be set in devicetree.cb as it's read from the file created by sconfig. `ScsEmmcEnabled` must be changed in the device config struct read using `pcidev_on_root` in `mainboard_silicon_init_params()` in ramstage, because `platform_fsp_silicon_init_params_cb()` sets it using `is_devfn_enabled(PCH_DEVFN_EMMC)` after mainboard_silicon_init_params was already called. Setting it directly in FSPS_UPD won't work as it would be replaced with what `is_devfn_enabled` returns. `is_devfn_enabled` returns true if in devicetree.cb `device pci 1a.0` is `on` (PCH_DEVFN_EMMC for cometlake is at PCHDEV_SLOT 0x1A, device 0 according to src/soc/intel/cannonlage/include/soc/pci_devs.h). Upstream-Status: Pending Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
…1 emmc config Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
…P 1c.3" Upstream-Status: Pending This reverts commit 0aa1b58. Change-Id: I1dc7d9017d3a6790f6878643816f033552551cc3
…P 1c.3" Upstream-Status: Pending This reverts commit 4a4006b. Change-Id: Id6c783ab69732c39fc7827ce4fd1884ba1aa5367
…P 1c.3" Upstream-Status: Pending This reverts commit d6ea878. Change-Id: Ib03236a19b3be63e8ffe8fd60c6da75eb4dcebe9
…urcation and lane reversal New FD blobs have changed SPA setting such that: - SATA is disabled - Lane reversal is enabled - 2x2 or 1x2 + 2x1 bifurcation is configured This way, the SSD always lands on root port 1 and gets 2 lanes, and subsequent devices on lanes 2,3 of SPA get allocated either an x1 or x2 link depending on board. Upstream-Status: Pending Change-Id: Ibd007334d09872baf7781ad2887212f4f847fc9b Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Change-Id: Id4859240606845a414524715ee31628df20820a5 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
The button sits on a multi-function pin of the IT8613E. Enabled the chip's GPIO block in devicetree.cb, muxed the pin to GP12 (away from PCIRST1#), and turned on its internal pull-up to make the signal go back to 1 after the button is released. Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Add CONFIG_ENABLE_EMMC Kconfig option (default y) to allow building
firmware without eMMC support for VP2440e hardware variants that lack
the eMMC controller. When disabled, ScsEmmcEnabled is cleared in FSP-S
UPD and the PCH eMMC device is disabled in ACPI, preventing spurious
initialization errors in firmware logs. SMBIOS product name reflects
the variant ("VP2440" vs "VP2440e"). Adds config.protectli_vp2440_no_emmc
defconfig and vp2440_noemmc/vp2440e build targets to build.sh.
Upstream-Status: Inappropriate [Dasharo downstream]
Signed-off-by: Wiktor Mowinski <wiktor.mowinski@3mdeb.com>
Upstream-Status: Inappropriate [Dasharo downstream] Signed-off-by: Wiktor Mowinski <wiktor.mowinski@3mdeb.com>
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
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