GitHub - CIDARLAB/NetlistSynthesizer: Verilog to Netlist

This is a Project for Netlist Synthesizer. I will write more later on.

Name		Name	Last commit message	Last commit date
Latest commit History 322 Commits
resources		resources
src		src
.gitignore		.gitignore
.travis.yml		.travis.yml
README.md		README.md
pom.xml		pom.xml

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