x86: fix the NLT, NLE and GE predicates in simde_mm_cmp_sd and simde_mm_cmp_ss

Both LSX branches complemented the wrong comparison, the same way
simde_mm256_cmp_pd did: NLT used cult and NLE used cule, which are false for
unordered operands where the negated predicates have to be true, and GE used
clt, which is true for them where GE has to be false.  Use clt and cle for
the negated predicates and cult for GE.

simde_mm_cmp_ss also selected its "always false" and "always true" cases with
SIMDE_LOONGARCH_LASX_NATIVE and wrote a_.i32[0] there, so those two cases went
through a different union member than every other case.  When the function is
not inlined (SIMDE_CONSTRAINED_COMPILATION at -O1 and above) GCC then dropped
the upper lanes, leaving _mm_cmp_ss with imm8 11, 15, 27 or 31 with garbage
above the low element.  Route them through a_.lsx_i64 like the rest.

Extend test_simde_mm_cmp_sd and test_simde_mm_cmp_ss with NaN inputs, which
are the only ones that tell the ordered and unordered predicates apart.

Author: jinboson

simde/x86/avx.h

@@ -2726,7 +2726,7 @@ simde_mm_cmp_sd (simde__m128d a, simde__m128d b, const int imm8)
     case SIMDE_CMP_NLT_UQ:
     case SIMDE_CMP_NLT_US:
       #if defined(SIMDE_LOONGARCH_LSX_NATIVE)
-        t_ = __lsx_vfcmp_cult_d(a_.lsx_f64, b_.lsx_f64);
+        t_ = __lsx_vfcmp_clt_d(a_.lsx_f64, b_.lsx_f64);
         a_.lsx_i64 = __lsx_vextrins_d(a_.lsx_i64, __lsx_vnor_v(t_, t_), 0x00);
       #else
         a_.i64[0] = !(a_.f64[0] < b_.f64[0]) ? ~INT64_C(0) : INT64_C(0);
@@ -2736,7 +2736,7 @@ simde_mm_cmp_sd (simde__m128d a, simde__m128d b, const int imm8)
     case SIMDE_CMP_NLE_UQ:
     case SIMDE_CMP_NLE_US:
       #if defined(SIMDE_LOONGARCH_LSX_NATIVE)
-        t_ = __lsx_vfcmp_cule_d(a_.lsx_f64, b_.lsx_f64);
+        t_ = __lsx_vfcmp_cle_d(a_.lsx_f64, b_.lsx_f64);
         a_.lsx_i64 = __lsx_vextrins_d(a_.lsx_i64, __lsx_vnor_v(t_, t_), 0x00);
       #else
         a_.i64[0] = !(a_.f64[0] <= b_.f64[0]) ? ~INT64_C(0) : INT64_C(0);
@@ -2787,7 +2787,7 @@ simde_mm_cmp_sd (simde__m128d a, simde__m128d b, const int imm8)
     case SIMDE_CMP_GE_OQ:
     case SIMDE_CMP_GE_OS:
       #if defined(SIMDE_LOONGARCH_LSX_NATIVE)
-        t_ = __lsx_vfcmp_clt_d(a_.lsx_f64, b_.lsx_f64);
+        t_ = __lsx_vfcmp_cult_d(a_.lsx_f64, b_.lsx_f64);
         a_.lsx_i64 = __lsx_vextrins_d(a_.lsx_i64, __lsx_vnor_v(t_, t_), 0x00);
       #else
         a_.i64[0] = (a_.f64[0] >= b_.f64[0]) ? ~INT64_C(0) : INT64_C(0);
@@ -2891,7 +2891,7 @@ simde_mm_cmp_ss (simde__m128 a, simde__m128 b, const int imm8)
     case SIMDE_CMP_NLT_UQ:
     case SIMDE_CMP_NLT_US:
       #if defined(SIMDE_LOONGARCH_LSX_NATIVE)
-        t_ = __lsx_vfcmp_cult_s(a_.lsx_f32, b_.lsx_f32);
+        t_ = __lsx_vfcmp_clt_s(a_.lsx_f32, b_.lsx_f32);
         a_.lsx_i64 = __lsx_vextrins_w(a_.lsx_i64, __lsx_vnor_v(t_, t_), 0x00);
       #else
         a_.i32[0] = !(a_.f32[0] < b_.f32[0]) ? ~INT32_C(0) : INT32_C(0);
@@ -2901,7 +2901,7 @@ simde_mm_cmp_ss (simde__m128 a, simde__m128 b, const int imm8)
     case SIMDE_CMP_NLE_UQ:
     case SIMDE_CMP_NLE_US:
       #if defined(SIMDE_LOONGARCH_LSX_NATIVE)
-        t_ = __lsx_vfcmp_cule_s(a_.lsx_f32, b_.lsx_f32);
+        t_ = __lsx_vfcmp_cle_s(a_.lsx_f32, b_.lsx_f32);
         a_.lsx_i64 = __lsx_vextrins_w(a_.lsx_i64, __lsx_vnor_v(t_, t_), 0x00);
       #else
         a_.i32[0] = !(a_.f32[0] <= b_.f32[0]) ? ~INT32_C(0) : INT32_C(0);
@@ -2946,8 +2946,8 @@ simde_mm_cmp_ss (simde__m128 a, simde__m128 b, const int imm8)
 
     case SIMDE_CMP_FALSE_OQ:
     case SIMDE_CMP_FALSE_OS:
-      #if defined(SIMDE_LOONGARCH_LASX_NATIVE)
-        a_.lsx_i32[0] = INT32_C(0);
+      #if defined(SIMDE_LOONGARCH_LSX_NATIVE)
+        a_.lsx_i64 = __lsx_vextrins_w(a_.lsx_i64, __lsx_vreplgr2vr_w(INT32_C(0)), 0x00);
       #else
         a_.i32[0] = INT32_C(0);
       #endif
@@ -2956,7 +2956,7 @@ simde_mm_cmp_ss (simde__m128 a, simde__m128 b, const int imm8)
     case SIMDE_CMP_GE_OQ:
     case SIMDE_CMP_GE_OS:
       #if defined(SIMDE_LOONGARCH_LSX_NATIVE)
-        t_ = __lsx_vfcmp_clt_s(a_.lsx_f32, b_.lsx_f32);
+        t_ = __lsx_vfcmp_cult_s(a_.lsx_f32, b_.lsx_f32);
         a_.lsx_i64 = __lsx_vextrins_w(a_.lsx_i64, __lsx_vnor_v(t_, t_), 0x00);
       #else
         a_.i32[0] = (a_.f32[0] >= b_.f32[0]) ? ~INT32_C(0) : INT32_C(0);
@@ -2974,8 +2974,8 @@ simde_mm_cmp_ss (simde__m128 a, simde__m128 b, const int imm8)
 
     case SIMDE_CMP_TRUE_UQ:
     case SIMDE_CMP_TRUE_US:
-      #if defined(SIMDE_LOONGARCH_LASX_NATIVE)
-        a_.lsx_i32[0] = ~INT32_C(0);
+      #if defined(SIMDE_LOONGARCH_LSX_NATIVE)
+        a_.lsx_i64 = __lsx_vextrins_w(a_.lsx_i64, __lsx_vreplgr2vr_w(~INT32_C(0)), 0x00);
       #else
         a_.i32[0] = ~INT32_C(0);
       #endif

test/x86/avx.c

@@ -5843,6 +5843,31 @@ test_simde_mm_cmp_sd(SIMDE_MUNIT_TEST_ARGS) {
   r = simde_mm_cmp_sd(a, b, 31);
   simde_assert_m128i_u64(simde_mm_castpd_si128(r), ==, simde_mm_castpd_si128(e));
 
+  /* The negated predicates have to be true for unordered operands, and their
+   * non-negated counterparts false; only NaN inputs tell the two apart. */
+  a = simde_mm_setr_pd(SIMDE_MATH_NAN, SIMDE_FLOAT64_C(  987.65));
+  b = simde_mm_setr_pd(SIMDE_FLOAT64_C(    0.00), SIMDE_FLOAT64_C(  123.45));
+
+  e = simde_mm_move_sd(a, simde_x_mm_setone_pd());
+  r = simde_mm_cmp_sd(a, b, 5);
+  simde_assert_m128i_u64(simde_mm_castpd_si128(r), ==, simde_mm_castpd_si128(e));
+
+  r = simde_mm_cmp_sd(a, b, 6);
+  simde_assert_m128i_u64(simde_mm_castpd_si128(r), ==, simde_mm_castpd_si128(e));
+
+  e = simde_mm_move_sd(a, simde_mm_setzero_pd());
+  r = simde_mm_cmp_sd(a, b, 13);
+  simde_assert_m128i_u64(simde_mm_castpd_si128(r), ==, simde_mm_castpd_si128(e));
+
+  /* The always-false and always-true predicates still have to pass the upper
+   * element through. */
+  r = simde_mm_cmp_sd(a, b, 11);
+  simde_assert_m128i_u64(simde_mm_castpd_si128(r), ==, simde_mm_castpd_si128(e));
+
+  e = simde_mm_move_sd(a, simde_x_mm_setone_pd());
+  r = simde_mm_cmp_sd(a, b, 31);
+  simde_assert_m128i_u64(simde_mm_castpd_si128(r), ==, simde_mm_castpd_si128(e));
+
   return 0;
 }
 
@@ -6042,6 +6067,31 @@ test_simde_mm_cmp_ss(SIMDE_MUNIT_TEST_ARGS) {
   r = simde_mm_cmp_ss(a, b, 31);
   simde_assert_m128i_u32(simde_mm_castps_si128(r), ==, simde_mm_castps_si128(e));
 
+  /* The negated predicates have to be true for unordered operands, and their
+   * non-negated counterparts false; only NaN inputs tell the two apart. */
+  a = simde_mm_setr_ps(SIMDE_MATH_NAN, SIMDE_FLOAT32_C(    1.00), SIMDE_FLOAT32_C(    2.00), SIMDE_FLOAT32_C(    3.00));
+  b = simde_mm_setr_ps(SIMDE_FLOAT32_C(    0.00), SIMDE_FLOAT32_C(    1.00), SIMDE_FLOAT32_C(    5.00), SIMDE_FLOAT32_C(    3.00));
+
+  e = simde_mm_move_ss(a, simde_x_mm_setone_ps());
+  r = simde_mm_cmp_ss(a, b, 5);
+  simde_assert_m128i_u32(simde_mm_castps_si128(r), ==, simde_mm_castps_si128(e));
+
+  r = simde_mm_cmp_ss(a, b, 6);
+  simde_assert_m128i_u32(simde_mm_castps_si128(r), ==, simde_mm_castps_si128(e));
+
+  e = simde_mm_move_ss(a, simde_mm_setzero_ps());
+  r = simde_mm_cmp_ss(a, b, 13);
+  simde_assert_m128i_u32(simde_mm_castps_si128(r), ==, simde_mm_castps_si128(e));
+
+  /* The always-false and always-true predicates still have to pass the upper
+   * elements through. */
+  r = simde_mm_cmp_ss(a, b, 11);
+  simde_assert_m128i_u32(simde_mm_castps_si128(r), ==, simde_mm_castps_si128(e));
+
+  e = simde_mm_move_ss(a, simde_x_mm_setone_ps());
+  r = simde_mm_cmp_ss(a, b, 31);
+  simde_assert_m128i_u32(simde_mm_castps_si128(r), ==, simde_mm_castps_si128(e));
+
   return 0;
 }