Control.sv

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/30 8:26:09
// Design Name: 
// Module Name: Control
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
//     添加了minyRV的支持， 剩余内存屏障、控制终端、csr等10条指令    
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module Control(
    input  logic [6:0]  opcode,
    
    output logic [1:0]  NpcOp,         //
    output logic        RegWrite,      //
    output logic [1:0]  MemToReg,      //_mux wb
    output logic        MemWrite,      //
    output logic        OffsetOrigin,  //_npc
    output logic        ALUSrc_B,        //_mux alu B
    output logic        ALUSrc_A       //_mux alu A (0: rs1, 1: PC)
);

always_comb begin
    // Default values：最好不要修改
    NpcOp        = 2'b00;  // PC+4 ,01:条件跳转 10：jalr 指令，npc = Result & ~1 
                           // 11：jal 指令，npc = pc + offset
    RegWrite     = 1'b0;
    MemToReg     = 2'b00;  // 00: ALU result, 01: memory data, 10: PC+4
                           // 11: immgen
    MemWrite     = 1'b0;
    OffsetOrigin = 1'b0;   // 0:jalr(ALU) , 1:  jal(immgen)
    ALUSrc_B       = 1'b0;   // 0: regB, 1: immediate
    ALUSrc_A       = 1'b0;  // 默认使用 0:rs1_data 作为 ALU A 端输入


    case(opcode)
        // R-type (ADD, SUB, etc.)
        7'b0110011: begin
            RegWrite = 1'b1;
            MemToReg = 2'b00;
            ALUSrc_B    = 1'b0;
            ALUSrc_A = 1'b0;
        end

        // I-type arithmetic (ADDI, etc.)
        7'b0010011: begin
            RegWrite = 1'b1;
            MemToReg = 2'b00;
            ALUSrc_B     = 1'b1;
            ALUSrc_A = 1'b0;
        end

        // Load (LW)
        7'b0000011: begin
            RegWrite = 1'b1;
            MemToReg = 2'b01;
            ALUSrc_B     = 1'b1;
            ALUSrc_A = 1'b0;
        end

        // Store (SW, SH, SB)
        7'b0100011: begin
            MemWrite = 1'b1;
            ALUSrc_B     = 1'b1;
            ALUSrc_A = 1'b0;
        end

        // Branch (BEQ, BNE, etc.)
        7'b1100011: begin
            NpcOp        = 2'b01;  // branch decision
            OffsetOrigin = 1'b1;  //immgen
            ALUSrc_A = 1'b0;
        end

        // JAL
        7'b1101111: begin
            NpcOp        = 2'b11;  // PC + offset
            RegWrite     = 1'b1;
            MemToReg     = 2'b10;  // PC+4
            OffsetOrigin = 1'b1;  //immgen
            ALUSrc_A = 1'b0;
        end

        // JALR
        7'b1100111: begin
            NpcOp           = 2'b10;  // register-based jump
            RegWrite        = 1'b1;
            MemToReg        = 2'b10;
            OffsetOrigin    = 1'b0;  // ALU
            ALUSrc_B          = 1'b1; //immediate
            ALUSrc_A = 1'b0; //rs1_data
        end

        // LUI
        7'b0110111: begin
            RegWrite = 1'b1;
            MemToReg = 2'b11;  // immediate value
            ALUSrc_A = 1'b0;
        end

        // AUIPC
        7'b0010111: begin
            RegWrite        = 1'b1;
            MemToReg        = 2'b00;
            ALUSrc_B           = 1'b1; // immediate value 
            ALUSrc_A = 1'b1;
        end

        //TODO: Add other opcodes : fence, fence.i, ecall, ebreak, csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
        default: begin
            // Handle undefined opcodes
            // Could set all outputs to 0 or implement exception handling
            // Default values：最好不要修改
            NpcOp        = 2'b00;  // PC+4 ,01:条件跳转 10：jalr 指令，npc = Result & ~1 
                                   // 11：jal 指令，npc = pc + offset
            RegWrite     = 1'b0;
            MemToReg     = 2'b00;  // 00: ALU result, 01: memory data, 10: PC+4
                                   // 11: immgen
            MemWrite     = 1'b0;
            OffsetOrigin = 1'b0;   // 0:jalr(ALU) , 1:  jal(immgen)
            ALUSrc_B        = 1'b0;   // 0: regB, 1: immediate
            ALUSrc_A= 1'b0;  
        end
    endcase
end

endmodule