diff --git a/packages/mesa/0003-fix-for-anon-file.patch b/packages/mesa/0003-fix-for-anon-file.patch index 06428da00d9..0cb80367abd 100644 --- a/packages/mesa/0003-fix-for-anon-file.patch +++ b/packages/mesa/0003-fix-for-anon-file.patch @@ -2,12 +2,12 @@ Fallback to `@TERMUX_PREFIX@/tmp` if env `XDG_RUNTIME_DIR` is not set. --- a/src/util/anon_file.c +++ b/src/util/anon_file.c -@@ -122,7 +122,7 @@ get_or_create_user_temp_dir(char* buf, size_t len) { +@@ -125,7 +125,7 @@ get_or_create_user_temp_dir(void) { return buf; } -- snprintf(buf, len, "/tmp/xdg-runtime-mesa-%ld", (long)getuid()); -+ snprintf(buf, len, "@TERMUX_PREFIX@/tmp/xdg-runtime-mesa-%ld", (long)getuid()); +- n = asprintf(&buf, "/tmp/xdg-runtime-mesa-%ld", (long)getuid()); ++ n = asprintf(&buf, "@TERMUX_PREFIX@/tmp/xdg-runtime-mesa-%ld", (long)getuid()); + if (n < 0) + return NULL; mesa_logd("%s: XDG_RUNTIME_DIR not set; falling back to temp dir %s", - __func__, buf); - if (stat(buf, &st) == 0) { diff --git a/packages/mesa/0007-use-mtx_t-operations-in-turnip.patch b/packages/mesa/0007-use-mtx_t-operations-in-turnip.patch index f905e4e66e7..616dfed1a14 100644 --- a/packages/mesa/0007-use-mtx_t-operations-in-turnip.patch +++ b/packages/mesa/0007-use-mtx_t-operations-in-turnip.patch @@ -1,6 +1,6 @@ --- a/src/freedreno/vulkan/tu_shader.cc +++ b/src/freedreno/vulkan/tu_shader.cc -@@ -1980,10 +1980,10 @@ +@@ -2694,10 +2694,10 @@ tu_upload_shader(struct tu_device *dev, size += vpc_size; } @@ -13,7 +13,7 @@ if (result != VK_SUCCESS) return result; -@@ -2013,9 +2013,9 @@ +@@ -2727,9 +2727,9 @@ tu_upload_shader(struct tu_device *dev, result = tu_setup_pvtmem(dev, shader, &pvtmem_config, pvtmem_size, per_wave); if (result != VK_SUCCESS) { @@ -25,7 +25,7 @@ return result; } -@@ -2419,10 +2419,10 @@ +@@ -3531,10 +3531,10 @@ tu_empty_shader_create(struct tu_device *dev, if (!shader) return VK_ERROR_OUT_OF_HOST_MEMORY; @@ -38,9 +38,9 @@ if (result != VK_SUCCESS) { vk_free(&dev->vk.alloc, shader); -@@ -2528,9 +2528,9 @@ - { +@@ -3645,9 +3645,9 @@ tu_shader_destroy(struct tu_device *dev, tu_cs_finish(&shader->cs); + TU_RMV(resource_destroy, dev, &shader->bo); - pthread_mutex_lock(&dev->pipeline_mutex); + mtx_lock(&dev->pipeline_mutex); @@ -50,20 +50,3 @@ if (shader->pvtmem_bo) tu_bo_finish(dev, shader->pvtmem_bo); ---- a/src/vulkan/wsi/wsi_common_wayland.c -+++ b/src/vulkan/wsi/wsi_common_wayland.c -@@ -2648,12 +2648,12 @@ wsi_wl_swapchain_wait_for_present2(struct wsi_swapchain *wsi_chain, - return result; - - while (1) { -- err = pthread_mutex_lock(&chain->present_ids.lock); -+ err = mtx_lock(&chain->present_ids.lock); - if (err != 0) - return VK_ERROR_OUT_OF_DATE_KHR; - - bool completed = chain->present_ids.max_completed >= present_id; -- pthread_mutex_unlock(&chain->present_ids.lock); -+ mtx_unlock(&chain->present_ids.lock); - - if (completed) - return VK_SUCCESS; diff --git a/packages/mesa/0013-detect-sve-sve2-support.patch b/packages/mesa/0013-detect-sve-sve2-support.patch deleted file mode 100644 index a9d2a422e04..00000000000 --- a/packages/mesa/0013-detect-sve-sve2-support.patch +++ /dev/null @@ -1,59 +0,0 @@ -https://github.com/llvm/llvm-project/issues/114987 -https://github.com/termux/termux-packages/issues/24544 - ---- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp -+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp -@@ -88,6 +88,23 @@ - #include "lp_bld_misc.h" - #include "lp_bld_debug.h" - -+#if __has_include() -+#include -+#define HAVE_SYS_AUXV 1 -+#ifndef AT_HWCAP -+#define AT_HWCAP 16 -+#endif -+#ifndef AT_HWCAP2 -+#define AT_HWCAP2 26 -+#endif -+#ifndef HWCAP_SVE -+#define HWCAP_SVE (1 << 22) -+#endif -+#ifndef HWCAP2_SVE2 -+#define HWCAP2_SVE2 (1 << 1) -+#endif -+#endif -+ - static void lp_run_atexit_for_destructors(void); - - namespace { -@@ -446,6 +463,29 @@ - MAttrs.push_back("-lasx"); - #endif - #endif -+ -+#if DETECT_ARCH_AARCH64 && defined(HAVE_SYS_AUXV) -+ // Guess SVE/SVE2 support on ARM64 -+ bool has_sve = getauxval(AT_HWCAP) & HWCAP_SVE; -+ bool has_sve2 = getauxval(AT_HWCAP2) & HWCAP2_SVE2; -+ MAttrs.push_back(has_sve ? "+sve" : "-sve"); -+ MAttrs.push_back(has_sve2 ? "+sve2" : "-sve2"); -+#endif -+ -+ // Allow adding extra MAttrs through envs -+ char *env_extra_mattrs = getenv("GALLIVM_EXTRA_MATTRS"); -+ if (env_extra_mattrs != NULL) { -+ char *dup = strdup(env_extra_mattrs); -+ if (dup != NULL) { -+ char *state; -+ char *token = strtok_r(dup, ",", &state); -+ while (token) { -+ MAttrs.push_back(token); -+ token = strtok_r(NULL, ",", &state); -+ } -+ free(dup); -+ } -+ } - } - - void diff --git a/packages/mesa/0016-unofficial_support_adreno_710_720_722.patch b/packages/mesa/0016-unofficial_support_adreno_710_720_722.patch deleted file mode 100644 index 068e6702115..00000000000 --- a/packages/mesa/0016-unofficial_support_adreno_710_720_722.patch +++ /dev/null @@ -1,74 +0,0 @@ -Created by, or sourced from, Vauzi-17 -https://github.com/Vauzi-17/710 -Upstream issue: -https://gitlab.freedesktop.org/mesa/mesa/-/issues/13036 - ---- a/src/freedreno/common/freedreno_devices.py -+++ b/src/freedreno/common/freedreno_devices.py -@@ -1149,6 +1149,66 @@ a740_raw_magic_regs = [ - [A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0], - ] - -+add_gpus([ -+ GPUId(chip_id=0x07010000, name="FD710"), -+ GPUId(chip_id=0xffff07010000, name="FD710"), -+ ], A6xxGPUInfo( -+ CHIP.A7XX, -+ [a7xx_base, a7xx_gen1], -+ num_ccu = 3, -+ tile_align_w = 64, -+ tile_align_h = 32, -+ tile_max_w = 1024, -+ tile_max_h = 1024, -+ num_vsc_pipes = 32, -+ cs_shared_mem_size = 32 * 1024, -+ wave_granularity = 2, -+ fibers_per_sp = 128 * 2 * 16, -+ highest_bank_bit = 16, -+ magic_regs = a730_magic_regs, -+ raw_magic_regs = a730_raw_magic_regs, -+ )) -+ -+add_gpus([ -+ GPUId(chip_id=0x43020000, name="FD720"), -+ GPUId(chip_id=0xffff43020000, name="FD720"), -+ ], A6xxGPUInfo( -+ CHIP.A7XX, -+ [a7xx_base, a7xx_gen1], -+ num_ccu = 3, -+ tile_align_w = 64, -+ tile_align_h = 32, -+ tile_max_w = 1024, -+ tile_max_h = 1024, -+ num_vsc_pipes = 32, -+ cs_shared_mem_size = 32 * 1024, -+ wave_granularity = 2, -+ fibers_per_sp = 128 * 2 * 16, -+ highest_bank_bit = 16, -+ magic_regs = a730_magic_regs, -+ raw_magic_regs = a730_raw_magic_regs, -+ )) -+ -+add_gpus([ -+ GPUId(chip_id=0x43020100, name="FD722"), -+ GPUId(chip_id=0xffff43020100, name="FD722"), -+ ], A6xxGPUInfo( -+ CHIP.A7XX, -+ [a7xx_base, a7xx_gen1], -+ num_ccu = 3, -+ tile_align_w = 64, -+ tile_align_h = 32, -+ tile_max_w = 1024, -+ tile_max_h = 1024, -+ num_vsc_pipes = 32, -+ cs_shared_mem_size = 32 * 1024, -+ wave_granularity = 2, -+ fibers_per_sp = 128 * 2 * 16, -+ highest_bank_bit = 16, -+ magic_regs = a730_magic_regs, -+ raw_magic_regs = a730_raw_magic_regs, -+ )) -+ - add_gpus([ - # These are named as Adreno730v3 or Adreno725v1. - GPUId(chip_id=0x07030002, name="FD725"), diff --git a/packages/mesa/0017-preserve-egl-support-in-zink.patch b/packages/mesa/0017-preserve-egl-support-in-zink.patch deleted file mode 100644 index 34a793c68ac..00000000000 --- a/packages/mesa/0017-preserve-egl-support-in-zink.patch +++ /dev/null @@ -1,40 +0,0 @@ -mesa upstream code 'thinks' that if 'x11_dri3_open()' -has a negative retval, then DRI3 EGL acceleration in Zink with the current settings -is impossible in all cases and it disables Zink and falls back to software rendering. - -However, Termux:X11 is a 3rd party edge case where, in actual testing, -for a very long time throughout the past year of mesa releases, -even if 'x11_dri3_open()' has a negative retval, -for some reason Zink+Tunip GPU acceleration still works if force-enabled -anytime that software rendering is not the initial default. - -This 'Termux-unaware' upstream mesa codepath that fails to 'understand' the true -capabilities of Zink+Turnip+Termux:X11 has gradually been building up in the background -for the last several months, but in this commit: -https://gitlab.freedesktop.org/mesa/mesa/-/commit/3294cad34159bd5317e3dfb0cb4e0ba5caca9f77 -the 'switch was flipped' to the new codepath, so to speak, locking vanilla mesa's EGL -support away from the Zink+Turnip+Termux:X11 codepath unless some kind of intervention -is performed, such as this patch. - ---- a/src/egl/drivers/dri2/platform_x11_dri3.c -+++ b/src/egl/drivers/dri2/platform_x11_dri3.c -@@ -535,7 +535,7 @@ dri3_x11_connect(struct dri2_egl_display *dri2_dpy, bool swrast) - _eglLog(_EGL_WARNING, "DRI3: Failed to initialize"); - } - -- return false; -+ return true; - } - - loader_get_user_preferred_fd(&dri2_dpy->fd_render_gpu, ---- a/src/egl/main/eglapi.c -+++ b/src/egl/main/eglapi.c -@@ -683,7 +683,7 @@ eglInitialize(EGLDisplay dpy, EGLint *major, EGLint *minor) - "Found 'LIBGL_ALWAYS_SOFTWARE' set, will use a CPU renderer"); - - const char *env = os_get_option("MESA_LOADER_DRIVER_OVERRIDE"); -- disp->Options.Zink = env && !strcmp(env, "zink"); -+ disp->Options.Zink = !env || !strcmp(env, "zink"); - - const char *gallium_hud_env = os_get_option("GALLIUM_HUD"); - disp->Options.GalliumHudWarn = diff --git a/packages/mesa/0018-disable-general-layout-in-zink-for-turnip.patch b/packages/mesa/0018-disable-general-layout-in-zink-for-turnip.patch deleted file mode 100644 index dc6d5eaa11b..00000000000 --- a/packages/mesa/0018-disable-general-layout-in-zink-for-turnip.patch +++ /dev/null @@ -1,22 +0,0 @@ -Partially reverts https://gitlab.freedesktop.org/mesa/mesa/-/commit/622612f67ea72298c3d85dfe53c5d54ee9f98527 -because that commit causes severe artifacts in Webrender in Firefox in Termux:X11 with GLX enabled and EGL -force-disabled in Zink in Turnip on Adreno devices, while using the about:config settings -gfx.webrender.all=true and gfx.x11-egl.force-disabled=true, -and doing this prevents the artifacts from occurring. - ---- a/src/gallium/drivers/zink/zink_screen.c -+++ b/src/gallium/drivers/zink/zink_screen.c -@@ -3044,10 +3044,12 @@ init_driver_workarounds(struct zink_screen *screen) - case VK_DRIVER_ID_MESA_LLVMPIPE: - case VK_DRIVER_ID_MESA_NVK: - case VK_DRIVER_ID_NVIDIA_PROPRIETARY: -- case VK_DRIVER_ID_MESA_TURNIP: - case VK_DRIVER_ID_QUALCOMM_PROPRIETARY: - screen->driver_workarounds.general_layout = true; - break; -+ case VK_DRIVER_ID_MESA_TURNIP: -+ screen->driver_workarounds.general_layout = false; -+ break; - default: - screen->driver_workarounds.general_layout = screen->info.have_KHR_unified_image_layouts; - break; diff --git a/packages/mesa/0019-UBWC_5-and-UBWC_6-support.patch b/packages/mesa/0019-UBWC_5-and-UBWC_6-support.patch deleted file mode 100644 index 487f6bf0219..00000000000 --- a/packages/mesa/0019-UBWC_5-and-UBWC_6-support.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 2da45c609845854491c09bd26d9d8245834ea4af Mon Sep 17 00:00:00 2001 -From: Rob Clark -Date: Tue, 13 Jan 2026 10:58:51 -0800 -Subject: [PATCH] WIP: tu/kgsl: Add UBWC_5 and UBWC_6 support - -The #defines seem to map 1:1, so we can add support even without an -updated kgsl uabi header. ---- - src/freedreno/vulkan/tu_knl_kgsl.cc | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/src/freedreno/vulkan/tu_knl_kgsl.cc b/src/freedreno/vulkan/tu_knl_kgsl.cc -index e3a49692e941..48a0f8802e1a 100644 ---- a/src/freedreno/vulkan/tu_knl_kgsl.cc -+++ b/src/freedreno/vulkan/tu_knl_kgsl.cc -@@ -1842,6 +1842,8 @@ tu_knl_kgsl_load(struct tu_instance *instance, int fd) - device->ubwc_config.macrotile_mode = FDL_MACROTILE_4_CHANNEL; - break; - case KGSL_UBWC_4_0: -+ case 5: -+ case 6: - device->ubwc_config.bank_swizzle_levels = 0x6; - device->ubwc_config.macrotile_mode = FDL_MACROTILE_8_CHANNEL; - break; diff --git a/packages/mesa/0020-unofficial-support-adreno-830.patch b/packages/mesa/0020-unofficial-support-adreno-830.patch deleted file mode 100644 index 33ae38135cb..00000000000 --- a/packages/mesa/0020-unofficial-support-adreno-830.patch +++ /dev/null @@ -1,85 +0,0 @@ -Modified based on Adreno 840, most features should work. - ---- a/src/freedreno/common/freedreno_devices.py -+++ b/src/freedreno/common/freedreno_devices.py -@@ -1499,28 +1499,6 @@ a8xx_gen2 = GPUProps( - has_fs_tex_prefetch = False, - ) - --# Totally fake, just to get cffdump to work: --add_gpus([ -- GPUId(chip_id=0x44050000, name="FD830"), -- ], A6xxGPUInfo( -- CHIP.A8XX, -- [a7xx_base, a7xx_gen3, a8xx_base], -- num_ccu = 6, -- num_slices = 3, -- tile_align_w = 64, -- tile_align_h = 32, -- tile_max_w = 16384, -- tile_max_h = 16384, -- num_vsc_pipes = 32, -- cs_shared_mem_size = 32 * 1024, -- wave_granularity = 2, -- fibers_per_sp = 128 * 2 * 16, -- magic_regs = dict( -- ), -- raw_magic_regs = [ -- ], -- )) -- - # For a8xx, the chicken bit and most other non-ctx reg - # programming moves into the kernel, and what remains - # should be easier to share between devices -@@ -1555,6 +1533,29 @@ a8xx_gen2_raw_magic_regs = [ - [A6XXRegs.REG_A8XX_PC_MODE_CNTL, 0x00003f00], - ] - -+# Modified based on Adreno 840, most features should work -+add_gpus([ -+ GPUId(chip_id=0x44050000, name="FD830"), -+ GPUId(chip_id=0xffff44050001, name="Adreno (TM) 830"), -+ ], A6xxGPUInfo( -+ CHIP.A8XX, -+ [a7xx_base, a7xx_gen3, a8xx_base, a8xx_gen2, -+ GPUProps(shading_rate_matches_vk = True)], -+ num_ccu = 6, -+ num_slices = 3, -+ tile_align_w = 96, -+ tile_align_h = 32, -+ tile_max_w = 16416, -+ tile_max_h = 16384, -+ num_vsc_pipes = 32, -+ cs_shared_mem_size = 32 * 1024, -+ wave_granularity = 2, -+ fibers_per_sp = 128 * 2 * 16, -+ magic_regs = dict( -+ ), -+ raw_magic_regs = a8xx_gen2_raw_magic_regs, -+ )) -+ - add_gpus([ - GPUId(chip_id=0xffff44050A31, name="Adreno (TM) 840"), - ], A6xxGPUInfo( ---- a/src/freedreno/drm-shim/freedreno_noop.c -+++ b/src/freedreno/drm-shim/freedreno_noop.c -@@ -288,7 +288,7 @@ static const struct msm_device_info device_infos[] = { - }, - { - .gpu_id = 830, -- .chip_id = 0x44050000, -+ .chip_id = 0x44050001, - .gmem_size = 12 * 1024 * 1024, - }, - }; ---- a/src/freedreno/ir3/tests/disasm.c -+++ b/src/freedreno/ir3/tests/disasm.c -@@ -33,7 +33,7 @@ - #define INSTR_6XX_RAW(i, d, ...) { .gpu_id = 630, .instr = NULL, .instr_raw = i, .expected = d, __VA_ARGS__ } - #define INSTR_7XX(i, d, ...) { .chip_id = 0x07030001, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ } - #define INSTR_7XX_RAW(i, d, ...) { .chip_id = 0x07030001, .instr = NULL, .instr_raw = i, .expected = d, __VA_ARGS__ } --#define INSTR_8XX(i, d, ...) { .chip_id = 0x44050000, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ } -+#define INSTR_8XX(i, d, ...) { .chip_id = 0x44050001, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ } - /* clang-format on */ - - static const struct test { diff --git a/packages/mesa/0021-unofficial-support-adreno-810-825-829.patch b/packages/mesa/0021-unofficial-support-adreno-810-825-829.patch deleted file mode 100644 index de5f15b26d2..00000000000 --- a/packages/mesa/0021-unofficial-support-adreno-810-825-829.patch +++ /dev/null @@ -1,168 +0,0 @@ -freedreno: enable Adreno 810+825+829 - -The source code is from whitebelyash: -https://github.com/whitebelyash/mesa-tu8/commit/cce699c8b5423adf1ad60335356408767c6971aa -https://github.com/whitebelyash/mesa-tu8/commit/6422f965fa26c384a139aa8e070ac37e5a4b3e96 -https://github.com/whitebelyash/mesa-tu8/commit/16ada8f7816b9dcfb678136f48036880699027b3 - -diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py -index 5cbd5d11504..ebeaab440a4 100644 ---- a/src/freedreno/common/freedreno_devices.py -+++ b/src/freedreno/common/freedreno_devices.py -@@ -1505,6 +1505,62 @@ a8xx_gen2 = GPUProps( - has_salu_int_narrowing_quirk = True - ) - -+a8xx_825 = GPUProps( -+ sysmem_vpc_attr_buf_size = 131072, -+ sysmem_vpc_pos_buf_size = 65536, -+ sysmem_vpc_bv_pos_buf_size = 32768, -+ sysmem_ccu_color_cache_fraction = CCUColorCacheFraction.FULL.value, -+ sysmem_per_ccu_color_cache_size = 128 * 1024, -+ sysmem_ccu_depth_cache_fraction = CCUColorCacheFraction.THREE_QUARTER.value, -+ sysmem_per_ccu_depth_cache_size = 96 * 1024, # TODO: check if 128 works too -+ gmem_vpc_attr_buf_size = 49152, -+ gmem_vpc_pos_buf_size = 24576, -+ gmem_vpc_bv_pos_buf_size = 32768, -+ gmem_ccu_color_cache_fraction = CCUColorCacheFraction.EIGHTH.value, -+ gmem_per_ccu_color_cache_size = 16 * 1024, -+ gmem_ccu_depth_cache_fraction = CCUColorCacheFraction.FULL.value, -+ gmem_per_ccu_depth_cache_size = 127 * 1024, -+) -+ -+a8xx_810 = GPUProps( -+ sysmem_vpc_attr_buf_size = 131072, -+ sysmem_vpc_pos_buf_size = 65536, -+ sysmem_vpc_bv_pos_buf_size = 32768, -+ # These values are maximum size of depth/color cache for current A8XX Gen2 sysmem configuration -+ # Bigger values cause an integer underflow in freedreno gmem calculations -+ sysmem_ccu_color_cache_fraction = CCUColorCacheFraction.FULL.value, -+ sysmem_per_ccu_color_cache_size = 32 * 1024, -+ sysmem_ccu_depth_cache_fraction = CCUColorCacheFraction.THREE_QUARTER.value, -+ sysmem_per_ccu_depth_cache_size = 32 * 1024, -+ gmem_vpc_attr_buf_size = 49152, -+ gmem_vpc_pos_buf_size = 24576, -+ gmem_vpc_bv_pos_buf_size = 32768, -+ gmem_ccu_color_cache_fraction = CCUColorCacheFraction.EIGHTH.value, -+ gmem_per_ccu_color_cache_size = 16 * 1024, -+ gmem_ccu_depth_cache_fraction = CCUColorCacheFraction.FULL.value, -+ gmem_per_ccu_depth_cache_size = 64 * 1024, -+ # FD810 does not support ray tracing -+ has_ray_intersection = False, -+ has_sw_fuse = False, -+) -+ -+a8xx_829 = GPUProps( -+ sysmem_vpc_attr_buf_size = 131072, -+ sysmem_vpc_pos_buf_size = 65536, -+ sysmem_vpc_bv_pos_buf_size = 32768, -+ sysmem_ccu_color_cache_fraction = CCUColorCacheFraction.FULL.value, -+ sysmem_per_ccu_color_cache_size = 128 * 1024, -+ sysmem_ccu_depth_cache_fraction = CCUColorCacheFraction.THREE_QUARTER.value, -+ sysmem_per_ccu_depth_cache_size = 96 * 1024, -+ gmem_vpc_attr_buf_size = 49152, -+ gmem_vpc_pos_buf_size = 24576, -+ gmem_vpc_bv_pos_buf_size = 32768, -+ gmem_ccu_color_cache_fraction = CCUColorCacheFraction.EIGHTH.value, -+ gmem_per_ccu_color_cache_size = 16 * 1024, -+ gmem_ccu_depth_cache_fraction = CCUColorCacheFraction.FULL.value, -+ gmem_per_ccu_depth_cache_size = 127 * 1024, -+) -+ - # For a8xx, the chicken bit and most other non-ctx reg - # programming moves into the kernel, and what remains - # should be easier to share between devices -@@ -1563,6 +1619,72 @@ add_gpus([ - raw_magic_regs = a8xx_gen2_raw_magic_regs, - )) - -+# gen8_6_0 -+add_gpus([ -+ GPUId(chip_id=0x44030000, name="FD825"), -+ ], A6xxGPUInfo( -+ CHIP.A8XX, -+ [a7xx_base, a7xx_gen3, a8xx_base, a8xx_825], -+ num_ccu = 4, -+ num_slices = 2, -+ tile_align_w = 64, -+ tile_align_h = 32, -+ tile_max_w = 16384, -+ tile_max_h = 16384, -+ num_vsc_pipes = 32, -+ cs_shared_mem_size = 32 * 1024, -+ wave_granularity = 2, -+ fibers_per_sp = 128 * 2 * 16, -+ magic_regs = dict( -+ ), -+ raw_magic_regs = a8xx_gen2_raw_magic_regs, -+ )) -+ -+# gen8_3_0 -+add_gpus([ -+ GPUId(chip_id=0x44010000, name="FD810"), -+ ], A6xxGPUInfo( -+ CHIP.A8XX, -+ [a7xx_base, a7xx_gen3, a8xx_base, a8xx_810], -+ num_ccu = 2, -+ num_slices = 1, -+ tile_align_w = 64, -+ tile_align_h = 32, -+ tile_max_w = 16384, -+ tile_max_h = 16384, -+ num_vsc_pipes = 32, -+ cs_shared_mem_size = 32 * 1024, -+ wave_granularity = 2, -+ fibers_per_sp = 128 * 2 * 16, -+ magic_regs = dict( -+ ), -+ raw_magic_regs = a8xx_gen2_raw_magic_regs, -+ )) -+ -+# TODO: Properly fill all values for this GPU -+# Very weird GPU, ugh.. -+add_gpus([ -+ GPUId(chip_id=0x44030A00, name="FD829"), # kgsl id??? -+ GPUId(chip_id=0x44030A20, name="FD829"), # found by testing -+ GPUId(chip_id=0xffff44030A00, name="FD829"), -+ ], A6xxGPUInfo( -+ CHIP.A8XX, -+ [a7xx_base, a7xx_gen3, a8xx_base, a8xx_829,], -+ num_ccu = 4, -+ num_slices = 2, -+ tile_align_w = 64, -+ tile_align_h = 32, -+ tile_max_w = 16384, -+ tile_max_h = 16384, -+ num_vsc_pipes = 32, -+ cs_shared_mem_size = 32 * 1024, -+ wave_granularity = 2, -+ fibers_per_sp = 128 * 2 * 16, -+ magic_regs = dict( -+ ), -+ raw_magic_regs = a8xx_gen2_raw_magic_regs, -+ )) -+ - add_gpus([ - GPUId(chip_id=0xffff44050A31, name="Adreno (TM) 840"), - ], A6xxGPUInfo( -diff --git a/src/freedreno/drm-shim/freedreno_noop.c b/src/freedreno/drm-shim/freedreno_noop.c -index 73ac6162a04..8bc1dbde164 100644 ---- a/src/freedreno/drm-shim/freedreno_noop.c -+++ b/src/freedreno/drm-shim/freedreno_noop.c -@@ -291,6 +291,16 @@ static const struct msm_device_info device_infos[] = { - .chip_id = 0x44050001, - .gmem_size = 12 * 1024 * 1024, - }, -+ { -+ .gpu_id = 810, -+ .chip_id = 0x44010000, -+ .gmem_size = 576 * 1024, -+ }, -+ { -+ .gpu_id = 829, -+ .chip_id = 0x44030A20, -+ .gmem_size = 2 * 1024 * 1024, -+ }, - }; - - static void diff --git a/packages/mesa/0022-fix-epoll-header-inclusion.patch b/packages/mesa/0022-fix-epoll-header-inclusion.patch new file mode 100644 index 00000000000..0c4c128dde5 --- /dev/null +++ b/packages/mesa/0022-fix-epoll-header-inclusion.patch @@ -0,0 +1,24 @@ +diff --git a/src/util/os_file.c b/src/util/os_file.c +index d3d3fb01580..ffffb6d4d06 100644 +--- a/src/util/os_file.c ++++ b/src/util/os_file.c +@@ -200,6 +200,10 @@ os_read_file(const char *filename, size_t *size) + return buf; + } + ++#if DETECT_OS_LINUX ++#include ++#endif ++ + #if (DETECT_OS_LINUX || DETECT_OS_FREEBSD) && ALLOW_KCMP + + #include +@@ -210,8 +214,6 @@ os_read_file(const char *filename, size_t *size) + #define KCMP_FILE 0 + #endif + +-#elif DETECT_OS_LINUX +-#include + #endif + + #if DETECT_OS_DRAGONFLY || DETECT_OS_FREEBSD diff --git a/packages/mesa/build.sh b/packages/mesa/build.sh index 5758b8ebc70..9e4396eb9cf 100644 --- a/packages/mesa/build.sh +++ b/packages/mesa/build.sh @@ -3,11 +3,12 @@ TERMUX_PKG_DESCRIPTION="An open-source implementation of the OpenGL specificatio TERMUX_PKG_LICENSE="MIT" TERMUX_PKG_LICENSE_FILE="docs/license.rst" TERMUX_PKG_MAINTAINER="@termux" -TERMUX_PKG_VERSION="26.0.6" -TERMUX_PKG_REVISION=1 -TERMUX_PKG_SRCURL=https://archive.mesa3d.org/mesa-${TERMUX_PKG_VERSION}.tar.xz -TERMUX_PKG_SHA256=1d3c3b8a8363b8cc354175bb4a684ad8b035211cc1d6fa17aeb9b9623c513f89 -TERMUX_PKG_AUTO_UPDATE=true +TERMUX_PKG_VERSION="26.2.0" +TERMUX_PKG_REVISION=99 +TERMUX_PKG_SRCURL=git+https://github.com/lfdevs/mesa-for-android-container.git +TERMUX_PKG_GIT_BRANCH=test/fix-termux-weston-xwayland-vulkan +_COMMIT=4e799fa5dac7827acdf9b9a0929b9d83ff4cbb40 +TERMUX_PKG_AUTO_UPDATE=false TERMUX_PKG_DEPENDS="libandroid-shmem, libc++, libdrm, libglvnd, libllvm (<< $TERMUX_LLVM_NEXT_MAJOR_VERSION), libwayland, libx11, libxext, libxfixes, libxshmfence, libxxf86vm, ncurses, vulkan-loader, zlib, zstd" TERMUX_PKG_SUGGESTS="mesa-dev" TERMUX_PKG_BUILD_DEPENDS="libclc, libwayland-protocols, libxrandr, llvm, llvm-tools, mlir, spirv-tools, xorgproto" @@ -28,13 +29,20 @@ TERMUX_PKG_EXTRA_CONFIGURE_ARGS=" -Dllvm=enabled -Dshared-llvm=enabled -Dplatforms=x11,wayland --Dgallium-drivers=llvmpipe,softpipe,virgl,zink -Dgallium-rusticl=true -Dglvnd=enabled -Dxmlconfig=disabled " termux_step_post_get_source() { + if [ -n "${_COMMIT}" ]; then + # Ensure the requested commit is available when cloning shallow. + if git -C "$TERMUX_PKG_SRCDIR" rev-parse --is-shallow-repository | grep -q true; then + git -C "$TERMUX_PKG_SRCDIR" fetch --unshallow + fi + git -C "$TERMUX_PKG_SRCDIR" checkout "$_COMMIT" + fi + # Do not use meson wrap projects rm -rf subprojects } @@ -76,11 +84,14 @@ termux_step_pre_configure() { export PATH="${_WRAPPER_BIN}:${CARGO_HOME}/bin:${PATH}" local _vk_drivers="swrast" + local _opengl_drivers="llvmpipe,softpipe,virgl,zink" if [ $TERMUX_ARCH = "arm" ] || [ $TERMUX_ARCH = "aarch64" ]; then _vk_drivers+=",freedreno" + _opengl_drivers+=",freedreno" TERMUX_PKG_EXTRA_CONFIGURE_ARGS+=" -Dfreedreno-kmds=msm,kgsl" fi TERMUX_PKG_EXTRA_CONFIGURE_ARGS+=" -Dvulkan-drivers=$_vk_drivers" + TERMUX_PKG_EXTRA_CONFIGURE_ARGS+=" -Dgallium-drivers=$_opengl_drivers" } termux_step_post_configure() {