os_delay with HPET interrupt

[macpacheco]

; -----------------------------------------------------------------------------
; os_delay -- Delay by X micro seconds
; IN:	RAX = Time in micro seconds
; OUT:	All registers preserved
os_delay:
	push rax
	push rbx
	push rcx
	push rdx

	mov rbx, rax	; Save delay to rbx
	xor rdx, rdx	; Zero rdx
	mov ecx, HPET_GEN_CAP
	call os_hpet_read
	shr rax, 32	; RCX = RAX >> 32
	mov rcx, rax
	mov rax, 1000000000	; Divide 10E9 (RDX:RAX) / RCX
	div rcx
	mul rbx	; RAX *= RBX, should get number of HPET cycles to wait
	mov rbx, rax ; RBX = delay * (1000000000 / (os_hpet_read(HPET_GEN_CAP) >> 32));
	mov ecx, HPET_MAIN_COUNTER
	call os_hpet_read
	add rbx, rax	; RBX += os_hpet_read(HPET_MAIN_COUNTER);
; Setup a one shot HPET interrupt when main counter=RBX
	mov ecx, HPET_TIMER_0_CONF
	mov rax, (5 << 9) | (1 << 2)
	call os_hpet_write ; os_hpet_write(HPET_TIMER_0_CONF, (5<<9)|(1<<2));

	mov rax, rbx
	mov ecx, HPET_TIMER_0_COMP
	call os_hpet_write ; os_hpet_write(HPET_TIMER_0_COMP, RBX);

; for (;;) {
microsleep_loop:
	mov rax, rbx
	mov ecx, HPET_MAIN_COUNTER
	call os_hpet_read	; rax = os_hpet_read(HPET_MAIN_COUNTER);
	cmp rax, rbx
	jae microsleep_end	; if (rax >= rbx) break;
	hlt	; else halt;
	jmp microsleep_loop
; }
microsleep_end:
	pop rdx
	pop rcx
	pop rbx
	pop rax
	ret
; -----------------------------------------------------------------------------

; =============================================================================
; BareMetal -- a 64-bit OS written in Assembly for x86-64 systems
; Copyright (C) 2008-2024 Return Infinity -- see LICENSE.TXT
;
; HPET Functions
; =============================================================================


; -----------------------------------------------------------------------------
; os_hpet_init -- Initialize the High Precision Event Timer
;  IN:	Nothing
; OUT:	Nothing
;	All other registers preserved
os_hpet_init:
	push rax
	push rcx
	push rdi
	; Pure64 has already initialized the HPET (if it existed)

	; Verify there is a valid HPET address
	mov rax, [os_HPET_Address]
	jz os_hpet_init_error

	; Set flag that HPET was enabled
	or qword [os_SysConfEn], 1 << 4

	mov edi, 0x23
	mov rax, hpet
	call create_gate

	mov ecx, 5			; HPET IRQ
	mov eax, 0x23			; HPET Interrupt Vector
	call os_ioapic_mask_clear

; setup a recurring HPET interrupt each million cycles (100Hz for an HPET with 100MHz timer)
;	mov ecx, HPET_TIMER_0_CONF
;	mov rax, (5 << 9) | (1 << 2) | (1 << 3) | (1 << 6)
;	call os_hpet_write

;	mov ecx, HPET_MAIN_COUNTER
;	call os_hpet_read
;	add rax, 1000000
;	mov ecx, HPET_TIMER_0_COMP ; First write to setup the TIMER value for the next interrupt
;	call os_hpet_write
;	mov rax, 1000000
;	mov ecx, HPET_TIMER_0_COMP ; Second tells HPET the interval to reset the interrupts
;	call os_hpet_write

os_hpet_init_error:
	pop rdi
	pop rcx
	pop rax
	ret
; -----------------------------------------------------------------------------


; -----------------------------------------------------------------------------
; os_hpet_read -- Read from a register in the High Precision Event Timer
;  IN:	ECX = Register to read
; OUT:	RAX = Register value
;	All other registers preserved
os_hpet_read:
	mov rax, [os_HPET_Address]
	mov rax, [rcx + rax]
	ret
; -----------------------------------------------------------------------------


; -----------------------------------------------------------------------------
; os_hpet_write -- Write to a register in the High Precision Event Timer
;  IN:	ECX = Register to write
;	RAX = Value to write
; OUT:	All registers preserved
os_hpet_write:
	push rcx
	add rcx, [os_HPET_Address]
	mov [rcx], rax
	pop rcx
	ret
; -----------------------------------------------------------------------------

; -----------------------------------------------------------------------------
; HPET interrupt. IRQ 0x05, INT 0x23
; This IRQ runs whenever an HPET timer expires
align 8
hpet:
	push rax
	push rcx
	pushfq

	mov  rcx, APIC_EOI
	xor  eax, eax
	call os_apic_write

	popfq
	pop  rcx
	pop  rax
	iretq


; Register list (64-bits wide)
HPET_GEN_CAP		equ 0x000 ; COUNTER_CLK_PERIOD (63:32), LEG_RT_CAP (15), COUNT_SIZE_CAP (13), NUM_TIM_CAP (12:8)
; 0x008 - 0x00F are Reserved
HPET_GEN_CONF		equ 0x010 ; LEG_RT_CNF (1), ENABLE_CNF (0)
; 0x018 - 0x01F are Reserved
HPET_GEN_INT_STATUS	equ 0x020
; 0x028 - 0x0EF are Reserved
HPET_MAIN_COUNTER	equ 0x0F0
; 0x0F8 - 0x0FF are Reserved
HPET_TIMER_0_CONF	equ 0x100
HPET_TIMER_0_COMP	equ 0x108
HPET_TIMER_0_INT	equ 0x110
; 0x118 - 0x11F are Reserved
HPET_TIMER_1_CONF	equ 0x120
HPET_TIMER_1_COMP	equ 0x128
HPET_TIMER_1_INT	equ 0x130
; 0x138 - 0x13F are Reserved
HPET_TIMER_2_CONF	equ 0x140
HPET_TIMER_2_COMP	equ 0x148
HPET_TIMER_2_INT	equ 0x150
; 0x158 - 0x15F are Reserved
; 0x160 - 0x3FF are Reserved for Timers 3-31


; =============================================================================
; EOF

I changed os_hpet_read / os_hpet_write. One of the two was clobbering a register and now both use less instructions. os_hpet_read only changes the output register.
Add a dummy hpet interrupt (IRQ 5, INT 0x23). os_delay halts between checks, otherwise the loop should be the same.
I intended this code to match the project's style. If there's anything different, or other changes, please send me a note, I'll edit the post until we're in sync.
BareMetal really needs an IRQ and INT allocator, so different drivers avoid stepping on each other.
Commented is the code to activate a periodic HPET interrupt. Eventually should be a separate routine that takes the interval in microseconds instead of a hardcoded value.

[IanSeyler]

Thanks! I've updated the os_hpet_read and os_hpet_write functions to use your optimized code: ReturnInfinity/BareMetal@f73de4c

I'll try the periodic HPET interrupt code you provided as well.

[IanSeyler]

I've added the one shot timer code you provided - ReturnInfinity/BareMetal@ab6eed0

Legacy replacement mode is enabled in Pure64 now so HPET timer 0 maps to IRQ 2 and HPET timer 1 maps to IRQ 8 by default.

[macpacheco]

Tried this code on my own bare metal and it didn't worked.
Turns out you can't dictate what IRQ HPET will use, it needs to be one of the allowed ones. And using the lowest IRQ my AMD. HPET allowed was the PIC timer one, that caused some trouble too.
So the following code chooses the highest IRQ number HPET allows.

hpet.asm:
; -----------------------------------------------------------------------------
; os_hpet_init -- Initialize the High Precision Event Timer
;  IN:	Nothing
; OUT:	Nothing
;	All other registers preserved
os_hpet_init:
	push rax
	push rcx
	push rdi
	; Pure64 has already initialized the HPET (if it existed)

	; Verify there is a valid HPET address
	mov rax, [os_HPET_Address]
	jz os_hpet_init_error

	mov ecx, HPET_TIMER_0_CONF
	call os_hpet_read
	lzcnt rax, rax ; Find the highest set bit in rax
	mov ecx, 32    ; The output of lzcnt is how many zeroes were skipped
	sub ecx, eax   ; Now we have the bit number which is the IRQ number in ecx
	mov [hpet_irq], cl ; Save IRQ number
	mov edi, ecx

	add edi, 0x20  ; Convert to gate number
	mov rax, hpet
	call create_gate

	; ECX should still contain the IRQ number HPET IRQ
	mov eax, 0x23			; HPET Interrupt Vector
	call os_ioapic_mask_clear

; setup a recurring HPET interrupt each million cycles (100Hz for an HPET with 100MHz timer)
;	mov ecx, HPET_TIMER_0_CONF
;	movzx rax, byte [os_HPET_IRQ]
;	shl rax, 9
;	or rax, (1 << 2) | (1 << 3) | (1 << 6) ; RAX = ([os_HPET_IRQ] << 9) | (1 << 2) | (1 << 3) | (1 << 6)
;	call os_hpet_write

;	mov ecx, HPET_MAIN_COUNTER
;	call os_hpet_read
;	add rax, 1000000
;	mov ecx, HPET_TIMER_0_COMP ; First write to setup the TIMER value for the next interrupt
;	call os_hpet_write
;	mov rax, 1000000
;	mov ecx, HPET_TIMER_0_COMP ; Second tells HPET the interval to reset the interrupts
;	call os_hpet_write

	; Set flag that HPET was enabled
	or qword [os_SysConfEn], 1 << 4

os_hpet_init_error:
	pop rdi
	pop rcx
	pop rax
	ret
; -----------------------------------------------------------------------------

sysvar.asm:
os_HPET_IRQ:            equ os_SystemVariables + 0x0120

syscalls/system.asm:
; Setup a one shot HPET interrupt when main counter=RBX
       mov ecx, HPET_TIMER_0_CONF
       movzx rax, byte [os_HPET_IRQ]
       shl rax, 9
       or rax, (1 << 2)
       call os_hpet_write ; os_hpet_write(HPET_TIMER_0_CONF, (os_HPET_IRQ<<9)|(1<<2));

[IanSeyler]

I'm working on integrating this.

In QEMU lzcnt rax, rax returns 0x37 (55) in RAX which means IRQ 23 is supported as the highest. That looks fine.

mov ecx, 32
sub ecx, eax

That's subtracting 55 from 32 so RCX is 0x00000000FFFFFFE9

Is that what you are expecting?

[macpacheco]

I'm working on integrating this.

In QEMU lzcnt rax, rax returns 0x37 (55) in RAX which means IRQ 23 is supported as the highest. That looks fine.

mov ecx, 32
sub ecx, eax

That's subtracting 55 from 32 so RCX is 0x00000000FFFFFFE9

Is that what you are expecting?

Yes. lzcnt returns the number of bits skipped from high to low. If the highest bit is set it returns zero, if no bits are set it returns 32 (for a 32 bit operand case).

[IanSeyler]

Ok so I'm noticing some odd behaviour with that instruction.

mov eax, 0x0F000000
lzcnt eax, eax

In QEMU EAX is set to 0x17. On physical hardware EAX is set to 0x08. From what I understand in the official docs, 0x08 is the correct answer.

Edit: VirtualBox also results in 0x08

[IanSeyler]

Fixed in ReturnInfinity/BareMetal@0ae7220

I didn't use lzcnt as it's a newer instruction. I substituted it with bsr.

[macpacheco]

Here's C code to initialize the APIC timer.
The major advantage of the APIC timer is it's a per core resource.
So a much better basis to implement os_delay so if multiple cores try to delay simultaneously it will work.
The robust way to do it requires another timing source reference to know how many ticks will pass in a given time.
This is fundamental if one wants to eventually do preemptive time slicing.
The operations performed are very straightforward to convert to assembly.

// Register list
// 0x000 - 0x010 are Reserved
#define APIC_ID		(0x020/4)		// ID Register
#define APIC_VER	(0x030/4)		// Version Register
// 0x040 - 0x070 are Reserved
#define APIC_TPR	(0x080/4)		// Task Priority Register
#define APIC_APR	(0x090/4)		// Arbitration Priority Register
#define APIC_PPR	(0x0A0/4)		// Processor Priority Register
#define APIC_EOI	(0x0B0/4)		// End Of Interrupt
#define APIC_RRD	(0x0C0/4)		// Remote Read Register
#define APIC_LDR	(0x0D0/4)		// Logical Destination Register
#define APIC_DFR	(0x0E0/4)		// Destination Format Register
#define APIC_SVR	(0x0F0/4)		// Spurious Interrupt Vector Register
#define APIC_ISR	(0x100/4)		// In-Service Register (Starting Address)
#define APIC_TMR	(0x180/4)		// Trigger Mode Register (Starting Address)
#define APIC_IRR	(0x200/4)		// Interrupt Request Register (Starting Address)
#define APIC_ESR	(0x280/4)		// Error Status Register
// 0x290 - 0x2E0 are Reserved
#define APIC_ICRL	(0x300/4)		// Interrupt Command Register (low 32 bits)
#define APIC_ICRH	(0x310/4)		// Interrupt Command Register (high 32 bits)
#define APIC_TMR_ONESHOT  0x00000   // APIC_LVT_TMR oneshot
#define APIC_TMR_PERIODIC 0x20000   // APIC_LVT_TMR periodic
#define APIC_TMR_TSCDEADL 0x40000   // APIC_LVT_TMR TSC deadline
#define APIC_TMR_DISABLE  0x10000   // APIC_LVT_TMR mask interrupts
#define APIC_LVT_TMR	(0x320/4)		// LVT Timer Register
#define APIC_LVT_TSR	(0x330/4)		// LVT Thermal Sensor Register
#define APIC_LVT_PERF	(0x340/4)		// LVT Performance Monitoring Counters Register
#define APIC_LVT_LINT0	(0x350/4)		// LVT LINT0 Register
#define APIC_LVT_LINT1	(0x360/4)		// LVT LINT1 Register
#define APIC_LVT_ERR	(0x370/4)		// LVT Error Register
#define APIC_TMRINITCNT	(0x380/4)		// Initial Count Register (for Timer)
#define APIC_TMRCURRCNT	(0x390/4)		// Current Count Register (for Timer)
// 0x3A0 - 0x3D0 are Reserved
#define APIC_TMR_2   0b0000 // TMRDIV values
#define APIC_TMR_4   0b0001
#define APIC_TMR_8   0b0010
#define APIC_TMR_16  0b0011
#define APIC_TMR_32  0b1000
#define APIC_TMR_64  0b1001
#define APIC_TMR_128 0b1010
#define APIC_TMR_1   0b1011
#define APIC_TMRDIV	(0x3E0/4)		// Divide Configuration Register (for Timer)
#define T_IRQ0 32
#define IRQ_TIMER 0
#define IRQ_KBD 1
#define IRQ_COM1 4
#define IRQ_IDE 14
#define IRQ_ERROR 19
#define IRQ_SPURIOUS 31
// 0x3F0 is Reserved

void os_apic_timer_init(void)
{   os_apic_write(APIC_TMRDIV, APIC_TMR_1); // Disable divisor - one
    os_apic_write(APIC_TMRINITCNT, 0xFFFFFFFF);
    os_delay(62500); // Wait 62.5 ms (1/16th second)
    u32 ticksin16th = 0xFFFFFFFF - os_apic_read(APIC_TMRCURRCNT);
    os_apic_write(APIC_LVT_TMR, T_IRQ0 | APIC_TMR_PERIODIC);
    os_apic_write(APIC_TMRINITCNT, ticksin16th);
    // Setup an IRQ0 handler to just tick
    create_gate(int_handler_hpet, T_IRQ0); // Now IRQ0 should be firing at 16Hz
}