diff --git a/.codespellrc b/.codespellrc new file mode 100644 index 00000000000..2ea390ce8b9 --- /dev/null +++ b/.codespellrc @@ -0,0 +1,3 @@ +[codespell] +exclude-file = .codespellx +ignore-words-list = "FPT,FTP,fpt,ftp" diff --git a/.codespellx b/.codespellx new file mode 100644 index 00000000000..e69de29bb2d diff --git a/.conform.yaml b/.conform.yaml new file mode 100644 index 00000000000..f96e4e09406 --- /dev/null +++ b/.conform.yaml @@ -0,0 +1,16 @@ +--- +policies: + - type: commit + spec: + header: + length: 80 + imperative: false + invalidLastCharacters: . + body: + required: false + dco: true + gpg: + required: true + spellcheck: + locale: US + maximumOfOneCommit: false diff --git a/.github/scripts/capsule-lint.sh b/.github/scripts/capsule-lint.sh new file mode 100755 index 00000000000..4e1aef0351b --- /dev/null +++ b/.github/scripts/capsule-lint.sh @@ -0,0 +1,87 @@ +#!/bin/bash + +function get_str() { + local cfg=$1 + local name=$2 + sed -n 's/^'"$name"'="\(.*\)"$/\1/p' "$cfg" +} + +function get_hex() { + local cfg=$1 + local name=$2 + sed -n 's/^'"$name"'=\(.*\)$/\1/p' "$cfg" +} + +function hex_to_ver_str() { + local hex=$1 + + local major=${hex:2:2} + local minor=${hex:4:2} + local bugfix=${hex:6:2} + local rc=${hex:8:2} + + local ver="v$((0x$major)).$((0x$minor)).$((0x$bugfix))" + if [ "$((0x$rc))" -lt 128 ]; then + ver="$ver-rc$((rc))" + fi + echo "$ver" +} + +if [ ! -d configs ]; then + echo "error: $(basename "$0") should be run from the root of coreboot's tree" + exit 1 +fi + +declare -A guids +fail=0 + +mapfile -t configs < <(grep -l 'EFI_UPDATE_CAPSULE' configs/config.*) +for c in "${configs[@]}"; do + local_ver=$(get_str "$c" 'CONFIG_LOCALVERSION') + + guid=$(get_str "$c" 'CONFIG_DRIVERS_EFI_MAIN_FW_GUID') + ver=$(get_hex "$c" 'CONFIG_DRIVERS_EFI_MAIN_FW_VERSION') + lsv=$(get_hex "$c" 'CONFIG_DRIVERS_EFI_MAIN_FW_LSV') + + # convert to lower case as normalization + guid=${guid,,*} + # remove common prefix to shorten error messages + c=${c##*/} + + if [ -z "$guid" ]; then + echo "$c: missing CONFIG_DRIVERS_EFI_MAIN_FW_GUID" + fail=1 + elif [ -n "${guids["$guid"]}" ]; then + echo "$c: duplicated CONFIG_DRIVERS_EFI_MAIN_FW_GUID value ($guid)" + echo "${c//?/ } also appears in ${guids["$guid"]}" + fail=1 + else + guids["$guid"]=$c + fi + + if [ -z "$ver" ]; then + echo "$c: missing CONFIG_DRIVERS_EFI_MAIN_FW_VERSION" + fail=1 + fi + if [ -z "$lsv" ]; then + echo "$c: missing CONFIG_DRIVERS_EFI_MAIN_FW_LSV" + fail=1 + fi + + if [ -n "$ver" ] && [ -n "$lsv" ] && [ $(( ver < lsv )) -eq 1 ]; then + echo "$c: CONFIG_DRIVERS_EFI_MAIN_FW_VERSION < CONFIG_DRIVERS_EFI_MAIN_FW_LSV" + echo "${c//?/ } $ver < $lsv" + fail=1 + fi + + if [ -n "$ver" ]; then + str_ver=$(hex_to_ver_str "$ver") + if [ "$str_ver" != "$local_ver" ]; then + echo "$c: CONFIG_LOCALVERSION doesn't match CONFIG_DRIVERS_EFI_MAIN_FW_VERSION" + echo "${c//?/ } $local_ver != $str_ver ($ver)" + fail=1 + fi + fi +done + +exit "$fail" diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 00000000000..1cee8b81c59 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,503 @@ +name: Dasharo +on: + pull_request: + branches: + - dasharo + - dasharo-24.12 + push: + branches: + - dasharo-24.12 + tags: + - '*' + +jobs: + build_novacustom_ec: + runs-on: ubuntu-24.04 + strategy: + matrix: + vendor: [ novacustom ] + model: [ nv4x_adl, ns5x_adl, nv4x_tgl, ns5x_tgl, v540tu, v560tu, v540tnx, v560tnx ] + steps: + - name: Checkout EC + uses: actions/checkout@v4 + with: + repository: Dasharo/ec + - name: Build EC + run: EC_BOARD_VENDOR=${{ matrix.vendor }} EC_BOARD_MODEL=${{ matrix.model }} ./build.sh + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-ec" + path: | + ${{ matrix.vendor }}_${{ matrix.model }}_ec.rom + retention-days: 30 + build_novacustom: + runs-on: ubuntu-24.04 + needs: build_novacustom_ec + strategy: + matrix: + vendor: [ novacustom ] + model: [ nv4x_adl, ns5x_adl, nv4x_tgl, ns5x_tgl, v540tu, v560tu, v540tnx, v560tnx ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Obtain EC + uses: actions/download-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-ec" + - name: Obtain blobs + uses: actions/checkout@v4 + with: + repository: Dasharo/novacustom-blobs + ref: 480afdc3d15bb9ec5b72b100581badea11e779f8 + path: 3rdparty/blobs/mainboard + token: ${{ secrets.NCM_BLOBS_TOKEN }} + - name: Build Dasharo + run: | + mv ${{ matrix.vendor }}_${{ matrix.model }}_ec.rom ec.rom + ./build.sh ${{ matrix.model }} + - name: Copy default testing keys for capsules + run: | + mkdir keys + cp payloads/external/edk2/workspace/Dasharo/BaseTools/Source/Python/Pkcs7Sign/Test* keys/ + - name: Generate capsule + run: | + ./capsule.sh make -t keys/TestRoot.pub.pem -o keys/TestSub.pub.pem -s keys/TestCert.pem -b + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + *.cap + retention-days: 30 + build_optiplex: + runs-on: ubuntu-24.04 + strategy: + matrix: + vendor: [ dell ] + model: [ optiplex_9010_sff, optiplex_9010_sff_uefi ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + ./build.sh ${{ matrix.model }} + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + retention-days: 30 + build_msi: + runs-on: ubuntu-24.04 + strategy: + matrix: + vendor: [ msi ] + model: [ ms7d25_ddr4, ms7d25_ddr5, ms7e06_ddr4, ms7e06_ddr5 ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + ./build.sh ${{ matrix.model }} + pkcs7sign=payloads/external/edk2/workspace/Dasharo/BaseTools/Source/Python/Pkcs7Sign + ./capsule.sh make -t "$pkcs7sign"/TestRoot.pub.pem \ + -o "$pkcs7sign"/TestSub.pub.pem \ + -s "$pkcs7sign"/TestCert.pem + mv *.cap build/coreboot.cap + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + build/coreboot.cap + retention-days: 30 + build_protectli: + runs-on: ubuntu-24.04 + strategy: + matrix: + vendor: [ protectli ] + model: [ vp66xx, vp46xx, vp32xx, vp2440, vp2430, vp2420, vp2410, V1210, V1211, V1410, V1610 ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + ./build.sh ${{ matrix.model }} + if grep -q CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y .config; then + pkcs7sign=payloads/external/edk2/workspace/Dasharo/BaseTools/Source/Python/Pkcs7Sign + ./capsule.sh make -t "$pkcs7sign"/TestRoot.pub.pem \ + -o "$pkcs7sign"/TestSub.pub.pem \ + -s "$pkcs7sign"/TestCert.pem + mv *.cap build/coreboot.cap + fi + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + build/coreboot.cap + retention-days: 30 + build_pcengines: + runs-on: ubuntu-24.04 + strategy: + matrix: + vendor: [ pcengines ] + model: [ apu2, apu3, apu4, apu6 ] + payload: [ uefi ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + ./build.sh ${{ matrix.model }} + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}" + path: | + build/coreboot.rom + retention-days: 30 + build_q35: + runs-on: ubuntu-24.04 + strategy: + matrix: + vendor: [ emulation_qemu ] + model: [ x86_q35 ] + payload: [ uefi, uefi_all_menus ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Build Dasharo + run: | + ./build.sh ${{ matrix.model }}_${{ matrix.payload }} + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}" + path: | + build/coreboot.rom + retention-days: 30 + test_q35: + needs: build_q35 + uses: ./.github/workflows/test.yml + strategy: + matrix: + vendor: [ emulation_qemu ] + model: [ x86_q35 ] + payload: [ uefi, uefi_all_menus ] + with: + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}" + build_hardkernel_odroid_h4: + runs-on: ubuntu-24.04 + strategy: + matrix: + vendor: [ hardkernel ] + model: [ odroid_h4, odroid_h4_netcard ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + ./build.sh ${{ matrix.model }} + pkcs7sign=payloads/external/edk2/workspace/Dasharo/BaseTools/Source/Python/Pkcs7Sign + ./capsule.sh make -t "$pkcs7sign"/TestRoot.pub.pem \ + -o "$pkcs7sign"/TestSub.pub.pem \ + -s "$pkcs7sign"/TestCert.pem + mv *.cap build/coreboot.cap + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + build/coreboot.cap + build_asrock_spc741d8: + runs-on: ubuntu-24.04 + strategy: + matrix: + vendor: [ asrock ] + model: [ spc741d8 ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + ./build.sh ${{ matrix.vendor }}_${{ matrix.model }} + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + retention-days: 30 + + deploy_protectli_adl: + if: startsWith(github.ref, 'refs/tags/protectli_vault_adl_') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp66xx ] + deploy_protectli_adl_n: + if: startsWith(github.ref, 'refs/tags/protectli_vault_adln_') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp32xx ] + deploy_protectli_vp2430: + if: startsWith(github.ref, 'refs/tags/protectli_vp2430_') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp2430 ] + deploy_protectli_vp2440: + if: startsWith(github.ref, 'refs/tags/protectli_vp2440_') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp2440 ] + deploy_protectli_jsl: + if: startsWith(github.ref, 'refs/tags/protectli_vault_jsl') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ V1210, V1211, V1410, V1610 ] + deploy_protectli_glk: + if: startsWith(github.ref, 'refs/tags/protectli_vault_glk') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp2410 ] + deploy_protectli_ehl: + if: startsWith(github.ref, 'refs/tags/protectli_vault_ehl') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp2420 ] + deploy_protectli_cml: + if: startsWith(github.ref, 'refs/tags/protectli_vault_cml') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp46xx ] + deploy_novacustom_adl: + if: startsWith(github.ref, 'refs/tags/novacustom') && contains(github.ref, 'adl') + needs: build_novacustom + uses: ./.github/workflows/deploy-template.yml + with: + platform: novacustom + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ novacustom ] + model: [ nv4x_adl, ns5x_adl ] + deploy_novacustom_tgl: + if: startsWith(github.ref, 'refs/tags/novacustom') && contains(github.ref, 'tgl') + needs: build_novacustom + uses: ./.github/workflows/deploy-template.yml + with: + platform: novacustom + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ novacustom ] + model: [ nv4x_tgl, ns5x_tgl ] + deploy_pcengines: + if: startsWith(github.ref, 'refs/tags/pcengines') + needs: build_pcengines + uses: ./.github/workflows/deploy-template.yml + with: + platform: pcengines + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + payload: ${{ matrix.payload }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}" + secrets: inherit + strategy: + matrix: + vendor: [ pcengines ] + model: [ apu2, apu3, apu4, apu6 ] + payload: [ uefi ] + deploy_msi_ms7d25: + if: startsWith(github.ref, 'refs/tags/msi_ms7d25') + needs: build_msi + uses: ./.github/workflows/deploy-template.yml + with: + platform: msi + vendor: ${{ matrix.vendor }} + model: "ms7d25" + type: ${{ matrix.type }} + artifact_name: "dasharo-${{ matrix.vendor }}-ms7d25_${{ matrix.type }}" + released_by_3mdeb: true + secrets: inherit + strategy: + matrix: + vendor: [ msi ] + type: [ ddr4, ddr5 ] + deploy_msi_ms7e06: + if: startsWith(github.ref, 'refs/tags/msi_ms7e06') + needs: build_msi + uses: ./.github/workflows/deploy-template.yml + with: + platform: msi + vendor: ${{ matrix.vendor }} + model: "ms7e06" + type: ${{ matrix.type }} + artifact_name: "dasharo-${{ matrix.vendor }}-ms7e06_${{ matrix.type }}" + released_by_3mdeb: true + secrets: inherit + strategy: + matrix: + vendor: [ msi ] + type: [ ddr4, ddr5 ] + deploy_hardkernel_odroid: + if: startsWith(github.ref, 'refs/tags/hardkernel_odroid_h4') + needs: build_hardkernel_odroid_h4 + uses: ./.github/workflows/deploy-template.yml + with: + platform: hardkernel + model: ${{ matrix.model }} + vendor: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + released_by_3mdeb: true + secrets: inherit + strategy: + matrix: + vendor: [ hardkernel ] + model: [ odroid_h4 ] diff --git a/.github/workflows/checks.yml b/.github/workflows/checks.yml new file mode 100644 index 00000000000..9142e82af46 --- /dev/null +++ b/.github/workflows/checks.yml @@ -0,0 +1,63 @@ +name: Dasharo Checks +on: + push: + +jobs: + + check-upstream-status: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v3 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # This should be enough, no need to have ~60000 commits + fetch-depth: 2000 + - uses: actions/setup-python@v3 + - uses: pre-commit/action@v3.0.1 + with: + extra_args: check-upstream-status --hook-stage pre-push + + lint: + runs-on: ubuntu-22.04 + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Top commit is enough + fetch-depth: 1 + - name: Standard lint tests + run: util/lint/lint lint-stable + - name: Extended lint tests + run: util/lint/lint lint-extended + + check-defconfigs: + runs-on: ubuntu-22.04 + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Top commit is enough + fetch-depth: 1 + - name: Verify defconfigs are up-to-date + run: | + # Start with the list of Dasharo boards, indicated by CONFIG_DASHARO + boards=( $(grep -l 'CONFIG_DASHARO=y' configs/config.*) ) + + # Update all of them before reporting anything + for c in $(printf "%s\n" "${boards[@]}" | sort); do + make savedefconfig DOTCONFIG="$c" + mv defconfig "$c" + done + + # Print all the differences at once and fail or do nothing + git diff --exit-code + - name: Verify update capsules support in defconfigs + run: .github/scripts/capsule-lint.sh diff --git a/.github/workflows/deploy-template.yml b/.github/workflows/deploy-template.yml new file mode 100644 index 00000000000..0ce66f563f3 --- /dev/null +++ b/.github/workflows/deploy-template.yml @@ -0,0 +1,121 @@ +name: Reusable Deploy workflow +on: + workflow_call: + inputs: + platform: + type: string + vendor: + type: string + required: false + model: + type: string + required: false + payload: + type: string + required: false + type: + type: string + required: false + artifact_name: + type: string + # Set to true for DPP/community releases by 3mdeb + released_by_3mdeb: + type: boolean + +jobs: + deploy: + runs-on: ubuntu-22.04 + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Set up tag name + id: tag_name + run: echo "tag=${GITHUB_REF#refs/tags/}" >> "$GITHUB_OUTPUT" + + - name: Parse directories + id: parse_directories + run: | + + tag=${{ steps.tag_name.outputs.tag }} + # Extract platform model string (everything before the last underscore in the tag) + model=$(echo "$tag" | awk -F'_' '{OFS="_"; $(NF)=""; print $0}' | sed 's/_$//') + # Extract version string (everything after the last underscore in the tag) + release=$(echo "$tag" | awk -F'_' '{print $NF}') + + # Use 3mdeb directory for community / DPP releases + if ${{ inputs.released_by_3mdeb }} ; then + base_dir="3mdeb" + else + # by default, use platform vendor name as a directory + base_dir="${{ inputs.platform }}" + fi + + echo "base_dir=$base_dir" >> "$GITHUB_OUTPUT" + echo "model=$model" >> "$GITHUB_OUTPUT" + echo "release=$release" >> "$GITHUB_OUTPUT" + + - name: Download workflow artifact + uses: actions/download-artifact@v4 + with: + name: ${{ inputs.artifact_name }} + path: "./artifacts" + + - name: Upload to Nextcloud + run: | + BASE_URL="https://cloud.3mdeb.com/public.php/webdav" + url_part=$(echo "${{ secrets.CLOUD_URL }}" | cut -d'/' -f6) + base_dir="${{ steps.parse_directories.outputs.base_dir }}" + model="${{ steps.parse_directories.outputs.model }}" + release="${{ steps.parse_directories.outputs.release }}" + CURL_CMD="curl -u $url_part:${{ secrets.CLOUD_PASSWORD }}" + + case "$model" in + *vp2430*|*vp2440*|*vp3230*|*3210*) + subdir="$model" + model="protectli_adln" + ;; + *) + subdir="" + ;; + esac + + if [ "${{ inputs.platform }}" == "pcengines" ]; then + new_name="pcengines_${{ inputs.model }}_${release}.rom" + else + new_name="${{ inputs.model }}_${release}.rom" + if [ ! -z "${{ inputs.vendor }}" ]; then + new_name="${{ inputs.vendor }}_${new_name}" + fi + if [ ! -z "${{ inputs.payload }}" ]; then + new_name=$(echo "$new_name" | awk -F'_' '{OFS="_"; $NF="${{ inputs.payload }}_"$NF; print}') + fi + if [ ! -z "${{ inputs.type }}" ]; then + new_name=$(echo "${new_name%.rom}_${{ inputs.type }}.rom") + fi + fi + + # Prepare cloud path + + if [[ "$model" == *adln* ]]; then + # If subdir is empty, assign default + if [[ -z "$subdir" ]]; then + subdir="protectli_vp32xx" + fi + path="$base_dir/$model/$subdir/$release" + else + path="$base_dir/$model/$release" + fi + + # Create release directory if it doesn't exist recursively + IFS='/' read -ra DIRS <<< "$path" + current="" + for part in "${DIRS[@]}"; do + current="${current:+$current/}$part" + $CURL_CMD -X MKCOL "$BASE_URL/$current" || true + done + + # upload firmware and hash files + $CURL_CMD -X PUT -T "artifacts/coreboot.rom" "$BASE_URL/$base_dir/$model/$release/$new_name" + sha256sum artifacts/coreboot.rom > ${new_name}.sha256 + $CURL_CMD -X PUT -T "${new_name}.sha256" "$BASE_URL/$base_dir/$model/$release/" diff --git a/.github/workflows/tag-check.yml b/.github/workflows/tag-check.yml new file mode 100644 index 00000000000..dbd772c1836 --- /dev/null +++ b/.github/workflows/tag-check.yml @@ -0,0 +1,48 @@ +name: Check tag is annotated & signed + +on: + push: + tags: + - '*' + +jobs: + verify-tag: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + + - name: Force fetch tags + run: | + git fetch --tags --force --prune + + - name: Check tag is annotated + shell: bash + run: | + set -euo pipefail + tag="${GITHUB_REF_NAME}" + ref="refs/tags/${tag}" + + if ! git show-ref --verify --quiet "$ref"; then + echo "::error::Tag '${tag}' not found after checkout" + exit 1 + fi + + type="$(git cat-file -t "$ref")" # 'tag' for annotated, 'commit' for lightweight + if [[ "$type" != "tag" ]]; then + echo "::error::Tag '${tag}' is not annotated: type '$type'. Use: git tag -s" + exit 1 + fi + + - name: Check tag has a signature block + shell: bash + run: | + set -euo pipefail + tag="${GITHUB_REF_NAME}" + ref="refs/tags/${tag}" + + if git cat-file -p "$ref" | grep -q '^-----BEGIN PGP SIGNATURE-----$'; then + echo "Tag '${tag}' contains a signature block" + else + echo "::error::Tag '${tag}' is NOT signed. Create it with: git tag -s" + exit 1 + fi diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml new file mode 100644 index 00000000000..b144c1b34be --- /dev/null +++ b/.github/workflows/test.yml @@ -0,0 +1,74 @@ +name: q35 testing workflow +on: + workflow_call: + inputs: + artifact_name: + type: string + +jobs: + test_in_qemu: + runs-on: ubuntu-24.04 + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Checkout OSFV repository and submodules + uses: actions/checkout@v4 + with: + repository: 'Dasharo/open-source-firmware-validation' + ref: 'develop' + submodules: 'recursive' + fetch-depth: 0 + + - name: Download workflow artifact + uses: actions/download-artifact@v4 + with: + name: ${{ inputs.artifact_name }} + + - name: Set up required tools + run: | + sudo apt-get update + sudo apt-get install qemu-system-x86-64 swtpm git-annex + + # Pulling secure-boot/sb_test_data.img fails, carry on anyway + - name: Set up osfv-test-data + run: | + pushd osfv-test-data + git config --global user.email "you@example.com" + git config --global user.name "Your Name" + git annex pull || true + ./setup.sh + popd + + - name: Enable KVM group perms + run: | + echo 'KERNEL=="kvm", GROUP="kvm", MODE="0666", OPTIONS+="static_node=kvm"' | sudo tee /etc/udev/rules.d/99-kvm4all.rules + sudo udevadm control --reload-rules + sudo udevadm trigger --name-match=kvm + + # OSFV scripts/ci/qemu-run.sh expects QEMU_FW_FILE="./qemu_q35.rom" + # VirtIO disks will be mounted dynamically later with esp-scanning.robot, + # no need to create and attach one here with `os` instead of `firmware` + - name: Start QEMU in background + run: | + mv coreboot.rom qemu_q35.rom + ./scripts/ci/qemu-run.sh nographic firmware & + + - name: Set up Python + uses: actions/setup-python@v2 + with: + python-version: '3.13' + + - name: Install dependencies + run: | + python -m pip install --upgrade pip + pip install -r requirements.txt + + - name: Start custom-boot-menu-key.robot, test case CBK001.001 and CBK002.001 + run: | + robot -b command_log_CBK001.001.txt -v fw_file:qemu_q35.rom -v snipeit:no -L TRACE -v config:qemu -v rte_ip:127.0.0.1 -t "CBK001.001*" dasharo-compatibility/custom-boot-menu-key.robot + robot -b command_log_CBK002.001.txt -v fw_file:qemu_q35.rom -v snipeit:no -L TRACE -v config:qemu -v rte_ip:127.0.0.1 -t "CBK002.001*" dasharo-compatibility/custom-boot-menu-key.robot + + - name: Start esp-scanning.robot + run: | + robot -d ./logs/$(date +%Y.%m.%d_%H.%M.%S)/self-tests -v fw_file:qemu_q35.rom -v snipeit:no -L TRACE -v config:qemu -v rte_ip:127.0.0.1 dasharo-compatibility/esp-scanning.robot diff --git a/.github/workflows/ucode.yml b/.github/workflows/ucode.yml new file mode 100644 index 00000000000..a55e063c636 --- /dev/null +++ b/.github/workflows/ucode.yml @@ -0,0 +1,62 @@ +name: Refresh Intel µcode submodule + +on: + schedule: + # At 23:35 on every day-of-week from Sunday through Saturday + # https://crontab.guru/#35_23_*_*_0-6 + - cron: '35 23 * * 0-6' + workflow_dispatch: + +jobs: + check: + runs-on: ubuntu-latest + + steps: + - name: Checkout Code + uses: actions/checkout@v4 + + - name: Check if µcode submodule is up to date + run: | + git submodule update --init --checkout 3rdparty/intel-microcode + pushd 3rdparty/intel-microcode + current=$(git log -1 --pretty=format:"%H") + git checkout main + new=$(git log -1 --pretty=format:"%H") + popd + if [[ $current == $new ]]; then + echo "Intel µcode submodule is up-to-date." + else + echo "Intel µcode submodule is out of date!" + exit 1 + fi + + update: + runs-on: ubuntu-latest + needs: check + if: | + always() && needs.check.result == 'failure' + + steps: + - name: Checkout Code + uses: actions/checkout@v4 + + - name: Update µcode submodule + run: | + git submodule update --init --checkout 3rdparty/intel-microcode + pushd 3rdparty/intel-microcode + git checkout main + popd + + - name: Set current date + run: | + pushd 3rdparty/intel-microcode + echo "RELEASE_DATE=$(git log -1 --pretty='format:%cs')" >> ${GITHUB_ENV} + popd + + - name: Submit pull request + uses: peter-evans/create-pull-request@v7.0.7 + with: + base: dasharo + branch: update_ucode_${{ env.RELEASE_DATE }} + title: Update µcode ${{ env.RELEASE_DATE }} + commit-message: "[automated change] Update µcode ${{ env.RELEASE_DATE }}\n\nUpstream-Status: Inappropriate (Dasharo automation)" diff --git a/.gitignore b/.gitignore index e813493526f..8fb8a8f99ae 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,8 @@ build/ coreboot-builds/ coreboot-builds*/ generated/ +uefiextract +UEFIExtract_NE_A68_x64_linux.zip site-local @@ -26,6 +28,7 @@ site-local *.pyc *.sw[po] /*.rom +*.rom.sha256 .test .dependencies diff --git a/.gitmodules b/.gitmodules index c1d7849a9e9..300e11a6457 100644 --- a/.gitmodules +++ b/.gitmodules @@ -68,3 +68,6 @@ [submodule "3rdparty/open-power-signing-utils"] path = 3rdparty/open-power-signing-utils url = https://review.coreboot.org/open-power-signing-utils.git +[submodule "3rdparty/dasharo-blobs"] + path = 3rdparty/dasharo-blobs + url = https://github.com/Dasharo/dasharo-blobs.git diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml new file mode 100644 index 00000000000..42c3b0431f4 --- /dev/null +++ b/.pre-commit-config.yaml @@ -0,0 +1,55 @@ +--- +default_stages: [pre-commit] + +default_install_hook_types: [pre-commit, commit-msg] + +ci: + autoupdate_commit_msg: 'pre-commit: autoupdate hooks' + autofix_prs: false + +repos: + - repo: https://github.com/pre-commit/pre-commit-hooks + rev: v4.4.0 + hooks: + - id: check-added-large-files + - id: check-merge-conflict + - id: check-symlinks + - id: detect-private-key + # Consider re-enabling (a lot of coreboot code is affected, but with + # vendorcode excluded is much less) + # - id: end-of-file-fixer + # exclude: "src/vendorcode" + # - id: trailing-whitespace + # exclude: "src/vendorcode" + - id: mixed-line-ending + + - repo: https://github.com/talos-systems/conform + rev: v0.1.0-alpha.27 + hooks: + - id: conform + stages: + - commit-msg + + # Consider re-enabling (a lot of coreboot code is affected, but with + # vendorcode excluded it is much less) + # - repo: https://github.com/codespell-project/codespell + # rev: v2.2.5 + # hooks: + # - id: codespell + + - repo: local + hooks: + - id: coreboot_lint + name: Runs coreboot lint-stable linter checks + entry: util/lint/lint lint-stable + language: script + types: [file] + + - repo: https://github.com/3mdeb/hooks + rev: v0.1.7 + # Can be triggered manually with command: + # pre-commit run --hook-stage pre-push check-upstream-status + hooks: + - id: check-upstream-status + args: [--base, origin/dasharo] + stages: [pre-push] diff --git a/3rdparty/dasharo-blobs b/3rdparty/dasharo-blobs new file mode 160000 index 00000000000..8dce760434d --- /dev/null +++ b/3rdparty/dasharo-blobs @@ -0,0 +1 @@ +Subproject commit 8dce760434d3cf3c6acfc7c2f07028d37365aa79 diff --git a/3rdparty/fsp b/3rdparty/fsp index 851f7105d80..5d0424c89dd 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 851f7105d803672e17202bc2f598a5a4dbf659d3 +Subproject commit 5d0424c89ddd4903cdd31eb36bc1c921c15422e3 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 8ac9378a848..4ded52b4b0e 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 8ac9378a84879e81c503e09f344560b3dd7f72df +Subproject commit 4ded52b4b0e1d60e83259cc88d1f5ad22f71a63e diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md index 6956cd49e1a..816f917dc14 100644 --- a/Documentation/drivers/smmstorev2.md +++ b/Documentation/drivers/smmstorev2.md @@ -197,6 +197,31 @@ coreboot tables, there's no risk that a malicious application capable of issuing SMIs could extract arbitrary data or modify the currently running kernel. +## Capsule update API + +To allow updating full flash content (except if locked at hardware +level), few new calls were added. They reuse communication buffer, SMI +command, return values and calling arguments of SMMSTORE commands listed +above, with the exception of subcommand passed via `%ah`. If the +subcommand is to operate on full flash size, it has the highest bit set, +e.g. it is `0x85` for `SMMSTORE_CMD_RAW_READ` and `0x86` for +`SMMSTORE_CMD_RAW_WRITE`. Every `block_id` describes block relative to +beginning of a flash, maximum value depends on its size. + +In addition, there is one new subcommand that must be called before any +other subcommands with highest bit set can be used. + +#### - SMMSTORE_CMD_USE_FULL_FLASH = 0x80 + +This command can only be executed once and is done by the firmware. +Calling this function at runtime has no effect. It takes one additional +parameter that, contrary to other commands, isn't a pointer. Instead, +`%ebx` indicates requested state of full flash access. If it equals 0, +commands for accessing full flash are permanently disabled, otherwise +they are permanently enabled until next boot. It is expected that the +payload won't allow regular OS to boot if the handler is enabled without +rebooting first. + ## External links * [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf) diff --git a/FUNDING.yml b/FUNDING.yml new file mode 100644 index 00000000000..4e77cf822a0 --- /dev/null +++ b/FUNDING.yml @@ -0,0 +1,2 @@ + +open_collective: 3mdeb_com diff --git a/Makefile.mk b/Makefile.mk index ca79d053ad4..10f707b9d1d 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -115,8 +115,8 @@ subdirs-y += $(filter-out src/superio/common,$(wildcard src/superio/*)) $(wildca subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool -subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu -subdirs-y += util/ifdtool +subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu util/msi +subdirs-y += util/ifdtool util/txesbmantool subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += src/security @@ -235,9 +235,7 @@ ifeq ($(CONFIG_USE_BLOBS),y) # until expressly requested and enabled with --checkout forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors)) forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors)) -ifeq ($(CONFIG_FSP_USE_REPO),y) forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors)) -endif ifeq ($(CONFIG_USE_AMD_BLOBS),y) forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors)) endif @@ -477,9 +475,20 @@ ifeq ($(CONFIG_COMPRESS_PRERAM_STAGES),y) CBFS_PRERAM_COMPRESS_FLAG:=LZ4 endif +strip_version = $(strip $(subst v,,$(subst ., ,$(1)))) + ifneq ($(CONFIG_LOCALVERSION),"") COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) +DASHARO_VERSION := $(call strip_quotes,$(CONFIG_LOCALVERSION)) +DASHARO_MAJOR_VERSION := $(word 1,$(call strip_version,$(DASHARO_VERSION))) +DASHARO_MINOR_VERSION := $(word 2,$(call strip_version,$(DASHARO_VERSION))) +DASHARO_PATCH_VERSION := $(word 3,$(call strip_version,$(DASHARO_VERSION))) + COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION +COREBOOT_EXPORTS += DASHARO_VERSION +COREBOOT_EXPORTS += DASHARO_MAJOR_VERSION +COREBOOT_EXPORTS += DASHARO_MINOR_VERSION +COREBOOT_EXPORTS += DASHARO_PATCH_VERSION endif CPPFLAGS_common := -Isrc @@ -648,7 +657,9 @@ build_h := $(obj)/build.h # when we call it through the `$(shell)` function. This is fragile # but as variables newly added to `genbuild_h.sh` would just not # work, we'd notice that instantly at least. -build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION +build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION \ + DASHARO_VERSION DASHARO_MAJOR_VERSION DASHARO_MINOR_VERSION \ + DASHARO_PATCH_VERSION # Report new `build.ht` as dependency if `build.h` differs. build_h_check := \ @@ -680,6 +691,12 @@ CSE_SERGER:=$(objutil)/cbfstool/cse_serger ECCTOOL:=$(objutil)/ffs/ecc/ecc CREATE_CONTAINER:=$(objutil)/open-power-signing-utils/create-container +ifeq ($(CONFIG_TXE_SECURE_BOOT),y) +TXESBMANTOOL:=$(objutil)/txesbmantool/txesbmantool +else +TXESBMANTOOL:= +endif + $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -846,7 +863,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.mk .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) $(ECCTOOL) $(CREATE_CONTAINER) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(objutil)/msi/romholetool $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) $(ECCTOOL) $(CREATE_CONTAINER) $(TXESBMANTOOL) ########################################################################### # Common recipes for all stages @@ -1061,9 +1078,12 @@ placed-files-in-region = $(foreach file,$(call all-files-in-region,$(1)), \ # $(call sort-files,subset of $(cbfs-files)) # reorders the files in the given set to list files at fixed positions first, -# followed by aligned files and finally those with no constraints. +# followed by a payload (which might be big, best to place it first when there +# are few files in CBFS), followed by aligned files, and finally those with +# no constraints. sort-files = \ $(eval _tmp_fixed:=) \ + $(eval _tmp_payload:=) \ $(eval _tmp_aligned:=) \ $(eval _tmp_regular:=) \ $(foreach file,$(1), \ @@ -1071,8 +1091,10 @@ sort-files = \ $(eval _tmp_fixed += $(file)), \ $(if $(call extract_nth,6,$(file)), \ $(eval _tmp_aligned += $(file)), \ - $(eval _tmp_regular += $(file))))) \ - $(_tmp_fixed) $(_tmp_aligned) $(_tmp_regular) + $(if $(filter payload,$(call extract_nth,3,$(file))), \ + $(eval _tmp_payload += $(file)), \ + $(eval _tmp_regular += $(file)))))) \ + $(_tmp_fixed) $(_tmp_payload) $(_tmp_aligned) $(_tmp_regular) # command list to add files to CBFS prebuild-files = $(foreach region,$(all-regions), \ diff --git a/build.sh b/build.sh new file mode 100755 index 00000000000..a1dd2c2fceb --- /dev/null +++ b/build.sh @@ -0,0 +1,494 @@ +#!/bin/bash + +set -euo pipefail + +usage() { + echo "${0} CMD" + echo "Available CMDs:" + echo -e "\tz690a_ddr4 - build Dasharo image compatible with MSI PRO Z690-A (WIFI) DDR4" + echo -e "\tz690a_ddr5 - build Dasharo image compatible with MSI PRO Z690-A (WIFI)" + echo -e "\tz790p_ddr4 - build Dasharo image compatible with MSI PRO Z790-P (WIFI) DDR4" + echo -e "\tz790p_ddr5 - build Dasharo image compatible with MSI PRO Z790-P (WIFI)" + echo -e "\tvp66xx - build Dasharo for Protectli VP66xx" + echo -e "\tvp46xx - build Dasharo for Protectli VP46xx" + echo -e "\tvp32xx - build Dasharo for Protectli VP32xx" + echo -e "\tvp2440 - build Dasharo for Protectli VP2440" + echo -e "\tvp2430 - build Dasharo for Protectli VP2430" + echo -e "\tvp2420 - build Dasharo for Protectli VP2420" + echo -e "\tvp2410 - build Dasharo for Protectli VP2410" + echo -e "\tV1210 - build Dasharo for Protectli V1210" + echo -e "\tV1211 - build Dasharo for Protectli V1211" + echo -e "\tV1410 - build Dasharo for Protectli V1410" + echo -e "\tV1610 - build Dasharo for Protectli V1610" + echo -e "\tns5x_adl - build Dasharo for Novacustom NS5x_ADL" + echo -e "\tns5x_tgl - build Dasharo for Novacustom NS5x_TGL" + echo -e "\tnv4x_adl - build Dasharo for Novacustom NV4x_ADL" + echo -e "\tnv4x_tgl - build Dasharo for Novacustom NV4x_TGL" + echo -e "\tv540tnx - build Dasharo for Novacustom V540TNx" + echo -e "\tv540tu - build Dasharo for Novacustom V540TU" + echo -e "\tv560tnx - build Dasharo for Novacustom V560TNx" + echo -e "\tv560tu - build Dasharo for Novacustom V560TU" + echo -e "\tnuc_box - build Dasharo for Novacustom NUC BOX" + echo -e "\tapu2 - build Dasharo for PC Engines APU2" + echo -e "\tapu3 - build Dasharo for PC Engines APU3" + echo -e "\tapu4 - build Dasharo for PC Engines APU4" + echo -e "\tapu6 - build Dasharo for PC Engines APU6" + echo -e "\toptiplex_9010_uefi - build Dasharo compatible with Dell OptiPlex 7010/9010 (UEFI)" + echo -e "\toptiplex_9010_seabios - build Dasharo compatible with Dell OptiPlex 7010/9010 (SeaBIOS)" + echo -e "\tqemu - build Dasharo for QEMU Q35" + echo -e "\tqemu_full - build Dasharo for QEMU Q35 with all menus available" + echo -e "\todroid_h4 - build Dasharo compatible with Hardkernel ODROID H4" + echo -e "\todroid_h4_netcard - build Dasharo compatible with Hardkernel ODROID H4 for netcard support" + echo -e "\tasrock_spc741d8 - build Dasharo compatible with ASRock Rack SPC741D8-2L2T/BCM" +} + +DASHARO_SDK=${DASHARO_SDK:-"ghcr.io/dasharo/dasharo-sdk:v1.6.0"} +BUILD_TIMELESS=${BUILD_TIMELESS:-0} +AIRGAP=${AIRGAP:-0} + +function sdk_run { + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -e BUILD_TIMELESS=${BUILD_TIMELESS} \ + -w /home/coreboot/coreboot ${DASHARO_SDK} \ + "$@" +} + +function build_prep { + if [ "${AIRGAP}" -eq 1 ]; then + sdk_run /bin/bash -c "make clean" + else + sdk_run /bin/bash -c "make distclean" + fi + + cp "${DEFCONFIG}" .config + + git submodule update --init --checkout $@ +} + +function build_start { + if [ "${AIRGAP}" -eq 1 ]; then + + # In this situation we assume that provided repository is ready to be used + # and nothing should be downloaded during build process. + + if [ -d "${EDK2_REPO_PATH}" ]; then + # Without following sequence workspce would be created by docker with root + # privilidges and build will fail. + # Target directory + TARGET_DIR="payloads/external/edk2/workspace/Dasharo" + mkdir -p "$TARGET_DIR" + chown -R $(id -u):$(id -g) "$TARGET_DIR" + chmod -R 755 "$TARGET_DIR" + sdk_run --network none \ + ${EDK2_REPO_PATH:+-v $EDK2_REPO_PATH:/home/coreboot/coreboot/${TARGET_DIR}} \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + else + echo "EDK2_REPO_PATH is not defined in AIRGAP!" + exit 1 + fi + else + sdk_run /bin/bash -c "make olddefconfig && make -j$(nproc)" + fi +} + +function build_optiplex_9010 { + DEFCONFIG=$1 + # Determine FW flavor first (uefi or seabios) + if [[ ${DEFCONFIG} == *"uefi"* ]]; then + FW_FLAVOR="uefi" + else + FW_FLAVOR="seabios" + fi + + # Get FW version + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + # Combine FW flavor with version + FW_VERSION="${FW_FLAVOR}_${FW_VERSION}" + + build_prep + + echo "Building Dasharo compatible with Dell OptiPlex 7010/9010 (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom ${BOARD}_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/${BOARD}_${FW_VERSION}.rom" + sha256sum ${BOARD}_${FW_VERSION}.rom > ${BOARD}_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_msi { + DEFCONFIG="configs/config.${BOARD}_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + build_prep + + echo "Building Dasharo compatible with MSI PRO $2(WIFI) (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom ${BOARD}_${FW_VERSION}_$1.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/${BOARD}_${FW_VERSION}_$1.rom" + sha256sum ${BOARD}_${FW_VERSION}_$1.rom > ${BOARD}_${FW_VERSION}_$1.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_protectli_vault { + DEFCONFIG="configs/config.protectli_${BOARD}" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + LOGO="3rdparty/dasharo-blobs/protectli/bootsplash.bmp" + + build_prep + + echo "Building Dasharo for Protectli $BOARD (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom protectli_${BOARD}_${FW_VERSION}.rom + + sdk_run /bin/bash -c "./build/cbfstool \ + protectli_${BOARD}_${FW_VERSION}.rom add \ + -r BOOTSPLASH \ + -f \"$LOGO\" \ + -n logo.bmp \ + -t raw \ + -c lzma" + + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/protectli_${BOARD}_${FW_VERSION}.rom" + sha256sum protectli_${BOARD}_${FW_VERSION}.rom > protectli_${BOARD}_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_v1x10 { + DEFCONFIG="configs/config.protectli_vault_jsl_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + LOGO="3rdparty/dasharo-blobs/protectli/bootsplash.bmp" + + build_prep + + echo "Building Dasharo for Protectli $1 (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom protectli_$1_${FW_VERSION}.rom + + sdk_run /bin/bash -c "./build/cbfstool \ + ./protectli_${1}_${FW_VERSION}.rom add \ + -r BOOTSPLASH \ + -f \"$LOGO\" \ + -n logo.bmp \ + -t raw \ + -c lzma" + + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/protectli_$1_${FW_VERSION}.rom" + sha256sum protectli_$1_${FW_VERSION}.rom > protectli_$1_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_novacustom { + DEFCONFIG="configs/config.novacustom_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + build_prep + + echo "Building Dasharo for Novacustom $1 (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom novacustom_$1_${FW_VERSION}.rom + + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/novacustom_$1_${FW_VERSION}.rom" + sha256sum novacustom_$1_${FW_VERSION}.rom > novacustom_$1_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + + +function build_novacustom_v5x0tu { + DEFCONFIG="configs/config.novacustom_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + build_prep + + # Obtain LAN ROM blob from release binary + wget -O UEFIExtract_NE_A68_x64_linux.zip https://github.com/LongSoft/UEFITool/releases/download/A68/UEFIExtract_NE_A68_x64_linux.zip + unzip -o UEFIExtract_NE_A68_x64_linux.zip + wget -O novacustom_v54x_mtl_v0.9.0.rom https://dl.3mdeb.com/open-source-firmware/Dasharo/novacustom_v54x_mtl/v0.9.0/novacustom_v54x_mtl_v0.9.0.rom + + # Extract and transfer LAN ROM blob + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot ${DASHARO_SDK} \ + /bin/bash -c "make -C util/cbfstool && \ + util/cbfstool/cbfstool novacustom_v54x_mtl_v0.9.0.rom extract -r COREBOOT -f payload -n fallback/payload -m x86" + + ./uefiextract payload DEB917C0-C56A-4860-A05B-BF2F22EBB717 + mkdir -p 3rdparty/blobs/mainboard/novacustom/mtl-h + cp payload.dump/2\ 8C8CE578-8A3D-4F1C-9935-896185C32DD3/82\ DEB917C0-C56A-4860-A05B-BF2F22EBB717/1\ PE32\ image\ section/body.bin 3rdparty/blobs/mainboard/novacustom/mtl-h/LanRom.efi + rm -rf payload.dump + + echo "Building Dasharo for Novacustom $1 (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom novacustom_$1_${FW_VERSION}.rom + + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/novacustom_$1_${FW_VERSION}.rom" + sha256sum novacustom_$1_${FW_VERSION}.rom > novacustom_$1_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_pcengines { + VARIANT=$1 + DEFCONFIG="configs/config.pcengines_uefi_${VARIANT}" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + # checkout several submodules needed by these boards (some others are checked + # out by coreboot's Makefile) + build_prep 3rdparty/dasharo-blobs 3rdparty/vboot + + echo "Building Dasharo for PC Engines ${VARIANT^^*} (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom pcengines_${VARIANT}_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/pcengines_${VARIANT}_${FW_VERSION}.rom" + sha256sum pcengines_${VARIANT}_${FW_VERSION}.rom > pcengines_${VARIANT}_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_qemu { + DEFCONFIG="configs/config.emulation_qemu_x86_q35_uefi${1:-}" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + # checkout several submodules needed by these boards (some others are checked + # out by coreboot's Makefile) + build_prep 3rdparty/dasharo-blobs + + echo "Building Dasharo for QEMU Q35 (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom qemu_q35_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/qemu_q35_${FW_VERSION}.rom" + sha256sum qemu_q35_${FW_VERSION}.rom > qemu_q35_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_odroid_h4 { + VARIANT=$1 + DEFCONFIG="configs/config.hardkernel_${VARIANT}" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + # checkout several submodules needed by these boards (some others are checked + # out by coreboot's Makefile) + build_prep 3rdparty/dasharo-blobs + + echo "Building Dasharo compatbile with Hardkernel ODROID H4 (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom hardkernel_${VARIANT}_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/hardkernel_${VARIANT}_${FW_VERSION}.rom" + sha256sum hardkernel_${VARIANT}_${FW_VERSION}.rom > hardkernel_${VARIANT}_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_asrock_rack { + DEFCONFIG="configs/config.asrock_spc741d8" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + build_prep + + echo "Building Dasharo for ASRock Rack SPC741D8-2L2T/BCM (version $FW_VERSION)" + + build_start + + cp build/coreboot.rom asrock_spc741d8_${FW_VERSION}.rom + + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/asrock_spc741d8_${FW_VERSION}.rom" + sha256sum asrock_spc741d8_${FW_VERSION}.rom > asrock_spc741d8_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +if [ $# -lt 1 ]; then + usage + exit +fi + +CMD="$1" + +case "$CMD" in + "ddr4" | "z690a_ddr4" | "ms7d25_ddr4") + BOARD="msi_ms7d25" + build_msi ddr4 "Z690-A DDR4 " + ;; + "ddr5" | "z690a_ddr5" | "ms7d25_ddr5") + BOARD="msi_ms7d25" + build_msi ddr5 "Z690-A DDR5 " + ;; + "z790p_ddr4" | "ms7e06_ddr4") + BOARD="msi_ms7e06" + build_msi ddr4 "Z790-P DDR4 " + ;; + "z790p_ddr5" | "ms7e06_ddr5") + BOARD="msi_ms7e06" + build_msi ddr5 "Z790-P DDR5 " + ;; + "vp66xx" | "VP66XX") + BOARD="vp66xx" + build_protectli_vault + ;; + "vp46xx" | "VP46XX") + BOARD="vp46xx" + build_protectli_vault + ;; + "vp32xx" | "VP32XX") + BOARD="vp32xx" + build_protectli_vault + ;; + "vp2410" | "VP2410") + BOARD="vp2410" + build_protectli_vault + ;; + "vp2420" | "VP2420") + BOARD="vp2420" + build_protectli_vault + ;; + "vp2430" | "VP2430") + BOARD="vp2430" + build_protectli_vault + ;; + "vp2440" | "VP2440") + BOARD="vp2440" + build_protectli_vault + ;; + "v1210" | "V1210" ) + build_v1x10 "v1210" + ;; + "v1211" | "V1211" ) + build_v1x10 "v1211" + ;; + "v1410" | "V1410" ) + build_v1x10 "v1410" + ;; + "v1610" | "V1610" ) + build_v1x10 "v1610" + ;; + "v540tnx" | "V540TNx" | "V540TNX" ) + BOARD="v540tnx" + build_novacustom "v540tnx" + ;; + "v560tnx" | "V560TNx" | "V560TNX" ) + BOARD="v560tnx" + build_novacustom "v560tnx" + ;; + "nv4x_adl" | "NV4x_ADL" | "NV4X_ADL" ) + BOARD="nv4x_adl" + build_novacustom "nv4x_adl" + ;; + "nv4x_tgl" | "NV4x_tgl" | "NV4X_TGL" ) + BOARD="nv4x_tgl" + build_novacustom "nv4x_tgl" + ;; + "ns5x_adl" | "NS5x_ADL" | "NS5X_ADL" ) + BOARD="ns5x_adl" + build_novacustom "ns5x_adl" + ;; + "ns5x_tgl" | "NS5x_TGL" | "NS5X_TGL" ) + BOARD="ns5x_tgl" + build_novacustom "ns5x_tgl" + ;; + "v560tu" | "V560TU" ) + BOARD="v560tu" + build_novacustom_v5x0tu "v560tu" + ;; + "nuc_box" | "nucbox" ) + BOARD="nuc_box" + build_novacustom "nuc_box" + ;; + "v540tu" | "V540TU" ) + BOARD="v540tu" + build_novacustom_v5x0tu "v540tu" + ;; + "apu2" | "APU2" ) + build_pcengines "apu2" + ;; + "apu3" | "APU3" ) + build_pcengines "apu3" + ;; + "apu4" | "APU4" ) + build_pcengines "apu4" + ;; + "apu6" | "APU6" ) + build_pcengines "apu6" + ;; + "optiplex_9010_uefi" | "optiplex_9010_sff_uefi") + BOARD="optiplex_9010" + build_optiplex_9010 "configs/config.dell_optiplex_9010_sff_uefi_txt" + ;; + "optiplex_9010_seabios" | "optiplex_9010_sff") + BOARD="optiplex_9010" + build_optiplex_9010 "configs/config.dell_optiplex_9010_sff_txt" + ;; + "qemu" | "QEMU" | "q35" | "Q35" | "x86_q35_uefi" ) + build_qemu + ;; + "qemu_full" | "QEMU_full" | "q35_full" | "Q35_full" | "x86_q35_uefi_all_menus" ) + build_qemu "_all_menus" + ;; + "odroid_h4" | "odroid_H4" | "ODROID_H4" ) + build_odroid_h4 "odroid_h4" + ;; + "odroid_h4_netcard" | "odroid_H4_netcard" | "ODROID_H4_NETCARD" ) + build_odroid_h4 "odroid_h4_netcard" + ;; + "asrock_spc741d8") + build_asrock_rack + ;; + *) + echo "Invalid command: \"$CMD\"" + usage + ;; +esac diff --git a/capsule.sh b/capsule.sh new file mode 100755 index 00000000000..89f30cedd65 --- /dev/null +++ b/capsule.sh @@ -0,0 +1,363 @@ +#!/bin/bash + +set -e + +edk_workspace=payloads/external/edk2/workspace +edk_basetools=${edk_workspace}/Dasharo/BaseTools +edk_tools=${edk_basetools}/BinWrappers/PosixLike +edk_scripts=${edk_basetools}/Scripts + +function die() { + echo error: "$@" 1>&2 + exit 1 +} + +function confirm() { + local msg=$1 + read -r -n1 -p "$msg [y/N] " + echo + if [ "$REPLY" != y ]; then + die "operation cancelled by the user" + fi +} + +function print_banner() { + local msg=$1 + + echo + echo ========== "${msg^^*}" ========== + echo +} + +function info() { + echo info: "$@" +} + +function print_usage() { + echo "Usage: $(basename "$0") subcommand [subcommand-args...]" + echo + echo 'Subcommands:' + echo ' box export standalone GenerateCapsule out of EDK2' + echo ' help print this message' + echo ' keygen use OpenSSL to auto-generate test keys suitable for signing' + echo ' positional argument: directory-path' + echo ' make build a capsule, options:' + echo ' -t root-certificate-file' + echo ' -o subroot-certificate-file' + echo ' -s signing-certificate-file' + echo ' -b (the flag adds battery check DXE into the capsule)' +} + +function help_subcommand() { + print_usage +} + +function keygen_subcommand() { + local dir=$1 + + if [ $# -ne 1 ]; then + echo "Usage: $(basename "$0") keygen keys-dir" + exit 1 + fi + + if [ -e "$dir" ]; then + confirm "OK to remove '$dir'?" + rm -r "$dir" + fi + + mkdir "$dir" + cd "$dir" + + # this is needed to make `openssl req` work non-interactively + cat > "openssl.cnf" << 'EOF' +.include /etc/ssl/openssl.cnf + +[ CA_default ] +dir = ./test-ca +certs = $dir/certs +crl_dir = $dir/crl +database = $dir/index.txt +new_certs_dir = $dir/newcerts +certificate = $dir/cacert.pem +serial = $dir/serial +crlnumber = $dir/crlnumber +crl = $dir/crl.pem +private_key = $dir/private/cakey.pem + +[ req_root ] +prompt = no +distinguished_name = req_root_dn +x509_extensions = v3_ca +string_mask = utf8only +[ req_root_dn ] +countryName = XX +stateOrProvinceName = Province +organizationName = Org +commonName = root + +[ req_sub ] +prompt = no +distinguished_name = req_sub_dn +x509_extensions = v3_ca +string_mask = utf8only +[ req_sub_dn ] +countryName = XX +stateOrProvinceName = Province +organizationName = Org +commonName = sub + +[ req_sign ] +prompt = no +distinguished_name = req_sign_dn +x509_extensions = v3_ca +string_mask = utf8only +[ req_sign_dn ] +countryName = XX +stateOrProvinceName = Province +organizationName = Org +commonName = sign +EOF + + print_banner 'Making root certificate' + + # make root certificate + openssl genrsa -out root.p8e 2048 + openssl req -config openssl.cnf -section req_root -new -x509 -days 3650 -key root.p8e -out root.pub.pem + + # dump certificate information like `openssl ca` does for completeness + openssl x509 -in root.pub.pem -text -certopt no_sigdump,no_pubkey -nocert + + # create a CA + mkdir -p test-ca/newcerts + touch test-ca/index.txt + echo 01 > test-ca/serial + + openssl x509 -in root.pub.pem -out root.cer -outform DER + python "${OLDPWD}/${edk_scripts}/BinToPcd.py" \ + -p gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr \ + -i root.cer -x -o CapsuleRootKey.inc + + print_banner 'Making subroot certificate' + + # make subroot certificate + openssl genrsa -out sub.p8e 2048 + openssl req -config openssl.cnf -section req_sub -new -key sub.p8e -out sub.csr + yes | openssl ca -config openssl.cnf -extensions v3_ca -in sub.csr -days 3650 -cert root.pub.pem -keyfile root.p8e -notext -out sub.pub.pem + + print_banner 'Making signing certificate' + + # make signing certificate + openssl genrsa -out sign.p8e 2048 + openssl req -config openssl.cnf -section req_sign -new -key sign.p8e -out sign.csr + yes | openssl ca -config openssl.cnf -in sign.csr -days 3650 -cert sub.pub.pem -keyfile sub.p8e -notext -out sign.crt + + # create binary PKCS12 (certificate + private key) from signing certificate + openssl pkcs12 -export -passout pass: -inkey sign.p8e -in sign.crt -out sign.pfx + # now convert binary PKCS12 into PEM PKCS12 with no password + openssl pkcs12 -in sign.pfx -passin pass: -nodes -out sign.p12 + + print_banner 'Usage examples' + + echo "Installing root certificate (before build):" + echo " cp $dir/CapsuleRootKey.inc ${edk_workspace}/Dasharo/DasharoPayloadPkg/" + echo + echo "Signing a capsule (after build):" + echo " $0 make -t $dir/root.pub.pem -o $dir/sub.pub.pem -s $dir/sign.p12" +} + +function check_cert() { + local name=$1 + local path=$2 + + if [ -z "$path" ]; then + die "$name certificate wasn't provided" + fi + + if [ ! -f "$path" ]; then + die "can't read $name certificate at '$path'" + fi +} + +function make_subcommand() { + if [ ! -f .config ]; then + die "no '.config' file in current directory" + fi + if [ ! -f build/coreboot.rom ]; then + die "no 'build/coreboot.rom'; the firmware wasn't built?" + fi + if [ ! build/coreboot.rom -nt .config ]; then + die "'build/coreboot.rom' is not newer than .config'; need a re-build?" + fi + if [ ! -x "${edk_tools}/GenerateCapsule" ]; then + die "'${edk_tools}/GenerateCapsule' can't be executed" + fi + + # import coreboot's config file replacing $(...) with ${...} + while read -r line; do + if ! eval "$line"; then + die "failed to source '.config'" + fi + done <<< "$(sed 's/\$(\([^)]\+\))/${\1}/g' .config)" + + if [ "$CONFIG_DRIVERS_EFI_UPDATE_CAPSULES" != y ]; then + die "current board configuration lacks support of update capsules" + fi + + # Option names match terminology of GenerateCapsule which conveniently start + # with different letters: + # * t - trusted + # * o - other + # * s - signer + local root_cert sub_cert sign_cert include_battery_check + while getopts "t:o:s:b" OPTION; do + case $OPTION in + t) root_cert="$OPTARG" ;; + o) sub_cert="$OPTARG" ;; + s) sign_cert="$OPTARG" ;; + b) include_battery_check=1 ;; + *) exit 1 ;; + esac + done + + check_cert root "$root_cert" + check_cert sub "$sub_cert" + check_cert sign "$sign_cert" + + local cap_file=${CONFIG_MAINBOARD_DIR//[\/-]/_} + if [[ ${CONFIG_MAINBOARD_PART_NUMBER} =~ DDR4 ]]; then + cap_file+=_ddr4 + fi + cap_file+=_${CONFIG_LOCALVERSION} + cap_file+=.cap + + if [ -e "$cap_file" ]; then + confirm "Overwrite already existing '$cap_file'?" + fi + + local build_type + if [ "$CONFIG_EDK2_RELEASE" = y ]; then + build_type=RELEASE + else + build_type=DEBUG + fi + + local json_file + json_file=$(mktemp --tmpdir --suffix -cap.json XXXXXXXX) + trap "$(printf 'rm -f %q' "$json_file")" EXIT + + cat > "$json_file" << EOF +{ + "EmbeddedDrivers": [ +EOF + + # Ensure the charger check driver module is first + if [ "$include_battery_check" = 1 ]; then + cat >> "$json_file" << EOF + { + "Driver": "${edk_workspace}/Build/DasharoPayloadPkgX64/${build_type}_COREBOOT/X64/CapsuleChargerCheckDxe.efi" + }, +EOF + fi + + cat >> "$json_file" << EOF + { + "Driver": "${edk_workspace}/Build/DasharoPayloadPkgX64/${build_type}_COREBOOT/X64/CapsuleSplashDxe.efi" + }, + { + "Driver": "${edk_workspace}/Build/DasharoPayloadPkgX64/${build_type}_COREBOOT/X64/FmpDxe.efi" + } + ], + "Payloads": [ + { + "Payload": "build/coreboot.rom", + "Guid": "${CONFIG_DRIVERS_EFI_MAIN_FW_GUID}", + "FwVersion": "${CONFIG_DRIVERS_EFI_MAIN_FW_VERSION}", + "LowestSupportedVersion": "${CONFIG_DRIVERS_EFI_MAIN_FW_LSV}", + + "OpenSslSignerPrivateCertFile": "${sign_cert}", + "OpenSslOtherPublicCertFile": "${sub_cert}", + "OpenSslTrustedPublicCertFile": "${root_cert}" + } + ] +} +EOF + + # Linux doesn't support InitiateReset flag, omitting it to rely on manual + # warm reset + if ! "${edk_tools}/GenerateCapsule" --encode \ + --capflag PersistAcrossReset \ + --json-file "$json_file" \ + --output "$cap_file"; then + die "GenerateCapsule failed" + fi + + echo "Created the capsule at '$cap_file'" +} + +function box_subcommand() { + local src=${edk_basetools}/Source/Python + local dst=gencap + + local keys=${src}/Pkcs7Sign + + if [ -e "$dst" ]; then + confirm "Overwrite already existing '$dst'?" + rm -r "${dst}" + fi + + info "using '${src}'" + info "constructing a standalone version in '${dst}'" + + mkdir -p "${dst}"/{Common,keys} + + cp "${src}/Capsule/GenerateCapsule.py" "${dst}" + cp -r "${src}/Common/Edk2" "${dst}/Common" + cp -r "${src}/Common/Uefi" "${dst}/Common" + + info "using keys from '${keys}'" + cp "$keys"/TestRoot.pub.pem "${dst}/keys/root.pub.pem" + cp "$keys"/TestSub.pub.pem "${dst}/keys/sub.pub.pem" + cp "$keys"/TestCert.pem "${dst}/keys/sign.crt" + + cat > "${dst}/GenerateCapsule" <<'EOF' +#!/usr/bin/env bash + +python=python +if command -v python3 >/dev/null; then + python=python3 +elif command -v python2 >/dev/null; then + python=python2 +fi + +dir=$(dirname "${BASH_SOURCE:-$0}") +exec "${python}" "${dir}/GenerateCapsule.py" "$@" +EOF + chmod +x "${dst}/GenerateCapsule" + + print_banner 'Help' + echo "Location of capsule signing keys:" + echo " ${dst}/keys/" + echo + echo "Usage examples:" + echo " ${dst}/GenerateCapsule --help" + echo " ${dst}/GenerateCapsule --output decoded --decode coreboot.cap" +} + +if [ $# -eq 0 ]; then + print_usage + exit 1 +fi + +subcommand=$1 +shift + +case "$subcommand" in + box|help|keygen|make) + "$subcommand"_subcommand "$@" ;; + + *) + echo "Unexpected subcommand: $subcommand" + echo + print_usage + exit 1 ;; +esac diff --git a/capsule_cabinet.sh b/capsule_cabinet.sh new file mode 100755 index 00000000000..a03851d2558 --- /dev/null +++ b/capsule_cabinet.sh @@ -0,0 +1,87 @@ +#!/bin/bash +# A script to generate cabinets for fwupd / LVFS + +set -e + +function die() { + echo error: "$@" 1>&2 + exit 1 +} + +if [ $# -ne 1 ]; then + die "Incorrect number of input parameters specified: $# (expected: 1)" +fi + +if [ -z $1 ]; then + die "No input capsule specified" +fi + +if [ ! -f $1 ]; then + die "File $1 not found" +fi + +if [ ! -f .config ]; then + die "No '.config' file in current directory" +fi + +# import coreboot's config file replacing $(...) with ${...} +while read -r line; do + if ! eval "$line"; then + die "failed to source '.config'" + fi +done <<< "$(sed 's/\$(\([^)]\+\))/${\1}/g' .config)" + +if [ "$CONFIG_DRIVERS_EFI_UPDATE_CAPSULES" != y ]; then + die "Current board configuration lacks support of update capsules" +fi + +capsule=$1 +date=$(stat -c %w $capsule | cut -d ' ' -f 1) +vendor=$(cat .config | grep -e "CONFIG_VENDOR_.*=y" | cut -d '=' -f 1 | cut -d '_' -f 3- | awk '{ print tolower($0) }') +version=$(echo $CONFIG_LOCALVERSION | tr -d 'v' | cut -d '-' -f 1) + +archive_dir=$(mktemp --tmpdir -d XXXXXXXX) + +cat > "${archive_dir}/firmware.metainfo.xml" << EOF + + + com.${vendor}.${CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME}.${CONFIG_MAINBOARD_VERSION}.system.firmware + ${CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME} + ${CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME} ${CONFIG_MAINBOARD_VERSION} system firmware + +

Dasharo ${CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME} ${CONFIG_MAINBOARD_VERSION} system firmware

+ + + ${CONFIG_DRIVERS_EFI_MAIN_FW_GUID} + + https://docs.dasharo.com/ + CC0-1.0 + LicenseRef-proprietary + + X-System + + + quad + dell-bios-msb + org.uefi.capsule + + + + + + + + +EOF + +cp $capsule $archive_dir/firmware.bin + +pushd $archive_dir &> /dev/null +fwupdtool build-cabinet $capsule.cab firmware.bin firmware.metainfo.xml +popd &> /dev/null + +cp $archive_dir/$capsule.cab ./ + +echo "File $capsule.cab created" + +rm -r $archive_dir diff --git a/configs/builder/config.asrock.spc741d8 b/configs/builder/config.asrock.spc741d8 new file mode 100644 index 00000000000..4b6a468ff06 --- /dev/null +++ b/configs/builder/config.asrock.spc741d8 @@ -0,0 +1,16 @@ +# This config is intended for ASRock Rack SPC741D8-2L2T boards based on Intel +# Sapphire Rapids Scalable Processor (SPR-SP) chipset. +# +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.asrock.spc741d8 + +CONFIG_VENDOR_ASROCK=y +CONFIG_BOARD_ASROCK_SPC741D8=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_IFD_BIN_PATH="site-local/eaglestream/descriptor.bin" +CONFIG_ME_BIN_PATH="site-local/eaglestream/me.bin" +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y diff --git a/configs/builder/config.intel.crb.ac b/configs/builder/config.intel.crb.ac index 73e2eea06f3..df898b0dc07 100644 --- a/configs/builder/config.intel.crb.ac +++ b/configs/builder/config.intel.crb.ac @@ -12,13 +12,7 @@ CONFIG_PAYLOAD_LINUX=y CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage" CONFIG_HAVE_ME_BIN=y CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y -CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y -CONFIG_ADD_FSP_BINARIES=y -CONFIG_FSP_T_FILE="site-local/archercity/Server_T.fd" -CONFIG_FSP_M_FILE="site-local/archercity/Server_M.fd" -CONFIG_FSP_S_FILE="site-local/archercity/Server_S.fd" CONFIG_IFD_BIN_PATH="site-local/archercity/descriptor.bin" CONFIG_ME_BIN_PATH="site-local/archercity/me.bin" -CONFIG_CPU_UCODE_BINARIES="site-local/archercity/mbf806f8.mcb" CONFIG_VALIDATE_INTEL_DESCRIPTOR=y CONFIG_NO_GFX_INIT=y diff --git a/configs/config.asrock_spc741d8 b/configs/config.asrock_spc741d8 new file mode 100644 index 00000000000..354c81ff415 --- /dev/null +++ b/configs/config.asrock_spc741d8 @@ -0,0 +1,61 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_ASROCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_BOARD_ASROCK_SPC741D8=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/asrock/spc741d8/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/asrock/spc741d8/me.bin" +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_TAG_OR_REV="22333c9e249641293ce4415e726354f396a0d8d3" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.dell_optiplex_9010_sff b/configs/config.dell_optiplex_9010_sff index b0ef91b09eb..b45182a67ad 100644 --- a/configs/config.dell_optiplex_9010_sff +++ b/configs/config.dell_optiplex_9010_sff @@ -1,10 +1,21 @@ -CONFIG_USE_OPTION_TABLE=y -CONFIG_USE_BLOBS=y +CONFIG_LOCALVERSION="v0.1.0-rc3" CONFIG_VENDOR_DELL=y -CONFIG_BOARD_DELL_OPTIPLEX_9010=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y -# CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_PCIEXP_CLK_PM=y CONFIG_SEABIOS_PS2_TIMEOUT=3000 -CONFIG_POST_DEVICE_LPC=y -CONFIG_HAVE_EM100_SUPPORT=y +CONFIG_PXE_ROM_ID="8086,1502" +CONFIG_BOARD_DELL_OPTIPLEX_9010=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TPM_MEASURED_BOOT=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_SEABIOS_USB_SIGATT_TIME=3000 +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_SEABIOS_DEBUG_LEVEL=0 +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" diff --git a/configs/config.dell_optiplex_9010_sff_txt b/configs/config.dell_optiplex_9010_sff_txt new file mode 100644 index 00000000000..b85a4db0657 --- /dev/null +++ b/configs/config.dell_optiplex_9010_sff_txt @@ -0,0 +1,25 @@ +CONFIG_LOCALVERSION="v0.1.0-rc3" +CONFIG_VENDOR_DELL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_PXE_ROM_ID="8086,1502" +CONFIG_BOARD_DELL_OPTIPLEX_9010=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_TPM_MEASURED_BOOT=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BDR_VERSION=4 +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_SEABIOS_USB_SIGATT_TIME=3000 +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_SEABIOS_DEBUG_LEVEL=0 +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_DASHARO=y diff --git a/configs/config.dell_optiplex_9010_sff_uefi b/configs/config.dell_optiplex_9010_sff_uefi new file mode 100644 index 00000000000..5a25cc742a3 --- /dev/null +++ b/configs/config.dell_optiplex_9010_sff_uefi @@ -0,0 +1,48 @@ +CONFIG_LOCALVERSION="v0.1.2-rc1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_DELL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_BOARD_DELL_OPTIPLEX_9010=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SD_MMC_TIMEOUT=1000 +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.dell_optiplex_9010_sff_uefi_txt b/configs/config.dell_optiplex_9010_sff_uefi_txt new file mode 100644 index 00000000000..83b14e0a748 --- /dev/null +++ b/configs/config.dell_optiplex_9010_sff_uefi_txt @@ -0,0 +1,51 @@ +CONFIG_LOCALVERSION="v0.1.2-rc1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_DELL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_BOARD_DELL_OPTIPLEX_9010=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BDR_VERSION=4 +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SD_MMC_TIMEOUT=1000 +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.emulation_qemu_x86_q35_uefi b/configs/config.emulation_qemu_x86_q35_uefi new file mode 100644 index 00000000000..0be46de9698 --- /dev/null +++ b/configs/config.emulation_qemu_x86_q35_uefi @@ -0,0 +1,43 @@ +CONFIG_LOCALVERSION="v0.2.1-rc1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_CPU_QEMU_X86_TSEG_SMM=y +CONFIG_UDK_202005_BINDING=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="20651b14-8653-4d9b-a75a-67fa76e0ada5" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00020101 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00020101 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_TPM1=y +CONFIG_TPM2=y +CONFIG_TPM_HASH_SHA256=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0017 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.emulation_qemu_x86_q35_uefi_all_menus b/configs/config.emulation_qemu_x86_q35_uefi_all_menus new file mode 100644 index 00000000000..a720d7970c4 --- /dev/null +++ b/configs/config.emulation_qemu_x86_q35_uefi_all_menus @@ -0,0 +1,54 @@ +CONFIG_LOCALVERSION="v0.2.1-rc1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_CPU_QEMU_X86_TSEG_SMM=y +CONFIG_UDK_202005_BINDING=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM1=y +CONFIG_TPM2=y +CONFIG_TPM_HASH_SHA256=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0017 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.hardkernel_odroid_h4 b/configs/config.hardkernel_odroid_h4 new file mode 100644 index 00000000000..da486c5dff0 --- /dev/null +++ b/configs/config.hardkernel_odroid_h4 @@ -0,0 +1,77 @@ +CONFIG_LOCALVERSION="v0.9.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_HARDKERNEL=y +CONFIG_VBOOT=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT=10 +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="cd18c3e8-b350-4fac-bc1a-36621db26999" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090180 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090180 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +# CONFIG_DRIVERS_MTK_WIFI is not set +CONFIG_TPM2=y +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_IBECC_OPTION=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y diff --git a/configs/config.hardkernel_odroid_h4_netcard b/configs/config.hardkernel_odroid_h4_netcard new file mode 100644 index 00000000000..8e856ccaf05 --- /dev/null +++ b/configs/config.hardkernel_odroid_h4_netcard @@ -0,0 +1,78 @@ +CONFIG_LOCALVERSION="v0.9.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_HARDKERNEL=y +CONFIG_VBOOT=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT=10 +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor_netcard.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_ODROID_H4_NETCARD_SUPPORT=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="99a22088-dea6-4cea-95cd-5381dcf23424" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090180 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090180 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +# CONFIG_DRIVERS_MTK_WIFI is not set +CONFIG_TPM2=y +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_IBECC_OPTION=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y diff --git a/configs/config.intel_minnowmax b/configs/config.intel_minnowmax new file mode 100644 index 00000000000..f06a87c19e4 --- /dev/null +++ b/configs/config.intel_minnowmax @@ -0,0 +1,44 @@ +CONFIG_VENDOR_INTEL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_VGA_BIOS is not set +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_IFD_BIN_PATH="IFWI_HEADER.bin" +CONFIG_ME_BIN_PATH="VLV_SEC_REGION.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_BOARD_INTEL_MINNOWMAX=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_HAVE_MRC=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="IntelBYTGopDriver.efi" +CONFIG_EDK2_DISABLE_TPM=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.msi_ms7d25_ddr4 b/configs/config.msi_ms7d25_ddr4 index fde405193c2..c41cf3952df 100644 --- a/configs/config.msi_ms7d25_ddr4 +++ b/configs/config.msi_ms7d25_ddr4 @@ -1,23 +1,75 @@ +CONFIG_LOCALVERSION="v1.1.5" CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y -CONFIG_PCIEXP_HOTPLUG=y -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_INCLUDE_HSPHY_IN_FMAP=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y CONFIG_DRIVERS_EFI_VARIABLE_STORE=y CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="0f3e8ba6-19d3-461b-bbbc-8b5689fe8097" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01010580 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01010580 CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y -CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y -CONFIG_DRIVERS_GENERIC_CBFS_UUID=y CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set CONFIG_POST_DEVICE_PCI_PCIE=y CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" -CONFIG_EDK2_TAG_OR_REV="origin/dasharo" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y -CONFIG_EDK2_SD_MMC_TIMEOUT=1000 +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.msi_ms7d25_ddr5 b/configs/config.msi_ms7d25_ddr5 index e26e99e8178..4e07f30ddfc 100644 --- a/configs/config.msi_ms7d25_ddr5 +++ b/configs/config.msi_ms7d25_ddr5 @@ -1,21 +1,74 @@ +CONFIG_LOCALVERSION="v1.1.5" +CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y -CONFIG_CBFS_SIZE=0x1000000 -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR5=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y -CONFIG_PCIEXP_HOTPLUG=y -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_INCLUDE_HSPHY_IN_FMAP=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="119059ec-1a5e-4844-b2e6-6f573b257570" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01010580 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01010580 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y -CONFIG_POST_DEVICE_PCI_PCIE=y -CONFIG_POST_IO_PORT=0x80 +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" -CONFIG_EDK2_TAG_OR_REV="origin/dasharo" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y -CONFIG_EDK2_SD_MMC_TIMEOUT=1000 -CONFIG_TPM2=y -CONFIG_TPM_MEASURED_BOOT=y -CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y -CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.msi_ms7e06_ddr4 b/configs/config.msi_ms7e06_ddr4 index a6080b93a9a..5a0f19f212e 100644 --- a/configs/config.msi_ms7e06_ddr4 +++ b/configs/config.msi_ms7e06_ddr4 @@ -1,11 +1,74 @@ +CONFIG_LOCALVERSION="v0.9.3" +CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VBOOT=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR4=y CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INCLUDE_HSPHY_IN_FMAP=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="91e6522e-25e1-4543-9b38-02e2aeafc9ed" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090380 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090380 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.msi_ms7e06_ddr5 b/configs/config.msi_ms7e06_ddr5 index f48435f159e..b376d0b8eda 100644 --- a/configs/config.msi_ms7e06_ddr5 +++ b/configs/config.msi_ms7e06_ddr5 @@ -1,11 +1,74 @@ +CONFIG_LOCALVERSION="v0.9.3" +CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VBOOT=y -CONFIG_BOARD_MSI_Z790_P_PRO_WIFI=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR5=y CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INCLUDE_HSPHY_IN_FMAP=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="58301b3d-5b6d-4562-9ec1-fbce40f15253" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090380 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090380 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.novacustom_ns5x_adl b/configs/config.novacustom_ns5x_adl new file mode 100644 index 00000000000..3919fb522c3 --- /dev/null +++ b/configs/config.novacustom_ns5x_adl @@ -0,0 +1,87 @@ +CONFIG_LOCALVERSION="v1.8.0-rc3" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_VERSION="v2.1" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/ns5x_adl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/ns5x_adl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="742d22fb-1043-4994-9154-7a30679de5f0" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01080003 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01080002 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/ns5x_adl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdS3SupportExperimental=TRUE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_ns5x_tgl b/configs/config.novacustom_ns5x_tgl new file mode 100644 index 00000000000..7c99eea8906 --- /dev/null +++ b/configs/config.novacustom_ns5x_tgl @@ -0,0 +1,88 @@ +CONFIG_LOCALVERSION="v1.6.0-rc2" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/clevo/tgl-u/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/ns5x_tgl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/ns5x_tgl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_NS5X_TGLU=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INTEL_TME=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="2c033395-4de7-4de5-b610-eafa2e0b6300" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01060002 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01060002 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/ns5x_tgl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdS3SupportExperimental=TRUE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_nuc_box b/configs/config.novacustom_nuc_box new file mode 100644 index 00000000000..54100861e86 --- /dev/null +++ b/configs/config.novacustom_nuc_box @@ -0,0 +1,63 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_VENDOR="NovaCustom" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_VBOOT_SLOTS_RW_A=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nuc_box/ifd.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nuc_box/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_NUC_BOX=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_VALIDATE_INTEL_DESCRIPTOR=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="6f3f1f8c-f0a1-42d4-adee-14b476f9e066" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090080 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090080 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_nv4x_adl b/configs/config.novacustom_nv4x_adl new file mode 100644 index 00000000000..a16a491ad8d --- /dev/null +++ b/configs/config.novacustom_nv4x_adl @@ -0,0 +1,87 @@ +CONFIG_LOCALVERSION="v1.8.0-rc3" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_VERSION="v2.1" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_adl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_adl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_NV4X_ADLP=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="b79b7279-79a4-47cf-ab2f-8636c541f2d0" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01080003 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01080002 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/nv4x_adl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_nv4x_tgl b/configs/config.novacustom_nv4x_tgl new file mode 100644 index 00000000000..96fa86e1bb4 --- /dev/null +++ b/configs/config.novacustom_nv4x_tgl @@ -0,0 +1,89 @@ +CONFIG_LOCALVERSION="v1.6.0-rc2" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/clevo/tgl-u/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_NV4X_TGLU=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INTEL_TME=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="ffe49861-809c-4aa4-8d3e-2b1640b3c96c" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01060002 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01060002 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdS3SupportExperimental=TRUE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_DGPU_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_v540tnx b/configs/config.novacustom_v540tnx new file mode 100644 index 00000000000..f65b7f83e3d --- /dev/null +++ b/configs/config.novacustom_v540tnx @@ -0,0 +1,96 @@ +CONFIG_LOCALVERSION="v1.0.0-rc7" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_PART_NUMBER="V54x_6x_TU" +CONFIG_FMDFILE="src/mainboard/novacustom/mtl-h/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +# CONFIG_CONSOLE_POST is not set +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_VBOOT_SLOTS_RW_A=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tnx/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tnx/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_VBOOT_SLOTS_RW_AB is not set +CONFIG_BOARD_NOVACUSTOM_V540TNX=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_SUBSYSTEM_DEVICE_ID=0xa741 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="ec380f40-ad1b-40e9-b5a2-99ab56be66d3" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01000007 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01000007 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/v5x0tu/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution=1920 --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution=1080" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_DGPU_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_v540tu b/configs/config.novacustom_v540tu new file mode 100644 index 00000000000..4388aa1f575 --- /dev/null +++ b/configs/config.novacustom_v540tu @@ -0,0 +1,97 @@ +CONFIG_LOCALVERSION="v1.0.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/novacustom/mtl-h/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +# CONFIG_CONSOLE_POST is not set +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_VBOOT_SLOTS_RW_A=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/me.bin" +CONFIG_GBE_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/gbe.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_VBOOT_SLOTS_RW_AB is not set +CONFIG_BOARD_NOVACUSTOM_V540TU=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_GBE_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="f4deb4f3-f673-48fe-a481-627357b00b6a" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01000080 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01000080 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_BUILDING_WITH_DEBUG_FSP=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/v5x0tu/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution=1920 --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution=1080" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_LAN_ROM_DRIVER="3rdparty/blobs/mainboard/novacustom/mtl-h/LanRom.efi" +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_v560tnx b/configs/config.novacustom_v560tnx new file mode 100644 index 00000000000..ef758fe1df8 --- /dev/null +++ b/configs/config.novacustom_v560tnx @@ -0,0 +1,96 @@ +CONFIG_LOCALVERSION="v1.0.0-rc7" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_PART_NUMBER="V54x_6x_TU" +CONFIG_FMDFILE="src/mainboard/novacustom/mtl-h/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +# CONFIG_CONSOLE_POST is not set +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_VBOOT_SLOTS_RW_A=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tnx/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tnx/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_VBOOT_SLOTS_RW_AB is not set +CONFIG_BOARD_NOVACUSTOM_V560TNX=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_SUBSYSTEM_DEVICE_ID=0xa741 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="d5f421ef-8c11-4f1f-903d-49acf69530a6" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01000007 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01000007 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/v5x0tu/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution=1920 --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution=1080" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_DGPU_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_v560tu b/configs/config.novacustom_v560tu new file mode 100644 index 00000000000..48286f50237 --- /dev/null +++ b/configs/config.novacustom_v560tu @@ -0,0 +1,97 @@ +CONFIG_LOCALVERSION="v1.0.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/novacustom/mtl-h/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +# CONFIG_CONSOLE_POST is not set +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_VBOOT_SLOTS_RW_A=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/me.bin" +CONFIG_GBE_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/gbe.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_VBOOT_SLOTS_RW_AB is not set +CONFIG_BOARD_NOVACUSTOM_V560TU=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_GBE_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="4d7c36d7-a987-4c54-b49c-ea557c75e1ee" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01000080 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01000080 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_BUILDING_WITH_DEBUG_FSP=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_INTEL_CBNT_SUPPORT=y +CONFIG_INTEL_CBNT_LOGGING=y +# CONFIG_INTEL_CBNT_GENERATE_KM is not set +# CONFIG_INTEL_CBNT_GENERATE_BPM is not set +CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/km_sample.bin" +CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY="3rdparty/dasharo-blobs/cbnt/bpm_sample.bin" +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_FTDI_USB_UART_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/v5x0tu/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution=1920 --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution=1080" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_LAN_ROM_DRIVER="3rdparty/blobs/mainboard/novacustom/mtl-h/LanRom.efi" +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1 index a3e34b8df04..7ca69636a16 100644 --- a/configs/config.pcengines_apu1 +++ b/configs/config.pcengines_apu1 @@ -6,5 +6,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="10ec,8168" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 index fe0a9d7ba43..8e2d0548db9 100644 --- a/configs/config.pcengines_apu2 +++ b/configs/config.pcengines_apu2 @@ -8,5 +8,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,157b" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 index bf377158dfe..166a1f31e31 100644 --- a/configs/config.pcengines_apu3 +++ b/configs/config.pcengines_apu3 @@ -8,5 +8,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,1539" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 index 17db794bcf9..8085a046859 100644 --- a/configs/config.pcengines_apu4 +++ b/configs/config.pcengines_apu4 @@ -8,5 +8,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,1539" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 index b004e89c910..9e31e65e063 100644 --- a/configs/config.pcengines_apu5 +++ b/configs/config.pcengines_apu5 @@ -8,5 +8,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,1539" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6 new file mode 100644 index 00000000000..e1ae2a14323 --- /dev/null +++ b/configs/config.pcengines_apu6 @@ -0,0 +1,40 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PCENGINES_APU6=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.pcengines_uefi_apu2 b/configs/config.pcengines_uefi_apu2 new file mode 100644 index 00000000000..d4545304c40 --- /dev/null +++ b/configs/config.pcengines_uefi_apu2 @@ -0,0 +1,49 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_VBOOT=y +CONFIG_PXE_ROM_ID="8086,157b" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CHIP=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SPI_LOCK_PIN=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0014 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.pcengines_uefi_apu3 b/configs/config.pcengines_uefi_apu3 new file mode 100644 index 00000000000..028969c4461 --- /dev/null +++ b/configs/config.pcengines_uefi_apu3 @@ -0,0 +1,50 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_VBOOT=y +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PCENGINES_APU3=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CHIP=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SPI_LOCK_PIN=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0014 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.pcengines_uefi_apu4 b/configs/config.pcengines_uefi_apu4 new file mode 100644 index 00000000000..4726ebca772 --- /dev/null +++ b/configs/config.pcengines_uefi_apu4 @@ -0,0 +1,50 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_VBOOT=y +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PCENGINES_APU4=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CHIP=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SPI_LOCK_PIN=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0014 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.pcengines_uefi_apu6 b/configs/config.pcengines_uefi_apu6 new file mode 100644 index 00000000000..48d7cfd53f7 --- /dev/null +++ b/configs/config.pcengines_uefi_apu6 @@ -0,0 +1,50 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_VBOOT=y +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PCENGINES_APU6=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CHIP=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SPI_LOCK_PIN=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0014 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_cml_vp46xx b/configs/config.protectli_cml_vp46xx deleted file mode 100644 index 11642325dbb..00000000000 --- a/configs/config.protectli_cml_vp46xx +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_VENDOR_PROTECTLI=y -CONFIG_BOARD_PROTECTLI_VP46XX=y -CONFIG_TPM_MEASURED_BOOT=y -CONFIG_SMMSTORE_SIZE=0x40000 -CONFIG_TPM2=y -CONFIG_POST_IO_PORT=0x80 -CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y -CONFIG_EDK2_BOOT_TIMEOUT=6 -CONFIG_EDK2_FOLLOW_BGRT_SPEC=y -# CONFIG_EDK2_FULL_SCREEN_SETUP is not set -CONFIG_EDK2_SD_MMC_TIMEOUT=10 -CONFIG_EDK2_SERIAL_SUPPORT=y diff --git a/configs/config.protectli_vault_jsl_v1210 b/configs/config.protectli_vault_jsl_v1210 new file mode 100644 index 00000000000..fc938bc79c3 --- /dev/null +++ b/configs/config.protectli_vault_jsl_v1210 @@ -0,0 +1,53 @@ +CONFIG_LOCALVERSION="v0.9.4-rc4" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/FSP.fd" +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1210/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1210/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_V1210=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/Include" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vault_jsl_v1211 b/configs/config.protectli_vault_jsl_v1211 new file mode 100644 index 00000000000..bf2e980f19a --- /dev/null +++ b/configs/config.protectli_vault_jsl_v1211 @@ -0,0 +1,53 @@ +CONFIG_LOCALVERSION="v0.9.4-rc4" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/FSP.fd" +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1210/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1210/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_V1211=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/Include" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vault_jsl_v1410 b/configs/config.protectli_vault_jsl_v1410 new file mode 100644 index 00000000000..50211473f0a --- /dev/null +++ b/configs/config.protectli_vault_jsl_v1410 @@ -0,0 +1,53 @@ +CONFIG_LOCALVERSION="v0.9.4-rc4" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/FSP.fd" +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1410/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1410/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_V1410=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/Include" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vault_jsl_v1610 b/configs/config.protectli_vault_jsl_v1610 new file mode 100644 index 00000000000..09b9b2bbfbd --- /dev/null +++ b/configs/config.protectli_vault_jsl_v1610 @@ -0,0 +1,53 @@ +CONFIG_LOCALVERSION="v0.9.4-rc4" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/FSP.fd" +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1610/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1610/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_V1610=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/Include" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp2410 b/configs/config.protectli_vp2410 new file mode 100644 index 00000000000..5f76b660af6 --- /dev/null +++ b/configs/config.protectli_vp2410 @@ -0,0 +1,62 @@ +CONFIG_LOCALVERSION="v1.1.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/GeminilakeFspBinPkg/Fsp.fd" +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_IFWI_FILE_NAME="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_VP2410=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/GeminilakeFspBinPkg/Include" +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_POST_DEVICE_LPC=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI=y diff --git a/configs/config.protectli_vp2420 b/configs/config.protectli_vp2420 index 899a9560d60..a173baecd08 100644 --- a/configs/config.protectli_vp2420 +++ b/configs/config.protectli_vp2420 @@ -1,13 +1,64 @@ +CONFIG_LOCALVERSION="v1.2.1-rc8" CONFIG_VENDOR_PROTECTLI=y -CONFIG_CBFS_SIZE=0x900000 CONFIG_ONBOARD_VGA_IS_PRIMARY=y -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_VBOOT=y +CONFIG_DISABLE_HECI1_AT_PRE_BOOT=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y CONFIG_BOARD_PROTECTLI_VP2420=y -CONFIG_SMMSTORE_SIZE=0x40000 +CONFIG_SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_INTEL_ME_DISABLED_HECI=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_POST_DEVICE_LPC=y CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y -CONFIG_EDK2_SD_MMC_TIMEOUT=10 +# CONFIG_EDK2_PS2_SUPPORT is not set CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp2430 b/configs/config.protectli_vp2430 new file mode 100644 index 00000000000..532c80ccb45 --- /dev/null +++ b/configs/config.protectli_vp2430 @@ -0,0 +1,61 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp2430/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp2430/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_VP2430=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_INTEL_ME_DISABLED_HECI=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable=FALSE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp2440 b/configs/config.protectli_vp2440 new file mode 100644 index 00000000000..ddbe286c347 --- /dev/null +++ b/configs/config.protectli_vp2440 @@ -0,0 +1,61 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp2440/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp2440/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_VP2440=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_INTEL_ME_DISABLED_HECI=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable=FALSE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp32xx b/configs/config.protectli_vp32xx new file mode 100644 index 00000000000..919a479e0d7 --- /dev/null +++ b/configs/config.protectli_vp32xx @@ -0,0 +1,61 @@ +CONFIG_LOCALVERSION="v0.9.0-rc10" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp32xx/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp32xx/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_INTEL_ME_DISABLED_HECI=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_FAN_OFF_CURVE_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp46xx b/configs/config.protectli_vp46xx new file mode 100644 index 00000000000..bb597750e2a --- /dev/null +++ b/configs/config.protectli_vp46xx @@ -0,0 +1,64 @@ +CONFIG_LOCALVERSION="v1.2.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_VP46XX=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_INTEL_ME_DISABLED_HECI=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_RUN_FSP_GOP=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_FULL_SCREEN_SETUP is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_OC_WDT_SHOW=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp46xx_txt b/configs/config.protectli_vp46xx_txt new file mode 100644 index 00000000000..eec510757bd --- /dev/null +++ b/configs/config.protectli_vp46xx_txt @@ -0,0 +1,59 @@ +CONFIG_LOCALVERSION="v1.2.0-rc2" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_VP46XX=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_RUN_FSP_GOP=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/biosac.bin" +CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/sinitac.bin" +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp46xx_txt_seabios b/configs/config.protectli_vp46xx_txt_seabios new file mode 100644 index 00000000000..8f34c77aba5 --- /dev/null +++ b/configs/config.protectli_vp46xx_txt_seabios @@ -0,0 +1,36 @@ +CONFIG_LOCALVERSION="v0.9.0-rc1" +CONFIG_VENDOR_PROTECTLI=y +CONFIG_FMDFILE="" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PXE_ROM_ID="8086,15f3" +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_VP46XX=y +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_RUN_FSP_GOP=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/biosac.bin" +CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/sinitac.bin" +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_SEABIOS_USB_SIGATT_TIME=500 +CONFIG_SEABIOS_DEBUG_LEVEL=0 +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y diff --git a/configs/config.protectli_vp66xx b/configs/config.protectli_vp66xx new file mode 100644 index 00000000000..f94e23241c2 --- /dev/null +++ b/configs/config.protectli_vp66xx @@ -0,0 +1,77 @@ +CONFIG_LOCALVERSION="v0.9.3-rc1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_VBOOT=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_BOARD_PROTECTLI_VP66XX=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/black_background.bmp" +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_IFDTOOL_DISABLE_ME=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_INTEL_ME_DISABLED_HAP=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="dbe538fe-d0fa-4a33-aa36-1d32945e4154" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090301 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090300 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_POST_DEVICE_LPC=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="1002a59639f111a2f8178b77d1f5fde0ea8d976f" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_DASHARO=y +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_FAN_OFF_CURVE_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +# CONFIG_EDK2_GRAPHICAL_CAPSULE_PROGRESS is not set +# CONFIG_EDK2_FUM_AUTO_IPXE_BOOT is not set diff --git a/payloads/Kconfig b/payloads/Kconfig index 49486246c6b..f1aed68ae71 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -57,6 +57,14 @@ endchoice source "payloads/external/*/Kconfig" +config DASHARO + bool "Enable Dasharo specific payload options" + default n + +menu "Dasharo specific payload options" +source "payloads/external/*/Kconfig.dasharo" +endmenu + config PAYLOAD_FILE string "Payload path and filename" depends on PAYLOAD_ELF || PAYLOAD_FIT || PAYLOAD_FLAT_BINARY diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 299f1eee0b9..b3365ac0561 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -121,6 +121,15 @@ $(call add_intermediate, seabios_sercon, $(CBFSTOOL)) $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port endif +ifneq ($(CONFIG_SEABIOS_USB_SIGATT_TIME),) +ifneq ($(CONFIG_SEABIOS_USB_SIGATT_TIME),0) +$(call add_intermediate, seabios_usb_sigatt_time, $(CBFSTOOL)) + @printf " SeaBIOS Add sercon-port file\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/usb-time-sigatt 2>/dev/null) + $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_USB_SIGATT_TIME) -n etc/usb-time-sigatt +endif +endif + ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) $(call add_intermediate, seabios_thread_optionroms, $(CBFSTOOL)) @printf " SeaBIOS Thread optionroms\n" @@ -156,8 +165,12 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D # edk2 -$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) - $(MAKE) -C payloads/external/edk2 UefiPayloadPkg \ +ifeq ($(CONFIG_EDK2_ENABLE_IPXE),y) +IPXE_EFI := payloads/external/iPXE/ipxe/ipxe.rom +endif + +$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI) + $(MAKE) -C payloads/external/edk2 DasharoPayloadPkg \ HOSTCC="$(HOSTCC)" \ CC="$(HOSTCC)" \ CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \ @@ -206,7 +219,84 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) OBJCOPY_x86_64=$(OBJCOPY_x86_64) \ OBJCOPY_arm=$(OBJCOPY_arm) \ OBJCOPY_arm64=$(OBJCOPY_arm64) \ - MFLAGS= MAKEFLAGS= + MFLAGS= MAKEFLAGS= \ + CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \ + CONFIG_EDK2_BATTERY_CONFIG_OPTION=$(CONFIG_EDK2_BATTERY_CONFIG_OPTION) \ + CONFIG_EDK2_BOOT_MENU_KEY=$(CONFIG_EDK2_BOOT_MENU_KEY) \ + CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=$(CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS) \ + CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=$(CONFIG_EDK2_DASHARO_CHIPSET_CONFIG) \ + CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=$(CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS) \ + CONFIG_EDK2_DASHARO_MEMORY_CONFIG=$(CONFIG_EDK2_DASHARO_MEMORY_CONFIG) \ + CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=$(CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE) \ + CONFIG_EDK2_DASHARO_NETWORK_CONFIG=$(CONFIG_EDK2_DASHARO_NETWORK_CONFIG) \ + CONFIG_EDK2_DASHARO_OC_WDT_ENABLE=$(CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE) \ + CONFIG_EDK2_DASHARO_OC_WDT_TIMEOUT=$(CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS) \ + CONFIG_EDK2_DASHARO_PCI_CONFIG=$(CONFIG_EDK2_DASHARO_PCI_CONFIG) \ + CONFIG_EDK2_DASHARO_POWER_CONFIG=$(CONFIG_EDK2_DASHARO_POWER_CONFIG) \ + CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=$(CONFIG_EDK2_DASHARO_SECURITY_OPTIONS) \ + CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=$(CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE) \ + CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=$(CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE) \ + CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=$(CONFIG_EDK2_DASHARO_SYSTEM_FEATURES) \ + CONFIG_EDK2_DASHARO_USB_CONFIG=$(CONFIG_EDK2_DASHARO_USB_CONFIG) \ + CONFIG_EDK2_DISABLE_MTRR_PROGRAMMING=$(CONFIG_EDK2_DISABLE_MTRR_PROGRAMMING) \ + CONFIG_EDK2_DISABLE_OPTION_ROMS=$(CONFIG_EDK2_DISABLE_OPTION_ROMS) \ + CONFIG_EDK2_ENABLE_BATTERY_CHECK=$(CONFIG_EDK2_ENABLE_BATTERY_CHECK) \ + CONFIG_EDK2_ENABLE_BIOS_LOCK=$(CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO) \ + CONFIG_EDK2_ENABLE_FUM=$(CONFIG_DASHARO_FIRMWARE_UPDATE_MODE) \ + CONFIG_EDK2_ENABLE_SMM_BWP=$(CONFIG_BOOTMEDIA_SMM_BWP) \ + CONFIG_EDK2_FAN_CURVE_OPTION=$(CONFIG_EDK2_FAN_CURVE_OPTION) \ + CONFIG_EDK2_FAN_OFF_CURVE_OPTION=$(CONFIG_EDK2_FAN_OFF_CURVE_OPTION) \ + CONFIG_EDK2_HAVE_2ND_UART=$(CONFIG_EDK2_HAVE_2ND_UART) \ + CONFIG_EDK2_IPXE=$(CONFIG_EDK2_ENABLE_IPXE) \ + CONFIG_EDK2_IPXE_OPTION_NAME=$(CONFIG_EDK2_IPXE_OPTION_NAME) \ + CONFIG_EDK2_LAN_ROM_DRIVER=$(CONFIG_EDK2_LAN_ROM_DRIVER) \ + CONFIG_EDK2_OPAL_PASSWORD=$(CONFIG_EDK2_OPAL_PASSWORD) \ + CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=$(CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE) \ + CONFIG_EDK2_PRINT_SOL_STRINGS=$(CONFIG_EDK2_PRINT_SOL_STRINGS) \ + CONFIG_EDK2_RAM_DISK_ENABLE=$(CONFIG_EDK2_RAM_DISK_ENABLE) \ + CONFIG_EDK2_S3_SLEEP_DEFAULT=$(CONFIG_DASHARO_PREFER_S3_SLEEP) \ + CONFIG_EDK2_SATA_PASSWORD=$(CONFIG_EDK2_SATA_PASSWORD) \ + CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE=$(CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE) \ + CONFIG_EDK2_SERIAL_ON_SUPERIO=$(CONFIG_DRIVERS_UART_8250IO) \ + CONFIG_EDK2_SETUP_MENU_KEY=$(CONFIG_EDK2_SETUP_MENU_KEY) \ + CONFIG_EDK2_SETUP_PASSWORD=$(CONFIG_EDK2_SETUP_PASSWORD) \ + CONFIG_EDK2_SHOW_CAMERA_OPTION=$(CONFIG_EDK2_SHOW_CAMERA_OPTION) \ + CONFIG_EDK2_SHOW_WIFI_BT_OPTION=$(CONFIG_EDK2_SHOW_WIFI_BT_OPTION) \ + CONFIG_EDK2_SKIP_PS2_DETECT=$(CONFIG_EDK2_SKIP_PS2_DETECT) \ + CONFIG_EDK2_SLEEP_TYPE_OPTION=$(CONFIG_EDK2_SLEEP_TYPE_OPTION) \ + CONFIG_EDK2_SYSTEM76_EC_LOGGING=$(CONFIG_EDK2_SYSTEM76_EC_LOGGING) \ + CONFIG_EDK2_VERBOSE_BUILD=$(CONFIG_EDK2_VERBOSE_BUILD) \ + CONFIG_HAVE_INTEL_ME_HAP=$(CONFIG_HAVE_INTEL_ME_HAP) \ + CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=$(CONFIG_HAVE_POWER_STATE_AFTER_FAILURE) \ + CONFIG_INTEL_ME_DEFAULT_STATE=$(CONFIG_INTEL_ME_DEFAULT_STATE) \ + CONFIG_IOMMU_ENABLE=$(CONFIG_ENABLE_EARLY_DMA_PROTECTION) \ + CONFIG_MAINBOARD_POWER_FAILURE_STATE=$(CONFIG_MAINBOARD_POWER_FAILURE_STATE) \ + CONFIG_VENDOR_PCENGINES=$(CONFIG_VENDOR_PCENGINES) \ + CONFIG_EDK2_DASHARO_OC_WDT_SHOW=$(CONFIG_EDK2_DASHARO_OC_WDT_SHOW) \ + CONFIG_EDK2_DASHARO_CPU_CONFIG=$(CONFIG_EDK2_DASHARO_CPU_CONFIG) \ + CONFIG_EDK2_CORE_DISABLE_OPTION=$(CONFIG_EDK2_CORE_DISABLE_OPTION) \ + CONFIG_EDK2_HYPERTHREADING_OPTION=$(CONFIG_EDK2_HYPERTHREADING_OPTION) \ + CONFIG_EDK2_HYPERTHREADING_DEFAULT_STATE=$(CONFIG_FSP_HYPERTHREADING) \ + CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=$(CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION) \ + CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT=$(CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT) \ + CONFIG_CPU_MAX_TEMPERATURE=$(CONFIG_CPU_MAX_TEMPERATURE) \ + CONFIG_EDK2_USE_LAPTOP_LID_LIB=$(CONFIG_EDK2_USE_LAPTOP_LID_LIB) \ + CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI=$(CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI) \ + CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES) \ + CONFIG_DRIVERS_EFI_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID) \ + CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=$(CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE) \ + CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=$(CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE) \ + CONFIG_EDK2_USB_PORT_POWER_OPTION=$(CONFIG_EDK2_USB_PORT_POWER_OPTION) \ + CONFIG_EDK2_DGPU_POWER_OPTION=$(CONFIG_EDK2_DGPU_POWER_OPTION) \ + CONFIG_DGPU_ONLY_AVAILABLE=$(CONFIG_DGPU_ONLY_AVAILABLE) \ + CONFIG_EDK2_FTDI_USB_UART_SUPPORT=$(CONFIG_EDK2_FTDI_USB_UART_SUPPORT) \ + CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS=$(CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS) \ + CONFIG_QEMU_PLATFORM=$(CONFIG_CPU_QEMU_X86) \ + CONFIG_EDK2_GRAPHICAL_CAPSULE_PROGRESS=$(CONFIG_EDK2_GRAPHICAL_CAPSULE_PROGRESS) \ + CONFIG_EDK2_FUM_AUTO_IPXE_BOOT=$(CONFIG_EDK2_FUM_AUTO_IPXE_BOOT) \ + CONFIG_EDK2_DASHARO_IBECC_OPTION=$(CONFIG_EDK2_DASHARO_IBECC_OPTION) \ + CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION=$(CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION) + $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG) $(MAKE) -C payloads/external/edk2 UniversalPayload \ @@ -364,13 +454,18 @@ else IPXE_SERIAL_CONSOLE = n endif +ifneq ($(CONFIG_EDK2_ENABLE_IPXE),y) cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += pci$(CONFIG_PXE_ROM_ID).rom pci$(CONFIG_PXE_ROM_ID).rom-file := $(PXE_ROM_FILE) pci$(CONFIG_PXE_ROM_ID).rom-type := raw +IPXE_CROSS_COMPILE:="$(CROSS_COMPILE_$(ARCH-ramstage-y))" +else +IPXE_CROSS_COMPILE:=$(CROSS_COMPILE_x86_64) +endif payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT) $(MAKE) -C payloads/external/iPXE all \ - CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \ + CROSS_COMPILE=$(IPXE_CROSS_COMPILE) \ PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \ CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \ CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \ @@ -381,7 +476,10 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT) CONFIG_HAS_SCRIPT=$(CONFIG_IPXE_ADD_SCRIPT) \ CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \ CONFIG_IPXE_HAS_HTTPS=$(CONFIG_IPXE_HAS_HTTPS) \ - CONFIG_IPXE_TRUST_CMD=$(CONFIG_IPXE_TRUST_CMD) + CONFIG_IPXE_TRUST_CMD=$(CONFIG_IPXE_TRUST_CMD) \ + CONFIG_IPXE_CUSTOM_BUILD_ID=$(CONFIG_IPXE_CUSTOM_BUILD_ID) \ + CFLAGS_x86_64="$(CFLAGS_x86_64)" \ + CONFIG_IPXE_BUILD_EFI=$(CONFIG_EDK2_ENABLE_IPXE) # LinuxBoot LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86) = x86_32 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index b12af46a14a..5131fe3f121 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -52,6 +52,20 @@ config SEABIOS_PS2_TIMEOUT after powering on. This specifies how long SeaBIOS will wait for the keyboard controller to become ready before giving up. +config SEABIOS_USB_SIGATT_TIME + prompt "USB device attachment timeout (milliseconds)" + default 0 + int + help + The USB2 specification requires devices to signal that they are + attached within 100ms of the USB port being powered on. Some USB + devices are known to require more time. Prior to receiving an + attachment signal there is no way to know if a USB port is empty or + if it has a device attached. One may specify an amount of time here + (in milliseconds, default 100) to wait for a USB device attachment + signal. Increasing this value will also increase the overall machine + bootup time. + config SEABIOS_THREAD_OPTIONROMS prompt "Hardware init during option ROM execution" default n diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 291da7a1f6d..e481e1dc152 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -77,7 +77,7 @@ endchoice config EDK2_REPOSITORY string "URL to git repository for edk2" default "https://github.com/starlabsltd/edk2" if EDK2_UNIVERSAL_PAYLOAD - default "https://github.com/mrchromebox/edk2" if EDK2_REPO_MRCHROMEBOX + default "https://github.com/mrchromebox/edk2" if EDK2_REPO_MRCHROMEBOX && !DASHARO default "https://github.com/tianocore/edk2" if EDK2_REPO_OFFICIAL default "" if EDK2_REPO_CUSTOM help @@ -86,7 +86,7 @@ config EDK2_REPOSITORY config EDK2_TAG_OR_REV string "Insert a commit's SHA-1 or a branch name" - default "origin/uefipayload_2408" if EDK2_REPO_MRCHROMEBOX + default "origin/uefipayload_2408" if EDK2_REPO_MRCHROMEBOX && !DASHARO default "origin/universalpayload" if EDK2_UNIVERSAL_PAYLOAD default "origin/master" if EDK2_REPO_OFFICIAL default "" if EDK2_REPO_CUSTOM @@ -229,7 +229,7 @@ config EDK2_FULL_SCREEN_SETUP config EDK2_HAVE_EFI_SHELL bool "Include EFI Shell" - default y + default n help Include the EFI shell Binary @@ -261,6 +261,13 @@ config EDK2_SERIAL_SUPPORT Enable serial port output in edk2. Serial output limits the performance of edk2's FrontPage. +config EDK2_FTDI_USB_UART_SUPPORT + bool "Support FTDI USB-UART converters" + default n + help + Add support for using an FTDI USB-UART converter as a serial console redirection + option. Useful for platforms without an easily accessible serial port. + config EDK2_SECURE_BOOT_SUPPORT bool "Enable UEFI Secure Boot support" depends on EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2 @@ -283,6 +290,14 @@ config EDK2_GOP_FILE help The name of the GOP driver file passed to edk2. +config EDK2_USE_LAPTOP_LID_LIB + bool "Use platform-specific GOP policy library" + depends on EDK2_GOP_DRIVER + default n + help + Select this option to have edk2 use a platform-specific library to get lid state. + If not selected, the lid is always assumed to be open. + config EDK2_DISABLE_TPM bool "Disable TPM support in edk2" default y if EDK2_REPO_MRCHROMEBOX && TPM_GOOGLE_CR50 && SOC_AMD_COMMON diff --git a/payloads/external/edk2/Kconfig.dasharo b/payloads/external/edk2/Kconfig.dasharo new file mode 100644 index 00000000000..2b6212240a0 --- /dev/null +++ b/payloads/external/edk2/Kconfig.dasharo @@ -0,0 +1,441 @@ +if PAYLOAD_EDK2 && DASHARO + +config EDK2_REPOSITORY + default "https://github.com/Dasharo/edk2" + +config EDK2_TAG_OR_REV + default "3afc86b599c663c641d9e8d94be9d47cee675c5b" + +config EDK2_SYSTEM76_EC_LOGGING + bool "Enable edk2 logging to System76 EC" + default n + depends on EC_SYSTEM76_EC || EC_DASHARO_EC + help + Select this option if you want to enable edk2 logging to S76 EC. + +config EDK2_SKIP_PS2_DETECT + bool "Skip PS/2 keyboard detection check" + depends on EDK2_PS2_SUPPORT + default n + help + Skips checking for the PS/2 keyboard presence and assumes the PS/2 + keyboard is connected. Useful for laptops, where PS/2 keyboard is + always connected, to save a precious second or two of boot time. + +config EDK2_ENABLE_IPXE + bool "Include iPXE in edk2 payload" + default n + select PXE + help + Instructs coreboot build system to build iPXE EFI target and include + it in the EDK2 payload. + +config EDK2_IPXE_OPTION_NAME + string "iPXE option name" + depends on EDK2_ENABLE_IPXE + default "iPXE Network Boot" + help + Configures how the iPXE boot option should be displayed in boot menu + of EDK2 Payload. This name will be passed as PCD to the EDK2 build + system. + +config EDK2_SECURE_BOOT_DEFAULT_ENABLE + bool "Set Secure Boot state to enabled by default" + default y + depends on EDK2_SECURE_BOOT_SUPPORT + help + Sets the UEFI Secure Boot state to enabled by default. + +config EDK2_SATA_PASSWORD + bool "Enable TianoCore SATA disk password" + default n + help + Enable SATA disk password suupport in the TianoCore payload. + +config EDK2_OPAL_PASSWORD + bool "Enable TianoCore TCG OPAL password" + default n + help + Enables TCG OPAL disk password in the TianoCore Payload. + +config EDK2_SETUP_PASSWORD + bool "Enable Setup Menu password" + default n + help + Enables setup menu password in the TianoCore Payload. + +config EDK2_PERFORMANCE_MEASUREMENT_ENABLE + bool "Enable firmware performance measurement" + default n + help + Enables firmware performance measurement in the TianoCore Payload. + The measurements will be exposed to OS via FPDT ACPI table. Should be + used in conjunction with EDK2_CPU_TIMER_LIB to match the coreboot + measurement made with TSC. If EDK2_CPU_TIMER_LIB cannot be enabled on + the platform, the counters wil be mismatched and the performance will + not be properly reported by OS. + +# DasharoModulePkg specific options + +config EDK2_DASHARO_SYSTEM_FEATURES + bool "Enable Dasharo System Features menu in EDK2" + default n + help + Enables Dasharo System Features submenu in the EDK2 setup menu. + +if EDK2_DASHARO_SYSTEM_FEATURES + +config EDK2_DASHARO_SECURITY_OPTIONS + bool "Enable EDK2 Dasharo Security Options Menu" + default n + help + Enables the security configuration submenu in Dasharo System Features. + +config EDK2_SHOW_CAMERA_OPTION + bool "Show Camera option in Dasharo Security Options Menu" + depends on EDK2_DASHARO_SECURITY_OPTIONS + help + Shows the Camera option in Dasharo Security Options submenu in + Dasharo System Features menu. + +config EDK2_SHOW_WIFI_BT_OPTION + bool "Show WiFi/BT option in Dasharo Security Options Menu" + depends on EDK2_DASHARO_SECURITY_OPTIONS + help + Shows the WiFi/BT option in Dasharo Security Options submenu in + Dasharo System Features menu. + +config EDK2_DASHARO_INTEL_ME_OPTIONS + bool "Enable EDK2 Dasharo ME Configuration Menu" + default n + help + Enables the Intel ME configuration submenu in Dasharo System Features. + +config EDK2_DASHARO_INTEL_ME_CBNT_STATUS + bool "Enable CBnT status on the Intel ME configuration page" + depends on INTEL_CBNT_SUPPORT && EDK2_DASHARO_INTEL_ME_OPTIONS + default n + help + Enables printing of CBnT related registers on the Intel Management Engine + status page in Dasharo System Features + +config EDK2_DASHARO_USB_CONFIG + bool "Enable EDK2 Dasharo USB Configuration Menu" + default n + help + Enables the EDK2 USB stack configuration submenu in Dasharo System Features. + +config EDK2_DASHARO_NETWORK_CONFIG + bool "Enable EDK2 Dasharo Network Stack Configuration Menu" + default n + help + Enables the EDK2 network stack configuration submenu in Dasharo System Features. + +config EDK2_DASHARO_CHIPSET_CONFIG + bool "Enable EDK2 Dasharo Chipset Configuration Menu" + default n + help + Enables the EDK2 chipset configuration submenu in Dasharo System Features menu. + +config EDK2_DASHARO_OC_WDT_SHOW + bool "Enable watchdog configuration options" + depends on EDK2_DASHARO_CHIPSET_CONFIG + default y if SOC_INTEL_COMMON_OC_WDT_ENABLE + default n + help + Enable watchdog-related options in the Dasharo Chipset Configuration + submenu. + +config EDK2_DASHARO_POWER_CONFIG + bool "Enable EDK2 Dasharo Power Configuration Menu" + default n + help + Enables the EDK2 power configuration submenu in Dasharo System Features menu. + +config EDK2_SLEEP_TYPE_OPTION + bool "Show Sleep Type option in Dasharo Power Configuration Menu" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Shows the Sleep Type option in EDK2 power configuration submenu in + Dasharo System Features menu. + +config EDK2_FAN_CURVE_OPTION + bool "Show Fan Curve option in Dasharo Power Configuration Menu" + depends on EDK2_DASHARO_POWER_CONFIG + default n + help + Shows the Fan Curve option in EDK2 power configuration submenu in + Dasharo System Features menu. + +config EDK2_FAN_OFF_CURVE_OPTION + bool "Show Fan Off option in the Fan Curve option list" + depends on EDK2_FAN_CURVE_OPTION + default n + help + Shows the Fan Off option when selecting Fan Curve in EDK2 power + configuration submenu in Dasharo System Features menu. + +config EDK2_BATTERY_CONFIG_OPTION + bool "Show Battery Threshold options in Dasharo Power Configuration Menu" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Enables battery threshold options in the EDK2 power management + configuration submenu. + +config EDK2_CPU_THROTTLING_THRESHOLD_OPTION + bool "Display CPU throttling threshold option" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Enables setting a custom CPU throttling threshold temperature + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + int "CPU throttling threshold default value" + depends on EDK2_CPU_THROTTLING_THRESHOLD_OPTION + default 20 + range 0 63 + help + Board-specific CPU throttling threshold temperature default value + +config EDK2_USB_PORT_POWER_OPTION + bool "Show USB Port Power option in Dasharo Power Configuration Menu" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Shows the USB Port Power option in EDK2 power configuration submenu in + Dasharo System Features menu. + +config EDK2_DGPU_POWER_OPTION + bool "Show DGPU power option in Dasharo Power Configuration Menu" + default n + depends on EDK2_DASHARO_POWER_CONFIG + depends on !EDK2_DISABLE_OPTION_ROMS + help + Shows the DGPU power option in EDK2 power configuration submenu in + Dasharo System Features menu. + +config EDK2_DASHARO_PCI_CONFIG + bool "Enable EDK2 Dasharo PCI/PCIe Configuration Menu" + default n + help + Enables the EDK2 PCI/PCIe configuration submenu in Dasharo System Features menu. + +config EDK2_DASHARO_MEMORY_CONFIG + bool "Enable EDK2 Dasharo Memory Configuration Menu" + default n + help + Enables the EDK2 Memory configuration submenu in Dasharo System Features menu. + +config EDK2_DASHARO_SPD_PROFILE_OPTION + bool "Show Memory SPD profile in Dasharo Memory Configuration Menu" + depends on EDK2_DASHARO_MEMORY_CONFIG + default n + help + Shows the Memory SPD profile option in EDK2 Memory configuration + submenu in Dasharo System Features menu. + +config EDK2_DASHARO_IBECC_OPTION + bool "Show In-band ECC in Dasharo Memory Configuration Menu" + depends on EDK2_DASHARO_MEMORY_CONFIG + default n + help + Shows the In-band ECC option in EDK2 Memory configuration submenu in + Dasharo System Features menu. + +config EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE + bool "Enable EDK2 network boot option by default" + default n + help + Enables the network boot option in EDK2 by default. + +config EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE + bool "Enable serial console redirection by default" + depends on EDK2_SERIAL_SUPPORT + default n + help + Enable serial port output in edk2 by default. Serial output limits + the performance of edk2's FrontPage. + +config EDK2_HAVE_2ND_UART + bool "Have second serial port for console redirection" + depends on EDK2_SERIAL_SUPPORT + depends on DRIVERS_UART_8250IO + default n + help + Enable support for two serial ports in edk2. + +config EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE + bool "Enable second serial port console redirection by default" + depends on EDK2_SERIAL_SUPPORT + depends on EDK2_HAVE_2ND_UART + default n + help + Enable serial port output on second UART in edk2 by default. Serial + output limits the performance of edk2's FrontPage. + +config EDK2_DASHARO_CPU_CONFIG + bool "Enable EDK2 Dasharo CPU Configuration Menu" + default n + help + Enables the EDK2 CPU configuration submenu in Dasharo System Features menu. + +config EDK2_CORE_DISABLE_OPTION + bool "Show CPU core disabling option in Dasharo CPU Configuration Menu" + depends on EDK2_DASHARO_CPU_CONFIG + help + Shows the CPU core disabling option in EDK2 CPU configuration submenu in + Dasharo System Features menu. + +config EDK2_HYPERTHREADING_OPTION + bool "Show CPU Hyper-Threading option in Dasharo CPU Configuration Menu" + depends on EDK2_DASHARO_CPU_CONFIG + default n + help + Shows the CPU Hyper-Threading option in EDK2 CPU configuration submenu in + Dasharo System Features menu. + +endif + +config EDK2_BOOT_MENU_KEY + hex "TianoCore boot menu key" + default 0x0016 + help + Select the TianoCore payload boot menu key: + UP 0x0001 + DOWN 0x0002 + RIGHT 0x0003 + LEFT 0x0004 + HOME 0x0005 + END 0x0006 + INSERT 0x0007 + DELETE 0x0008 + F1 0x000B + F2 0x000C + F3 0x000D + F4 0x000E + F5 0x000F + F6 0x0010 + F7 0x0011 + F8 0x0012 + F9 0x0013 + F10 0x0014 + F11 0x0015 + F12 0x0016 + ESC 0x0017 + +config EDK2_SETUP_MENU_KEY + hex "TianoCore setup menu key" + default 0x0017 + help + Select the TianoCore payload setup menu key: + UP 0x0001 + DOWN 0x0002 + RIGHT 0x0003 + LEFT 0x0004 + HOME 0x0005 + END 0x0006 + INSERT 0x0007 + DELETE 0x0008 + F1 0x000B + F2 0x000C + F3 0x000D + F4 0x000E + F5 0x000F + F6 0x0010 + F7 0x0011 + F8 0x0012 + F9 0x0013 + F10 0x0014 + F11 0x0015 + F12 0x0016 + ESC 0x0017 + +config EDK2_DISABLE_MTRR_PROGRAMMING + bool "Disable MTRR programming in EDK2 Payload" + default y + help + Disables MTRRs programming in the TianoCore Payload. + +config EDK2_ENABLE_BATTERY_CHECK + bool "Enable battery level check" + default n + help + Enables the battery level check in the UEFI Payload. If the battery + level is too low, a pop up will appear with appropriate warning and + prevent booting, which could cause disk data corruption. + +config EDK2_DISABLE_OPTION_ROMS + bool "Disable OptionROM loading by default" + default n + help + Disables OptionROM loading and execution in UEFI Payload. By default + all PCI OptionROMs are loaded and executed. + +config EDK2_PRINT_SOL_STRINGS + bool "Print Sign Of Life string on boot" + default n + help + Prints the BIOS and, if available, the EC version on the screen + during boot prompt in UEFI Payload. + +config EDK2_RAM_DISK_ENABLE + bool "Enable RAM Disk support" + default n + help + Enable support for RAM Disks in EDK2 UEFIPayload. + +config EDK2_LAN_ROM_DRIVER + string "Optional LAN ROM driver file" + help + Integrates LAN ROM driver in TianoCore Payload. Takes an EFI driver + as input. + +config EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS + bool "Create boot entries for pre-installed OSes" + default n + help + Tell UEFIPaylaod to scan available EFI System Partitions and create + boot options from the bootloader binaries found on the disks. + +config EDK2_USE_UEFIVAR_BACKED_TPM_PPI + bool "Use UEFI variable-backed TPM PPI" + default n + depends on !EDK2_DISABLE_TPM + help + Tell UEFIPayload to use TPM PPI buffer in UEFI variables. Workaround + for platform-specific issues causing the RAM to not be preserved + across reboots. + + If unsure, say N. + +config EDK2_ENABLE_FAST_BOOT_FEATURE + bool "Enable fast boot feature in EDK2 Payload" + default n + help + Enables fast boot option in the TianoCore Payload. + +config EDK2_ENABLE_QUIET_BOOT_FEATURE + bool "Enable quiet boot feature in EDK2 Payload" + default n + help + Enables quiet boot option in the TianoCore Payload. + +config EDK2_GRAPHICAL_CAPSULE_PROGRESS + bool "Enable graphical capsule update progress" + default y + help + An alternative is a textual one which also appears on serial, the default + is graphical. + +config EDK2_FUM_AUTO_IPXE_BOOT + bool "Launch the auto-update sequence in Firmware Update Mode" + depends on DASHARO_FIRMWARE_UPDATE_MODE + default y + help + By default FUM results in automatic booting into DTS via iPXE, the + alternative provides a way to disable all flash locks on the next boot + but otherwise boot the platform as usual. + +endif diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 6464e9f8514..e5454bae25d 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -8,6 +8,7 @@ export WORKSPACE := $(CURDIR)/workspace export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY))) ifeq ($(CONFIG_EDK2_USE_EDK2_PLATFORMS),y) +BUILD_STR += -D USE_EDK2_PLATFORMS=TRUE export EDK2_PLATFORMS_PATH := $(WORKSPACE)/edk2-platforms export PACKAGES_PATH := $(EDK2_PATH):\ $(EDK2_PLATFORMS_PATH)/Platform/Intel:\ @@ -18,15 +19,18 @@ export PACKAGES_PATH := $(EDK2_PATH):\ $(EDK2_PLATFORMS_PATH)/Features/Intel/OutOfBandManagement:\ $(EDK2_PLATFORMS_PATH)/Features/Intel/PowerManagement:\ $(EDK2_PLATFORMS_PATH)/Features/Intel/SystemInformation:\ - $(EDK2_PLATFORMS_PATH)/Features/Intel/UserInterface + $(EDK2_PLATFORMS_PATH)/Features/Intel/UserInterface: \ + $(EDK2_PLATFORMS_PATH)/Drivers/ else export PACKAGES_PATH := $(EDK2_PATH) endif OBJCOPY = $(GCC_PREFIX)objcopy +PAYLOAD_NAME=DasharoPayloadPkg + ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y) -BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc +BUILD_STR += -p $(PAYLOAD_NAME)/$(PAYLOAD_NAME).dsc endif BUILD_STR += -t COREBOOT BUILD_STR += -D BOOTLOADER=COREBOOT @@ -112,8 +116,24 @@ ifeq ($(CONFIG_EDK2_SECURE_BOOT_SUPPORT), y) BUILD_STR += -D SECURE_BOOT_ENABLE=TRUE endif # PCIEXP_SUPPORT_RESIZABLE_BARS = FALSE -ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y) -BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE +#ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y) +#BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE +#endif +# CAPSULE_SUPPORT = FALSE +# CAPSULE_MAIN_FW_GUID = +ifneq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES),) +BUILD_STR += -D CAPSULE_SUPPORT=TRUE +BUILD_STR += -D CAPSULE_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID) +endif +# QEMU_PLATFORM = FALSE +ifneq ($(CONFIG_QEMU_PLATFORM),) +BUILD_STR += -D QEMU_PLATFORM=TRUE +endif + +# GRAPHICAL_CAPSULE_PROGRESS = TRUE +# Decides if capsule update progress bar should use Graphics or Text based lib +ifneq ($(CONFIG_EDK2_GRAPHICAL_CAPSULE_PROGRESS),y) +BUILD_STR += -D GRAPHICAL_CAPSULE_PROGRESS=FALSE endif # @@ -128,6 +148,10 @@ endif # GOP_DRIVER = FALSE ifeq ($(CONFIG_EDK2_GOP_DRIVER), y) BUILD_STR += -D USE_PLATFORM_GOP=TRUE +# USE_LAPTOP_LID_LIB = FALSE +ifeq ($(CONFIG_EDK2_USE_LAPTOP_LID_LIB), y) +BUILD_STR += -D USE_LAPTOP_LID_LIB=TRUE +endif endif # PRIORITIZE_INTERNAL = FALSE ifeq ($(CONFIG_EDK2_PRIORITIZE_INTERNAL),y) @@ -150,6 +174,285 @@ ifeq ($(CONFIG_EDK2_USE_LAPIC_TIMER),y) BUILD_STR += -D TIMER_SUPPORT=LAPIC endif +# +# The Dasharo repository has the following additional options: +# +ifneq ($(CONFIG_EDK2_DISABLE_TPM),y) +ifeq ($(CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI),y) +BUILD_STR += -D USE_UEFIVAR_BACKED_TPM_PPI=TRUE +endif +endif +# ABOVE_4G_MEMORY = TRUE +ifneq ($(CONFIG_EDK2_ABOVE_4G_MEMORY),y) +BUILD_STR += -D ABOVE_4G_MEMORY=FALSE +endif +# PcdSerialRedirectionDefaultState = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSerialRedirectionDefaultState=TRUE +endif +# SERIAL_TERMINAL = FALSE +ifeq ($(CONFIG_EDK2_SERIAL_SUPPORT),y) +BUILD_STR += -D DISABLE_SERIAL_TERMINAL=FALSE +BUILD_STR += -D SERIAL_TERMINAL=TRUE +ifeq ($(CONFIG_EDK2_HAVE_2ND_UART),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdHave2ndUart=TRUE +ifeq ($(CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSerialRedirection2DefaultState=TRUE +endif +endif # CONFIG_EDK2_HAVE_2ND_UART +endif # SERIAL_TERMINAL +# PS2_KEYBOARD_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_PS2_SUPPORT),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowPs2Option=TRUE +# SKIP_PS2_DETECT = FALSE +ifeq ($(CONFIG_EDK2_SKIP_PS2_DETECT),y) +BUILD_STR += --pcd g$(PAYLOAD_NAME)TokenSpaceGuid.PcdSkipPs2Detect=TRUE +endif # SKIP_PS2_DETECT +else +BUILD_STR += --pcd g$(PAYLOAD_NAME)TokenSpaceGuid.PcdSkipPs2Detect=TRUE +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowPs2Option=FALSE +endif # PS2_KEYBOARD_ENABLE +# SYSTEM76_EC_LOGGING = FALSE +ifeq ($(CONFIG_EDK2_SYSTEM76_EC_LOGGING),y) +BUILD_STR += -D SYSTEM76_EC_LOGGING=TRUE +endif +# NETWORK_IPXE = FALSE +ifeq ($(CONFIG_EDK2_IPXE),y) +BUILD_STR += -D NETWORK_IPXE=TRUE +BUILD_STR += --pcd g$(PAYLOAD_NAME)TokenSpaceGuid.PcdiPXEOptionName=L"$(CONFIG_EDK2_IPXE_OPTION_NAME)" +endif +# SECURE_BOOT_DEFAULT_ENABLE = TRUE +ifneq ($(CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE),y) +BUILD_STR += -D SECURE_BOOT_DEFAULT_ENABLE=FALSE +endif +# SATA_PASSWORD_ENABLE = TRUE +ifeq ($(CONFIG_EDK2_SATA_PASSWORD),y) +BUILD_STR += -D SATA_PASSWORD_ENABLE=TRUE +endif +# OPAL_PASSWORD_ENABLE = TRUE +ifeq ($(CONFIG_EDK2_OPAL_PASSWORD),y) +BUILD_STR += -D OPAL_PASSWORD_ENABLE=TRUE +endif +# SETUP_PASSWORD_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_SETUP_PASSWORD),y) +BUILD_STR += -D SETUP_PASSWORD_ENABLE=TRUE +endif +# NETWORK_LAN_ROM = FALSE +ifneq ($(CONFIG_EDK2_LAN_ROM_DRIVER),) +BUILD_STR += -D NETWORK_LAN_ROM=TRUE +endif +# DISABLE_MTRR_PROGRAMMING = TRUE +ifneq ($(CONFIG_EDK2_DISABLE_MTRR_PROGRAMMING),y) +BUILD_STR += -D DISABLE_MTRR_PROGRAMMING=FALSE +endif +# IOMMU_ENABLE = FALSE +ifeq ($(CONFIG_IOMMU_ENABLE),y) +BUILD_STR += -D IOMMU_ENABLE=TRUE +endif +# DASHARO_SYSTEM_FEATURES = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_SYSTEM_FEATURES),y) +BUILD_STR += -D DASHARO_SYSTEM_FEATURES_ENABLE=TRUE +endif +# DASHARO_SECURITY_OPTIONS = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_SECURITY_OPTIONS),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowSecurityMenu=TRUE +endif +# DASHARO_INTEL_ME_OPTIONS = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowIntelMeMenu=TRUE +endif +# DASHARO_NETWORK_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_NETWORK_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowNetworkMenu=TRUE +endif +# DASHARO_USB_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_USB_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowUsbMenu=TRUE +endif +# DASHARO_CHIPSET_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_CHIPSET_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowChipsetMenu=TRUE +endif +# Always set the default power failure state to some value +ifeq ($(CONFIG_HAVE_POWER_STATE_AFTER_FAILURE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdDefaultPowerFailureState=$(CONFIG_MAINBOARD_POWER_FAILURE_STATE) +else +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdDefaultPowerFailureState=0 +endif +# DASHARO_POWER_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_POWER_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowPowerMenu=TRUE + +ifneq ($(CONFIG_EDK2_SLEEP_TYPE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowSleepType=FALSE +endif # CONFIG_EDK2_SLEEP_TYPE_OPTION + +ifeq ($(CONFIG_EDK2_FAN_CURVE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowFanCurve=TRUE +ifeq ($(CONFIG_EDK2_FAN_OFF_CURVE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowFanCurveOffOption=TRUE +endif # CONFIG_EDK2_FAN_OFF_CURVE_OPTION +endif # CONFIG_EDK2_FAN_CURVE_OPTION + +ifeq ($(CONFIG_EDK2_BATTERY_CONFIG_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowBatteryThresholds=TRUE +endif + +ifeq ($(CONFIG_EDK2_USB_PORT_POWER_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowUsbPowerOption=TRUE +endif + +ifeq ($(CONFIG_EDK2_DGPU_POWER_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowDGPUPowerOption=TRUE +endif + +endif # CONFIG_EDK2_DASHARO_POWER_CONFIG +# DASHARO_PCI_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_PCI_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowPciMenu=TRUE +endif +# PcdShowMemoryMenu = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_MEMORY_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowMemoryMenu=TRUE +ifeq ($(CONFIG_EDK2_DASHARO_SPD_PROFILE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowMemorySpdProfileOption=TRUE +endif +ifeq ($(CONFIG_EDK2_DASHARO_IBECC_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowMemoryIbeccOption=TRUE +endif +endif # PcdShowMemoryMenu +# DASHARO_NETWORK_BOOT_DEFAULT_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdDefaultNetworkBootEnable=TRUE +endif +ifeq ($(CONFIG_EDK2_DASHARO_OC_WDT_SHOW),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdOcWdtEnableDefault=TRUE +endif +ifeq ($(CONFIG_EDK2_DASHARO_OC_WDT_SHOW),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowOcWdtOptions=TRUE +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdOcWdtTimeoutDefault=$(CONFIG_EDK2_DASHARO_OC_WDT_TIMEOUT) +endif +# PCIEXP_SUPPORT_RESIZABLE_BARS = FALSE +ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPciMenuShowResizeableBars=TRUE +endif +# BATTERY_CHECK = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_BATTERY_CHECK),y) +BUILD_STR += -D BATTERY_CHECK=TRUE +endif +# LOAD_OPTION_ROMS = TRUE +ifeq ($(CONFIG_EDK2_DISABLE_OPTION_ROMS),y) +BUILD_STR += -D LOAD_OPTION_ROMS=FALSE +endif +# PRINT_SOL_STRINGS = FALSE +ifeq ($(CONFIG_EDK2_PRINT_SOL_STRINGS),y) +BUILD_STR += --pcd g$(PAYLOAD_NAME)TokenSpaceGuid.PcdPrintSolStrings=TRUE +endif +# CREATE_PREINSTALLED_BOOT_OPTIONS = FALSE +ifeq ($(CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS),y) +BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdCreatePreInstalledBootOptions=TRUE +endif +# SHOW_CAMERA_OPTION = FALSE +ifeq ($(CONFIG_EDK2_SHOW_CAMERA_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSecurityShowCameraOption=TRUE +endif +# SHOW_WIFI_BT_OPTION = FALSE +ifeq ($(CONFIG_EDK2_SHOW_WIFI_BT_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSecurityShowWiFiBtOption=TRUE +endif +# PERFORMANCE_MEASUREMENT_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE),y) +BUILD_STR += -D PERFORMANCE_MEASUREMENT_ENABLE=TRUE +endif +ifneq ($(CONFIG_HAVE_INTEL_ME_HAP),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdIntelMeHapAvailable=FALSE +endif +ifneq ($(CONFIG_INTEL_ME_DEFAULT_STATE),) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdIntelMeDefaultState=$(CONFIG_INTEL_ME_DEFAULT_STATE) +endif +ifeq ($(CONFIG_EDK2_DGPU_POWER_OPTION),y) +ifneq ($(CONFIG_DGPU_ONLY_AVAILABLE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdDgpuOnlyAvailable=FALSE +endif +endif +# RAM_DISK_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_RAM_DISK_ENABLE),y) +BUILD_STR += -D RAM_DISK_ENABLE=TRUE +endif +# APU_CONFIG_ENABLE = FALSE +ifeq ($(CONFIG_VENDOR_PCENGINES),y) +BUILD_STR += -D APU_CONFIG_ENABLE=TRUE +endif + +BUILD_STR += -D BOOT_MENU_KEY=$(CONFIG_EDK2_BOOT_MENU_KEY) +BUILD_STR += -D SETUP_MENU_KEY=$(CONFIG_EDK2_SETUP_MENU_KEY) + +# PcdShowLockBios = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_BIOS_LOCK),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowLockBios=TRUE +endif +# PcdShowSmmBwp = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_SMM_BWP),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowSmmBwp=TRUE +endif +# PcdSleepTypeDefaultS3 = FALSE +ifeq ($(CONFIG_EDK2_S3_SLEEP_DEFAULT),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSleepTypeDefaultS3=TRUE +endif +# PcdShowFum = TRUE +ifneq ($(CONFIG_EDK2_ENABLE_FUM),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowFum=FALSE +endif +# UART_ON_SUPERIO = FALSE +ifeq ($(CONFIG_EDK2_SERIAL_ON_SUPERIO),y) +BUILD_STR += -D UART_ON_SUPERIO=TRUE +endif +# FTDI_USB_UART_SUPPORT = FALSE +ifeq ($(CONFIG_EDK2_FTDI_USB_UART_SUPPORT),y) +BUILD_STR += -D FTDI_USB_UART_SUPPORT=TRUE +endif +# PcdShowCpuMenu = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_CPU_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowCpuMenu=TRUE +endif +# PcdShowCpuCoreDisable = FALSE +ifeq ($(CONFIG_EDK2_CORE_DISABLE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowCpuCoreDisable=TRUE +endif +# PcdShowCpuHyperThreading = FALSE +ifeq ($(CONFIG_EDK2_HYPERTHREADING_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowCpuHyperThreading=TRUE +endif +# PcdCpuHyperThreadingDefault = TRUE +ifneq ($(CONFIG_EDK2_HYPERTHREADING_DEFAULT_STATE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdCpuHyperThreadingDefault=FALSE +endif +# PcdShowCpuThrottlingThreshold = FALSE +ifeq ($(CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowCpuThrottlingThreshold=TRUE +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdCpuThrottlingOffsetDefault=$(CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT) +# PcdCpuMaxTemperature = 100 +ifneq ($(CONFIG_CPU_MAX_TEMPERATURE),) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdCpuMaxTemperature=$(CONFIG_CPU_MAX_TEMPERATURE) +endif +endif +# PcdFastBootFeatureEnabled = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE),y) +BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdFastBootFeatureEnabled=TRUE +endif +# PcdQuietBootFeatureEnabled = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE),y) +BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdQuietBootFeatureEnabled=TRUE +endif +# PcdIntelMeMenuShowCbntStatus = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_INTEL_ME_CBNT_STATUS),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdIntelMeMenuShowCbntStatus=TRUE +endif +# PcdFumAutoIpxeBoot = TRUE +ifneq ($(CONFIG_EDK2_FUM_AUTO_IPXE_BOOT),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdFumAutoIpxeBoot=FALSE +endif + endif # @@ -169,7 +472,7 @@ ifneq ($(CONFIG_EDK2_CUSTOM_BUILD_PARAMS),) BUILD_STR += $(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) endif -all: UefiPayloadPkg +all: $(PAYLOAD_NAME) $(WORKSPACE): mkdir $(WORKSPACE) @@ -193,12 +496,12 @@ $(EDK2_PLATFORMS_PATH): $(WORKSPACE) $(EDK2_PATH): $(WORKSPACE) if [ ! -d "$(EDK2_PATH)" ]; then \ - git clone --recurse-submodules $(CONFIG_EDK2_REPOSITORY) $(EDK2_PATH) -j5; \ + git clone $(CONFIG_EDK2_REPOSITORY) $(EDK2_PATH) -j5; \ fi cd $(EDK2_PATH); \ - git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true; \ - if [ -e UefiPayloadPkg/ShimLayer/UniversalPayload.o ]; then \ - rm UefiPayloadPkg/ShimLayer/UniversalPayload.o; \ + git checkout -- MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true; \ + if [ -e $(PAYLOAD_NAME)/ShimLayer/UniversalPayload.o ]; then \ + rm $(PAYLOAD_NAME)/ShimLayer/UniversalPayload.o; \ fi; \ echo " Fetching new commits from $(CONFIG_EDK2_REPOSITORY)"; \ git fetch origin 2>/dev/null; \ @@ -227,10 +530,29 @@ logo: $(EDK2_PATH) gop_driver: $(EDK2_PATH) if [ -n "$(CONFIG_EDK2_GOP_DRIVER)" ]; then \ echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \ - cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/UefiPayloadPkg/IntelGopDriver.efi; \ - cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/UefiPayloadPkg/vbt.bin; \ + cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/IntelGopDriver.efi; \ + cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/vbt.bin; \ fi; \ +lan_rom: $(EDK2_PATH) + case "$(CONFIG_EDK2_LAN_ROM_DRIVER)" in \ + "") ;; \ + /*) mkdir -p $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/; \ + cp $(CONFIG_EDK2_LAN_ROM_DRIVER) \ + $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/LanRom.efi;; \ + *) mkdir -p $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/; \ + cp $(top)/$(CONFIG_EDK2_LAN_ROM_DRIVER) \ + $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/LanRom.efi;; \ + esac \ + +ipxe_rom: $(EDK2_PATH) + if [ "$(CONFIG_EDK2_IPXE)" == "y" ]; then \ + echo " Including externally built iPXE"; \ + mkdir -p $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/; \ + cp $(top)/payloads/external/iPXE/ipxe/ipxe.rom \ + $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/ipxe.efi; \ + fi \ + checktools: echo -n "EDK2: Checking uuid-dev:" echo "#include " > libtest.c @@ -268,7 +590,7 @@ print: -e 's/s /Build: Silent/' \ -e 's/t /Toolchain: /' -prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver +prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver lan_rom ipxe_rom cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \ @@ -277,49 +599,49 @@ prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver cat ../tools_def.txt >> $(EDK2_PATH)/Conf/tools_def.txt; \ fi; \ -$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd: \ +$(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd: \ prep print cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ echo -n "EDK2: Building... "; \ build -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR) \ - -y $(WORKSPACE)/Build/UefiPayloadPkgX64/UEFIPAYLOAD.txt; \ + -y $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/UEFIPAYLOAD.txt; \ if [ ! -f $@ ]; then \ echo "Failed!"; \ exit 1; \ fi echo "Success!"; \ -$(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf: \ +$(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/UniversalPayload.elf: \ prep print cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ echo -n "EDK2: Building... "; \ - $(EDK2_PATH)/UefiPayloadPkg/UniversalPayloadBuild.sh -a IA32 -b $(RELEASE_STR) $(BUILD_STR) + $(EDK2_PATH)/$(PAYLOAD_NAME)/UniversalPayloadBuild.sh -a IA32 -b $(RELEASE_STR) $(BUILD_STR) if [ ! -f $@ ]; then \ echo "Failed!"; \ exit 1; \ fi echo "Success!"; \ -$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll: \ - $(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf prep - cd $(WORKSPACE)/Build/UefiPayloadPkgX64 && \ +$(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/IA32/$(PAYLOAD_NAME)/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll: \ + $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/UniversalPayload.elf prep + cd $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64 && \ $(OBJCOPY) -I binary UniversalPayload.elf -O elf32-i386 -B i386 \ - $(EDK2_PATH)/UefiPayloadPkg/ShimLayer/UniversalPayload.o; \ + $(EDK2_PATH)/$(PAYLOAD_NAME)/ShimLayer/UniversalPayload.o; \ cd $(WORKSPACE) && \ source $(EDK2_PATH)/edksetup.sh; \ - build -p UefiPayloadPkg/UefiPayloadPkg.dsc -b $(RELEASE_STR) -a IA32 -a X64 \ - -m UefiPayloadPkg/ShimLayer/ShimLayer.inf \ + build -p $(PAYLOAD_NAME)/$(PAYLOAD_NAME).dsc -b $(RELEASE_STR) -a IA32 -a X64 \ + -m $(PAYLOAD_NAME)/ShimLayer/ShimLayer.inf \ -t COREBOOT -D BOOTLOADER=COREBOOT -D SHIMLAYER=TRUE \ - -y $(WORKSPACE)/Build/UefiPayloadPkgX64/ShimLayer.txt + -y $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/ShimLayer.txt -UefiPayloadPkg: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd - mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \ +$(PAYLOAD_NAME): $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd + mv $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \ ../../../build/UEFIPAYLOAD.fd -UniversalPayload: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll - mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \ +UniversalPayload: $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/IA32/$(PAYLOAD_NAME)/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll + mv $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/IA32/$(PAYLOAD_NAME)/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \ ../../../build/ShimmedUniversalPayload.elf clean: @@ -328,4 +650,4 @@ clean: distclean: rm -rf $(WORKSPACE) -.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg UniversalPayload clean distclean +.PHONY: $(EDK2_PATH) checktools logo $(PAYLOAD_NAME) UniversalPayload clean distclean diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index ff25d81957f..90a3e482e9d 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -54,12 +54,12 @@ choice default IPXE_STABLE config IPXE_STABLE - bool "2022.1" + bool "2025.03" help iPXE uses a rolling release with no stable version, for reproducibility, use the last commit of a given month as the 'stable' version. - This is iPXE from the end of January, 2022. + This is iPXE from the end of March, 2025. config IPXE_MASTER bool "master" @@ -70,7 +70,9 @@ endchoice config IPXE_SERIAL_CONSOLE bool "Enable iPXE serial console" - def_bool y + default n if PAYLOAD_EDK2 && EDK2_ENABLE_IPXE + default n if PAYLOAD_SEABIOS && SEABIOS_ADD_SERCON_PORT_FILE + default y help Enable/disable iPXE serial console. Since SeaBIOS supports serial console this option might be helpful to avoid duplicated output. @@ -116,6 +118,13 @@ config IPXE_TRUST_CMD digital signature of file prior loading it, and restrict to loading trusted files only. +config IPXE_CUSTOM_BUILD_ID + string "iPXE custom build_id variable" + default "" + help + This option allows user to customize build_id for reproducible builds. + It is 32-bit hexadecimal number without "0x" prefix. + endif # BUILD_IPXE endmenu diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 7ec8126c977..5c30ee72baf 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -1,15 +1,36 @@ ## SPDX-License-Identifier: GPL-2.0-only -# 2022.1 - Last commit of January 2022 +# 2023.8 - Last commit of August 2023 # When updating, change the name both here and in payloads/external/iPXE/Kconfig -STABLE_COMMIT_ID=6ba671acd922ee046b257c5119b8a0f64d275473 + +# Temporarily Dasharo fork is used until i225/i226 native support is merged. +STABLE_COMMIT_ID=6c7068fce4bba31b4d03a6990dedc530c0727588 TAG-$(CONFIG_IPXE_MASTER)=origin/master TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID) project_name=iPXE project_dir=ipxe -project_git_repo=https://git.ipxe.org/ipxe.git +project_git_repo=https://github.com/Dasharo/ipxe.git + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +ifneq ($(CONFIG_IPXE_CUSTOM_BUILD_ID),) +PXE_MAKE_OPTS := BUILD_ID_CMD="echo 0x$(CONFIG_IPXE_CUSTOM_BUILD_ID)" +endif + +ifeq ($(CONFIG_IPXE_BUILD_EFI),y) +IPXE_BUILD_TARGET := bin-x86_64-efi-sb/ipxe.efi +# Workaround problems with unrecognized ipxe/util/elf2efi relocations +PXE_MAKE_OPTS += EXTRA_CFLAGS="$(CFLAGS_x86_64) -fno-pic" +else +IPXE_BUILD_TARGET := bin/$(PXE_ROM_PCI_ID).rom +endif all: build @@ -28,6 +49,7 @@ fetch: $(project_dir) checkout: fetch echo " Checking out $(project_name) revision $(TAG-y)" cd $(project_dir); \ + git checkout -- src/config/general.h; \ git checkout master; \ git branch -D coreboot 2>/dev/null; \ git checkout -b coreboot $(TAG-y) @@ -59,12 +81,12 @@ endif build: config $(CONFIG_SCRIPT) ifeq ($(CONFIG_HAS_SCRIPT),y) echo " MAKE $(project_name) $(TAG-y) EMBED=$(CONFIG_SCRIPT)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) + $(MAKE) -C $(project_dir)/src $(IPXE_BUILD_TARGET) EMBED=$(CONFIG_SCRIPT) $(PXE_MAKE_OPTS) else echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src $(IPXE_BUILD_TARGET) $(PXE_MAKE_OPTS) endif - cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom + cp $(project_dir)/src/$(IPXE_BUILD_TARGET) $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h" cp "$(project_dir)/src/config/serial.h.cb" "$(project_dir)/src/config/serial.h" diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 06aa038caac..874c86d8ce4 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -180,6 +180,19 @@ static void acpi_create_mcfg(acpi_header_t *header, void *unused) header->length = current - (unsigned long)mcfg; } +static bool should_publish_tpm_log(void) +{ + /* + * EDK will publish its own version of the log after parsing and + * importing coreboot's log discovered through CBMEM. + * + * Publishing is done by appending a table, so coreboot must avoid + * adding corresponding log tables to let OS find a more complete one + * from EDK. + */ + return !CONFIG(PAYLOAD_EDK2) || CONFIG(EDK2_DISABLE_TPM); +} + static void *get_tcpa_log(u32 *size) { const struct cbmem_entry *ce; @@ -207,7 +220,7 @@ static void *get_tcpa_log(u32 *size) static void acpi_create_tcpa(acpi_header_t *header, void *unused) { - if (tlcl_get_family() != TPM_1) + if (!should_publish_tpm_log() || tlcl_get_family() != TPM_1) return; acpi_tcpa_t *tcpa = (acpi_tcpa_t *)header; @@ -253,7 +266,7 @@ static void *get_tpm2_log(u32 *size) static void acpi_create_tpm2(acpi_header_t *header, void *unused) { - if (tlcl_get_family() != TPM_2) + if (!should_publish_tpm_log() || tlcl_get_family() != TPM_2) return; acpi_tpm2_t *tpm2 = (acpi_tpm2_t *)header; @@ -304,7 +317,7 @@ static void acpi_ssdt_write_cbtable(void) acpigen_write_device("CTBL"); acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE); acpigen_write_name_integer("_UID", 0); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_resource_consumer_mmio(base, base + size - 1, @@ -1231,6 +1244,11 @@ static void acpi_create_iort(acpi_header_t *header, void *unused) header->length = current - (unsigned long)iort; } +__weak unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) +{ + return 0; +} + static void acpi_create_wdat(acpi_header_t *header, void *unused) { if (!CONFIG(ACPI_WDAT_WDT)) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index f682522bc86..9db849e611e 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -839,12 +839,9 @@ void acpigen_write_thermal_zone(const char *name) void acpigen_write_STA(uint8_t status) { /* - * Method (_STA, 0, NotSerialized) { Return (status) } + * Name (_STA, status) */ - acpigen_write_method("_STA", 0); - acpigen_emit_byte(RETURN_OP); - acpigen_write_byte(status); - acpigen_pop_len(); + acpigen_write_name_integer("_STA", status); } void acpigen_write_STA_ext(const char *namestring) diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 1f44d6abef6..73ef8de9d67 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -33,8 +33,8 @@ SECTIONS { BOOTBLOCK_TOP = .; .init (.) : { *(.init._start); - *(.init); - *(.init.*); + KEEP(*(.init)); + KEEP(*(.init.*)); } /* diff --git a/src/arch/x86/include/arch/fit_table.h b/src/arch/x86/include/arch/fit_table.h new file mode 100644 index 00000000000..22da62e8baf --- /dev/null +++ b/src/arch/x86/include/arch/fit_table.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _FIT_TABLE_H_ +#define _FIT_TABLE_H_ + +#include +#include + +#define FIT_POINTER_ADDRESS 0xffffffc0 + +#define FIT_ENTRY_HAS_CHECKSUM 0x80 + +/* + * From "Firmware Interface Table, BIOS Specification" (document #599500), Rev. 1.6, March 2025 + */ +#define FIT_ENTRY_TYPE_HEADER 0x00 // FIT Header Entry +#define FIT_ENTRY_TYPE_UCODE 0x01 // Microcode Update Entry +#define FIT_ENTRY_TYPE_SACM 0x02 // Startup AC Module Entry +#define FIT_ENTRY_TYPE_DACM 0x03 // Diagnostic AC Module Entry +#define FIT_ENTRY_TYPE_PBP 0x04 // Platform Boot Policy Entry +#define FIT_ENTRY_TYPE_MMF 0x05 // Memory Microcontroller Firmware Entry +#define FIT_ENTRY_TYPE_FRS 0x06 // FIT Reset State Entry +#define FIT_ENTRY_TYPE_BIOS_SACM 0x07 // BIOS Startup Module Entry +#define FIT_ENTRY_TYPE_TPM 0x08 // TPM Policy Record +#define FIT_ENTRY_TYPE_BIOS 0x09 // BIOS Policy Record +#define FIT_ENTRY_TYPE_TXT 0x0a // TXT Policy Record +#define FIT_ENTRY_TYPE_KM 0x0b // Key Manifest Record +#define FIT_ENTRY_TYPE_BPM 0x0c // Boot Policy Manifest +#define FIT_ENTRY_TYPE_FSP 0x0d // FSP Boot Manifest +// 0x0E - 0x0F Intel Reserved +#define FIT_ENTRY_TYPE_CSE 0x10 // CSE Secure Boot +// 0x11 - 0x19 Intel Reserved +#define FIT_ENTRY_TYPE_VAB_PT 0x1a // Vendor Authorized Boot Provisioning Table +#define FIT_ENTRY_TYPE_VAB_KM 0x1b // Vendor Authorized Boot Key Manifest +#define FIT_ENTRY_TYPE_VAB_IM 0x1c // Vendor Authorized Boot Image Manifest +#define FIT_ENTRY_TYPE_VAB_IH 0x1d // Vendor Authorized Boot Image Hash (Deprecated) +#define FIT_ENTRY_TYPE_VAB_ACPIM 0x1e // VAB Authorization Code Patch Image Manifest +// 0x1F - 0x2B Intel Reserved +#define FIT_ENTRY_TYPE_SACM_DBG 0x2c // SACM Debug Record +#define FIT_ENTRY_TYPE_FPDR 0x2d // Feature Policy Delivery Record. + // Deprecated in CBnT platforms. +#define FIT_ENTRY_TYPE_SCRTM_ERR 0x2e // Granular SCRTM Error Record +#define FIT_ENTRY_TYPE_JMP_DBG 0x2f // JMP $ Debug Policy +// 0x30 - 0x70 Reserved for Platform Manufacturer Use +// 0x71 - 0x7E Intel Reserved +#define FIT_ENTRY_TYPE_UNUSED 0x7f // Unused Entry (skip) + +struct fit_entry { + union { + uint8_t bytes[sizeof(uint64_t)]; + uint64_t u64; + } address; + uint32_t size_reserved; + uint16_t version; + uint8_t type_checksum_valid; + uint8_t checksum; +} __packed; + +static inline uint32_t fit_entry_size(const struct fit_entry *entry) +{ + return entry->size_reserved & 0xffffff; +} + +static inline uint8_t fit_entry_type(const struct fit_entry *entry) +{ + return entry->type_checksum_valid & 0x7f; +} + +static inline struct fit_entry *fit_table_search(uint8_t entry_type) +{ + struct fit_entry *fit = *(struct fit_entry **)(uintptr_t)FIT_POINTER_ADDRESS; + + union { + uint8_t bytes[sizeof(uint64_t)]; + uint64_t u64; + } signature = { .bytes = {'_', 'F', 'I', 'T', '_', ' ', ' ', ' '} }; + + /* A quick sanity check that we're in fact dealing with FIT. */ + if (fit->address.u64 != signature.u64) + return NULL; + + int entry_count = fit_entry_size(fit) * 16 / sizeof(struct fit_entry); + + for (int i = 0; i < entry_count; i++) { + if (fit_entry_type(&fit[i]) == entry_type) + return &fit[i]; + } + + return NULL; +} + +#endif /* _FIT_TABLE_H_ */ diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 97d5f242567..db83e420a5c 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -39,6 +39,8 @@ static int smbios_processor_name(u8 *start) } tmp[12] = 0; str = (const char *)tmp; + /* Skip leading spaces. */ + while (*str == ' ') str++; } } return smbios_add_string(start, str); @@ -162,7 +164,8 @@ int smbios_write_type4(unsigned long *current, int handle) t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number()); t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED; t->processor_upgrade = get_socket_type(); - if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) { + if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16 && + cpuid_eax(0x16) != 0 && cpuid_ecx(0x16) != 0) { t->current_speed = cpuid_eax(0x16); /* base frequency */ t->external_clock = cpuid_ecx(0x16); } else { @@ -237,7 +240,20 @@ int smbios_write_type7_cache_parameters(unsigned long *current, const u8 level = info.level; const size_t assoc = info.num_ways; const size_t cache_share = info.num_cores_shared; - const size_t cache_size = info.size * get_number_of_caches(cache_share); + + /* + * In the case of unified L3 cache, the info_size is already the correct + * total size. Multiplying by number of cores is unnecessary and might result + * in the cache displaying as zero. + */ + size_t tmp_cache_size; + if (level < 3) { + tmp_cache_size = info.size * get_number_of_caches(cache_share); + } + else { + tmp_cache_size = info.size; + } + const size_t cache_size = tmp_cache_size; if (!cache_type) /* No more caches in the system */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index b88a0831b95..4eb8097a19e 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -90,6 +90,7 @@ #define CBMEM_ID_CSE_INFO 0x4553435F #define CBMEM_ID_CSE_BP_INFO 0x42455343 #define CBMEM_ID_AMD_OPENSIL 0x4153494C +#define CBMEM_ID_TIANOCORE_LOGO 0x42475254 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -172,5 +173,7 @@ { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"},\ { CBMEM_ID_CSE_INFO, "CSE SPECIFIC INFO"},\ { CBMEM_ID_CSE_BP_INFO, "CSE BP INFO"}, \ - { CBMEM_ID_AMD_OPENSIL, "OPENSIL DATA"} + { CBMEM_ID_AMD_OPENSIL, "OPENSIL DATA"}, \ + { CBMEM_ID_TIANOCORE_LOGO, "UEFI LOGO "} + #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index def48b77979..6740781603d 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -90,6 +90,7 @@ enum { LB_TAG_EFI_FW_INFO = 0x0045, LB_TAG_CAPSULE = 0x0046, LB_TAG_CFR_ROOT = 0x0047, + LB_TAG_LOGO = 0x00a0, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -606,4 +607,12 @@ struct lb_cfr { /* struct lb_cfr_option_form forms[] */ }; +/* + * Bootlogo header for TianoCore boot logo + * * size Contains the size of the BMP file + */ +struct bootlogo_header { + uint64_t size; +} __packed; + #endif diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 2770f648b49..ab4a472a7df 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -194,3 +194,9 @@ config CPU_UCODE_BINARIES microcode binary files to include, separated by spaces. If unsure, leave this blank. + +config CPU_MAX_TEMPERATURE + int + default 100 + help + The maximum CPU temperature, aka TjMax. Processor-specific. diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index d7c23daf105..984bd0ff2cc 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -43,8 +43,9 @@ static void model_16_init(struct device *dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - lock_smm(); + /* Write protect SMM space with SMMLOCK, or let SMI handler do it if any. */ + if (!CONFIG(HAVE_SMI_HANDLER)) + lock_smm(); amd_update_microcode_from_cbfs(); diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 2336d68f968..17d2526e90b 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -10,7 +10,11 @@ config CPU_AMD_PI select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select NO_SMM + select SMM_TSEG + select PARALLEL_MP_AP_WORK + select SOC_AMD_COMMON_BLOCK_SMM + select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_ACPI select SSE2 if CPU_AMD_PI @@ -31,10 +35,20 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x4000 +config SMM_MODULE_STACK_SIZE + default 0x800 + +config SMM_TSEG_SIZE + default 0x100000 if HAVE_SMI_HANDLER + default 0x0 + endif # CPU_AMD_PI source "src/cpu/amd/pi/00730F01/Kconfig" diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk index f405c577445..0661984f155 100644 --- a/src/cpu/intel/fit/Makefile.mk +++ b/src/cpu/intel/fit/Makefile.mk @@ -13,6 +13,10 @@ intel_fit-file := fit_table.c:struct intel_fit-type := intel_fit intel_fit-align := 16 +ifneq ($(CONFIG_INTEL_FIT_LOC),) +intel_fit-COREBOOT-position := $(CONFIG_INTEL_FIT_LOC) +endif + $(call add_intermediate, set_fit_ptr, $(IFITTOOL)) @printf " UPDATE-FIT set FIT pointer to table\n" $(IFITTOOL) -f $< -F -n intel_fit -r COREBOOT -c diff --git a/src/cpu/intel/fit/fit_table.c b/src/cpu/intel/fit/fit_table.c index 62d624f5b00..b378295112f 100644 --- a/src/cpu/intel/fit/fit_table.c +++ b/src/cpu/intel/fit/fit_table.c @@ -1,21 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include - -struct fit_entry { - uint8_t address[sizeof(uint64_t)]; - uint32_t size_reserved; - uint16_t version; - uint8_t type_checksum_valid; - uint8_t checksum; -} __packed; +#include __attribute((used)) static struct fit_entry fit_table[CONFIG_CPU_INTEL_NUM_FIT_ENTRIES + 1] = { [0] = { - .address = {'_', 'F', 'I', 'T', '_', ' ', ' ', ' '}, + .address.bytes = {'_', 'F', 'I', 'T', '_', ' ', ' ', ' '}, .size_reserved = 1, .version = 0x100, - .type_checksum_valid = 0x80, + .type_checksum_valid = FIT_ENTRY_HAS_CHECKSUM | FIT_ENTRY_TYPE_HEADER, .checksum = 0x7d, } }; diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 86dcbea1772..a08cc9a9eed 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -451,13 +452,16 @@ static void configure_thermal_target(struct device *dev) /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ struct cpu_intel_haswell_config *conf = dev->upstream->dev->chip_info; msr_t msr; + uint32_t tcc_offset; + + tcc_offset = get_cpu_throttling_offset(conf->tcc_offset); /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; + msr.lo |= (tcc_offset & 0xf) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } } diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 28705230a2a..7e05a4cc1a3 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -48,6 +48,11 @@ .global update_bsp_microcode update_bsp_microcode: +#if CONFIG_CPU_MICROCODE_CBFS_LOC != 0 && CONFIG_CPU_MICROCODE_CBFS_LEN != 0 + movl $(CONFIG_CPU_MICROCODE_CBFS_LOC), %esi + movl $(CONFIG_CPU_MICROCODE_CBFS_LEN), %edi + addl %esi, %edi +#else /* Keep return address */ movl %esp, %edx /* find microcodes in cbfs */ @@ -69,6 +74,7 @@ update_bsp_microcode: movl CBFS_FILE_LEN(%eax), %edi bswap %edi addl %esi, %edi +#endif /* * Microcode revision -> %ebx diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index cb748543468..cf76b33851d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -24,13 +25,16 @@ static void configure_thermal_target(struct device *dev) { struct cpu_intel_model_2065x_config *conf = dev->upstream->dev->chip_info; msr_t msr; + uint32_t tcc_offset; + + tcc_offset = get_cpu_throttling_offset(conf->tcc_offset); /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; + msr.lo |= (tcc_offset & 0xf) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 23310a303b4..ef9d752b5e6 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -331,6 +332,9 @@ static void configure_thermal_target(struct device *dev) { struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info; msr_t msr; + uint32_t tcc_offset; + + tcc_offset = get_cpu_throttling_offset(conf->tcc_offset); if (boot_cpu()) { /* @@ -340,10 +344,10 @@ static void configure_thermal_target(struct device *dev) /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; + msr.lo |= (tcc_offset & 0xf) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } } diff --git a/src/cpu/x86/lapic/Makefile.mk b/src/cpu/x86/lapic/Makefile.mk index dd484ee6f66..24865c317b7 100644 --- a/src/cpu/x86/lapic/Makefile.mk +++ b/src/cpu/x86/lapic/Makefile.mk @@ -6,6 +6,8 @@ bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +# Use TSC for SMM, should be safer than LAPIC after OS takes over +smm-$(CONFIG_UDELAY_LAPIC) += ../tsc/delay_tsc.c all_x86-y += boot_cpu.c all_x86-y += lapic.c diff --git a/src/cpu/x86/lapic/lapic_cpu_stop.c b/src/cpu/x86/lapic/lapic_cpu_stop.c index 6eacba6c21c..359a57dec90 100644 --- a/src/cpu/x86/lapic/lapic_cpu_stop.c +++ b/src/cpu/x86/lapic/lapic_cpu_stop.c @@ -55,6 +55,13 @@ void stop_this_cpu(void) printk(BIOS_DEBUG, "CPU %ld going down...\n", id); + /* + * Increment the parked AP count after the printf (which has a spinlock that + * may delay the parking if console debugging is enabled), but before + * sending INIT to self, after which code may not be executed. + */ + atomic_inc(&parked_ap_count); + /* send an LAPIC INIT to myself */ lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT); wait_for_ipi_completion_without_printk(timeout_100ms); diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 47b3a9ef848..b19a8a8a45a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -36,6 +36,7 @@ struct mp_callback { }; static char processor_name[49]; +atomic_t parked_ap_count; /* * A mp_flight_record details a sequence of calls for the APs to perform @@ -500,6 +501,8 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap return CB_ERR; } + atomic_set(&parked_ap_count, 0); + return CB_SUCCESS; } @@ -1052,11 +1055,24 @@ enum cb_err mp_park_aps(void) enum cb_err ret; long duration_msecs; - stopwatch_init(&sw); + atomic_set(&parked_ap_count, 0); ret = mp_run_on_aps(park_this_cpu, NULL, MP_RUN_ON_ALL_CPUS, 1000 * USECS_PER_MSEC); + stopwatch_init_msecs_expire(&sw, 500); + + while (atomic_read(&parked_ap_count) < global_num_aps) { + if (stopwatch_expired(&sw)) { + printk(BIOS_DEBUG, "%s failed, %d / %d CPUs parked after 500 msecs\n", + __func__, atomic_read(&parked_ap_count), global_num_aps); + return CB_ERR; + + } + + udelay(10); + } + duration_msecs = stopwatch_duration_msecs(&sw); if (ret == CB_SUCCESS) @@ -1177,3 +1193,46 @@ enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) return ret; } + + +/* AP restart code */ + +static struct mp_flight_record ap_restart_steps[] = { + /* Wait for APs to finish then optionally start looking for work. */ + MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL), +}; + +enum cb_err restart_aps(void) +{ + struct mp_params mp_params; + atomic_t *ap_count; + + if (!CONFIG(PARALLEL_MP_AP_WORK)) + return CB_ERR_NOT_IMPLEMENTED; + + mp_params.num_cpus = mp_state.cpu_count; + mp_params.num_records = ARRAY_SIZE(ap_restart_steps); + mp_params.flight_plan = &ap_restart_steps[0]; + + mp_info.num_records = ARRAY_SIZE(ap_restart_steps); + mp_info.records = &ap_restart_steps[0]; + + /* Load the SIPI vector. */ + ap_count = load_sipi_vector(&mp_params); + if (ap_count == NULL) + return CB_ERR; + + /* Make sure SIPI data hits RAM so the APs that come up will see + * the startup code even if the caches are disabled. */ + wbinvd(); + + if (start_aps(NULL, global_num_aps, ap_count) != CB_SUCCESS) { + mdelay(1000); + printk(BIOS_DEBUG, "%d/%d eventually checked in?\n", + atomic_read(ap_count), global_num_aps); + return CB_ERR; + } + + /* Walk the flight plan for the BSP. */ + return bsp_do_flight_plan(&mp_params); +} diff --git a/src/cpu/x86/topology.c b/src/cpu/x86/topology.c index b2fd202ed52..70bdf47c4a3 100644 --- a/src/cpu/x86/topology.c +++ b/src/cpu/x86/topology.c @@ -110,12 +110,14 @@ void set_cpu_topology(struct device *cpu) static struct bitfield_descriptor topology[LEVEL_TYPE_MAX]; static enum cb_err ret; static bool done; + unsigned int core_id_within_package; struct { unsigned int level; unsigned int *field; } apic_fields[] = { { LEVEL_TYPE_SMT, &cpu->path.apic.thread_id }, { LEVEL_TYPE_CORE, &cpu->path.apic.core_id }, + { LEVEL_TYPE_MODULE, &cpu->path.apic.module_id }, { LEVEL_TYPE_PACKAGE, &cpu->path.apic.package_id }, { LEVEL_TYPE_PACKAGE, &cpu->path.apic.node_id } }; @@ -150,4 +152,8 @@ void set_cpu_topology(struct device *cpu) *apic_fields[i].field = value; } } + + core_id_within_package = apicid & ((1 << topology[LEVEL_TYPE_PACKAGE].first_bit) - 1); + core_id_within_package >>= topology[LEVEL_TYPE_CORE].first_bit; + cpu->path.apic.core_id_within_package = core_id_within_package; } diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 4253b18dab2..746e7876e52 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -30,7 +30,7 @@ void udelay(unsigned int us) } } -#if CONFIG(TSC_MONOTONIC_TIMER) +#if CONFIG(TSC_MONOTONIC_TIMER) || (CONFIG(LAPIC_MONOTONIC_TIMER) && ENV_SMM) #include static struct monotonic_counter { diff --git a/src/device/pci_device.c b/src/device/pci_device.c index d03d88df399..5b0531d7050 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -372,14 +373,15 @@ static uint64_t get_rebar_sizes_mask(const struct device *dev, static void pci_store_rebar_size(const struct device *dev, const struct resource *resource) { - const unsigned int num_bits = __fls64(resource->size); + /* The ReBAR size value in the register is in MiB */ + const unsigned int num_bits = __fls64(resource->size / MiB); const uint32_t offset = get_rebar_offset(dev, resource->index); if (!offset) return; pci_update_config32(dev, offset + PCI_REBAR_CTRL_OFFSET, - ~PCI_REBAR_CTRL_SIZE_MASK, - num_bits << PCI_REBAR_CTRL_SIZE_SHIFT); + PCI_REBAR_CTRL_BAR_SIZE_MASK, + num_bits << PCI_REBAR_CTRL_BAR_SIZE_SHIFT); } static void configure_adjustable_base(const struct device *dev, @@ -455,7 +457,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) resource = pci_get_resource(dev, index); const bool is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE) != 0; - if (CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS) && is_pcie) + if (is_pcie && dasharo_resizeable_bars_enabled()) configure_adjustable_base(dev, index, resource); index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; @@ -698,7 +700,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource) if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { if (CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS) && - (resource->flags & IORESOURCE_PCIE_RESIZABLE_BAR)) + (resource->flags & IORESOURCE_PCIE_RESIZABLE_BAR) && + dasharo_resizeable_bars_enabled()) pci_store_rebar_size(dev, resource); pci_store_resource(dev, resource); diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 8686e38a868..6b9010fb9c8 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -718,21 +719,24 @@ static void pciexp_tune_dev(struct device *dev) if (!root_cap) return; - /* Check for and enable Common Clock */ - if (CONFIG(PCIEXP_COMMON_CLOCK)) - pciexp_enable_common_clock(root, root_cap, dev, cap); + if (!CONFIG(VENDOR_PCENGINES) || CONFIG(BOARD_PCENGINES_APU5) || + dasharo_apu_pcie_pm_enabled()) { + /* Check for and enable Common Clock */ + if (CONFIG(PCIEXP_COMMON_CLOCK)) + pciexp_enable_common_clock(root, root_cap, dev, cap); - /* Check if per port CLK req is supported by endpoint*/ - if (CONFIG(PCIEXP_CLK_PM)) - pciexp_enable_clock_power_pm(dev, cap); + /* Check if per port CLK req is supported by endpoint*/ + if (CONFIG(PCIEXP_CLK_PM)) + pciexp_enable_clock_power_pm(dev, cap); - /* Enable L1 Sub-State when both root port and endpoint support */ - if (CONFIG(PCIEXP_L1_SUB_STATE)) - pciexp_config_L1_sub_state(root, dev); + /* Enable L1 Sub-State when both root port and endpoint support */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pciexp_config_L1_sub_state(root, dev); - /* Check for and enable ASPM */ - if (CONFIG(PCIEXP_ASPM)) - pciexp_enable_aspm(root, root_cap, dev, cap); + /* Check for and enable ASPM */ + if (CONFIG(PCIEXP_ASPM)) + pciexp_enable_aspm(root, root_cap, dev, cap); + } /* Clear PCIe Lane Error Status */ if (CONFIG(PCIEXP_LANE_ERR_STAT_CLEAR)) diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 44782d87a1e..626a613ca16 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -91,6 +91,10 @@ static resource_t effective_limit(const struct resource *const res) if (res->flags & IORESOURCE_BRIDGE) return res->limit; + /* If the resource is bigger than 4G or resource 64bit, force 64bit limit */ + if (res->size > UINT32_MAX || res->flags & IORESOURCE_PCI64) + return UINT64_MAX; + const resource_t quirk_4g_limit = res->flags & IORESOURCE_ABOVE_4G ? UINT64_MAX : UINT32_MAX; return MIN(res->limit, quirk_4g_limit); diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index df45125f010..6b2287bb690 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -105,6 +105,12 @@ static void crb_tpm_fill_ssdt(const struct device *dev) acpigen_pop_len(); /* Device */ } +static void crb_tpm_read_resources(struct device *dev) +{ + /* Static 5K memory region specified in Kconfig */ + mmio_range(dev, 0, TPM_CRB_BASE_ADDRESS, 0x5000); +} + static const char *crb_tpm_acpi_name(const struct device *dev) { return "TPM"; @@ -194,7 +200,7 @@ static int smbios_write_type43_tpm(struct device *dev, int *handle, unsigned lon #endif static struct device_operations __maybe_unused crb_ops = { - .read_resources = noop_read_resources, + .read_resources = crb_tpm_read_resources, .set_resources = noop_set_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = crb_tpm_acpi_name, diff --git a/src/drivers/efi/Kconfig b/src/drivers/efi/Kconfig index 07e5f146a61..4c8189bc65b 100644 --- a/src/drivers/efi/Kconfig +++ b/src/drivers/efi/Kconfig @@ -42,6 +42,8 @@ config DRIVERS_EFI_MAIN_FW_LSV config DRIVERS_EFI_UPDATE_CAPSULES bool "Include EFI update capsules driver" depends on DRIVERS_EFI_VARIABLE_STORE && SMMSTORE_V2 && DRIVERS_EFI_FW_INFO + select FAST_SPI_FULL_RO_BOOTMEDIA if SOC_INTEL_COMMON_BLOCK + select DASHARO_FIRMWARE_UPDATE_MODE help Adds a driver that is able to parse CapsuleUpdateData* EFI variables to discover firmware updates and expose them for tianocore thorough diff --git a/src/drivers/efi/capsules.c b/src/drivers/efi/capsules.c index e674e33228c..352c798ea63 100644 --- a/src/drivers/efi/capsules.c +++ b/src/drivers/efi/capsules.c @@ -7,12 +7,14 @@ #include #include #include +#include #include #include #include +#include +#include #include #include -#include #include #include @@ -344,7 +346,15 @@ static struct block_descr check_capsule_block(struct block_descr first_block, goto error; } - data_size += ALIGN_UP(capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT); + uint64_t capsule_size = + ALIGN_UP((uint64_t)capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT); + if (data_size + capsule_size < data_size) { /* overflow detection */ + printk(BIOS_ERR, + "capsules: capsules block size is too large (%#llx + %#llx) for uint64.\n", + data_size, capsule_size); + goto error; + } + data_size += capsule_size; uint32_t size_left = capsule_hdr->CapsuleImageSize; while (size_left != 0) { @@ -384,6 +394,12 @@ static struct block_descr check_capsule_block(struct block_descr first_block, } /* Increase the size only on successful parsing of the capsule block. */ + if (*total_data_size + data_size < *total_data_size) { /* overflow detection */ + printk(BIOS_ERR, + "capsules: total capsule's size is too large (%#llx + %#llx) for uint64.\n", + *total_data_size, data_size); + goto error; + } *total_data_size += data_size; return block; @@ -582,6 +598,7 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target) { struct block_descr block = block_chain; uint8_t *capsule_start = NULL; + uint32_t capsule_size = 0; uint32_t size_left = 0; /* No safety checks in this function, as all of them were done earlier. */ @@ -596,8 +613,10 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target) if (size_left == 0) { const EFI_CAPSULE_HEADER *capsule_hdr = map_range(block.addr, sizeof(*capsule_hdr)); - size_left = capsule_hdr->CapsuleImageSize; + capsule_size = capsule_hdr->CapsuleImageSize; capsule_start = target; + + size_left = capsule_size; } uint64_t addr = block.addr; @@ -627,25 +646,30 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target) } uefi_capsules[uefi_capsule_count].base = (uintptr_t)capsule_start; - uefi_capsules[uefi_capsule_count].len = block.len; + uefi_capsules[uefi_capsule_count].len = capsule_size; uefi_capsule_count++; /* This is to align start of the next capsule (assumes that initial value of target was suitably aligned). */ - if (!IS_ALIGNED(block.len, CAPSULE_ALIGNMENT)) - target += ALIGN_UP(block.len, CAPSULE_ALIGNMENT) - block.len; + if (!IS_ALIGNED(capsule_size, CAPSULE_ALIGNMENT)) + target += ALIGN_UP(capsule_size, CAPSULE_ALIGNMENT) - + capsule_size; } } printk(BIOS_INFO, "capsules: found %d capsule(s).\n", uefi_capsule_count); } -void efi_parse_capsules(void) +void efi_parse_capsules(uintptr_t *base, size_t *size) { /* EDK2 starts with 20 items and then grows the list, but it's unlikely to be necessary in practice. */ enum { MAX_CAPSULE_BLOCKS = MAX_CAPSULES }; + /* Assume no capsules at the start. */ + *base = 0; + *size = 0; + struct region_device rdev; if (smmstore_lookup_region(&rdev)) { printk(BIOS_INFO, "capsules: no SMMSTORE region, no update capsules.\n"); @@ -711,12 +735,16 @@ void efi_parse_capsules(void) printk(BIOS_ERR, "capsules: failed to find a buffer (%#llx bytes) for coalesced UEFI capsules.\n", total_data_size); - } else { - printk(BIOS_DEBUG, "capsules: coalescing capsules data @ %#010x.\n", - coalesce_buffer.base); - coalesce_capsules(block_chain, (void *)(uintptr_t)coalesce_buffer.base); + goto exit; } + printk(BIOS_DEBUG, "capsules: coalescing capsules data @ %#010x-%#010x.\n", + coalesce_buffer.base, coalesce_buffer.base + coalesce_buffer.len); + coalesce_capsules(block_chain, (void *)(uintptr_t)coalesce_buffer.base); + + *base = coalesce_buffer.base; + *size = coalesce_buffer.len; + exit: paging_disable_pae(); memranges_teardown(&memory_map); @@ -761,10 +789,38 @@ void efi_add_capsules_to_bootmem(void) static void parse_capsules(void *unused) { + uintptr_t capsules_base; + size_t capsules_size; + if (!acpi_is_wakeup_s3()) - efi_parse_capsules(); + efi_parse_capsules(&capsules_base, &capsules_size); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, parse_capsules, NULL); #endif + +static void enable_capsule_smi(void *unused) +{ + uint32_t ret; + + /* SMI can occasionally be ignored, so retry several times on failure. */ + uint8_t retries_left = 10; + while (1) { + ret = call_smm(APM_CNT_SMMSTORE, SMMSTORE_CMD_USE_FULL_FLASH, + (void *)(uintptr_t)uefi_capsule_count); + if (ret == SMMSTORE_RET_SUCCESS) + break; + + if (retries_left-- == 0) + break; + + /* Add a tiny delay before making another try. */ + udelay(100); + } + + printk(BIOS_INFO, "%sabled capsule update SMI handler\n", + ret == SMMSTORE_RET_SUCCESS ? "En" : "Dis"); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, enable_capsule_smi, NULL); diff --git a/src/drivers/efi/capsules.h b/src/drivers/efi/capsules.h index 608ce3400f6..4f996491bb1 100644 --- a/src/drivers/efi/capsules.h +++ b/src/drivers/efi/capsules.h @@ -3,15 +3,22 @@ #ifndef _EDK2_CAPSULES_H_ #define _EDK2_CAPSULES_H_ +#include +#include + #if CONFIG(DRIVERS_EFI_UPDATE_CAPSULES) -void efi_parse_capsules(void); +void efi_parse_capsules(uintptr_t *base, size_t *size); void efi_add_capsules_to_bootmem(void); #else -static inline void efi_parse_capsules(void) { } +static inline void efi_parse_capsules(uintptr_t *base, size_t *size) +{ + *base = 0; + *size = 0; +} static inline void efi_add_capsules_to_bootmem(void) { } diff --git a/src/drivers/efi/efivars.c b/src/drivers/efi/efivars.c index 2591eab7307..56b517ada7f 100644 --- a/src/drivers/efi/efivars.c +++ b/src/drivers/efi/efivars.c @@ -3,14 +3,13 @@ #include #include #include +#include #include #include #include #include -#include "efivars.h" - #define PREFIX "EFIVARS: " static const EFI_GUID EfiVariableGuid = { @@ -408,12 +407,13 @@ enum cb_err efi_fv_print_options(struct region_device *rdev) { enum cb_err ret; bool auth_format; + struct region_device store_rdev = *rdev; - ret = efi_fv_init(rdev, &auth_format); + ret = efi_fv_init(&store_rdev, &auth_format); if (ret != CB_SUCCESS) return ret; - return walk_variables(rdev, auth_format, print_var, NULL); + return walk_variables(&store_rdev, auth_format, print_var, NULL); } /* @@ -431,8 +431,9 @@ enum cb_err efi_fv_get_option(struct region_device *rdev, struct efi_find_args args; bool auth_format; enum cb_err ret; + struct region_device store_rdev = *rdev; - ret = efi_fv_init(rdev, &auth_format); + ret = efi_fv_init(&store_rdev, &auth_format); if (ret != CB_SUCCESS) return ret; @@ -441,7 +442,7 @@ enum cb_err efi_fv_get_option(struct region_device *rdev, args.size = size; args.data = dest; - return walk_variables(rdev, auth_format, find_and_copy, &args); + return walk_variables(&store_rdev, auth_format, find_and_copy, &args); } static enum cb_err write_auth_hdr(struct region_device *rdev, const EFI_GUID *guid, @@ -584,13 +585,14 @@ enum cb_err efi_fv_set_option(struct region_device *rdev, uint32_t size) { struct region_device rdev_old; + struct region_device store_rdev = *rdev; struct efi_find_compare_args args; bool found_existing; VARIABLE_HEADER hdr; bool auth_format; enum cb_err ret; - ret = efi_fv_init(rdev, &auth_format); + ret = efi_fv_init(&store_rdev, &auth_format); if (ret != CB_SUCCESS) return ret; @@ -601,7 +603,7 @@ enum cb_err efi_fv_set_option(struct region_device *rdev, args.match = false; args.data = data; - ret = walk_variables(rdev, auth_format, find_and_compare, &args); + ret = walk_variables(&store_rdev, auth_format, find_and_compare, &args); found_existing = ret == CB_SUCCESS; if (found_existing) { @@ -610,17 +612,17 @@ enum cb_err efi_fv_set_option(struct region_device *rdev, if (args.match) return CB_SUCCESS; - rdev_old = *rdev; + rdev_old = store_rdev; /* Mark as to be deleted */ hdr.State = VAR_IN_DELETED_TRANSITION; - if (rdev_writeat(rdev, &hdr.State, offsetof(VARIABLE_HEADER, State), + if (rdev_writeat(&store_rdev, &hdr.State, offsetof(VARIABLE_HEADER, State), sizeof(hdr.State)) != sizeof(hdr.State)) return CB_EFI_ACCESS_ERROR; } /* Walk to end of variable store */ - ret = walk_variables(rdev, auth_format, noop, NULL); + ret = walk_variables(&store_rdev, auth_format, noop, NULL); if (ret != CB_EFI_OPTION_NOT_FOUND) return ret; @@ -632,9 +634,9 @@ enum cb_err efi_fv_set_option(struct region_device *rdev, */ if (auth_format) - ret = write_auth_hdr(rdev, guid, name, data, size); + ret = write_auth_hdr(&store_rdev, guid, name, data, size); else - ret = write_hdr(rdev, guid, name, data, size); + ret = write_hdr(&store_rdev, guid, name, data, size); if (ret != CB_SUCCESS) return ret; diff --git a/src/drivers/efi/efivars.h b/src/drivers/efi/efivars.h index b3443b33b35..a7932d1dc1b 100644 --- a/src/drivers/efi/efivars.h +++ b/src/drivers/efi/efivars.h @@ -6,6 +6,12 @@ #include #include +/* + * efi/efi_datatype.h must be included before other EFI headers because it + * provides entities that EDK's headers define when they are absent, leading to + * conflicting definitions for some orderings of includes. + */ +#include #include /** diff --git a/src/drivers/efi/option.c b/src/drivers/efi/option.c index d634c963545..cc147d26697 100644 --- a/src/drivers/efi/option.c +++ b/src/drivers/efi/option.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include - #include "efivars.h" static const EFI_GUID EficorebootNvDataGuid = { diff --git a/src/drivers/generic/bayhub_lv2/lv2.h b/src/drivers/generic/bayhub_lv2/lv2.h index 9eef4b3fc39..cb2ddb83e64 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.h +++ b/src/drivers/generic/bayhub_lv2/lv2.h @@ -22,7 +22,7 @@ enum { LV2_PCR_HEX_234 = 0x234, LV2_MAX_LATENCY_SETTING = 0x10011001, LV2_PCR_HEX_3F4 = 0x3F4, - LV2_L1_SUBSTATE_OPTIMISE = 0x0000000A, + LV2_L1_SUBSTATE_OPTIMISE = 0x0000000F, LV2_L1_SUBSTATE_OPTIMISE_MASK = 0xFFFFFFF0, LV2_PCR_HEX_300 = 0x300, LV2_TUNING_WINDOW = 0x00006055, diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c index 6ff010cb413..3b6e9ce63a4 100644 --- a/src/drivers/generic/cbfs-serial/cbfs-serial.c +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -20,6 +21,9 @@ const char *smbios_mainboard_serial_number(void) return serial_number; } + if (get_serial_number_from_efivar(serial_number)) + return serial_number; + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, MAX_SERIAL_LENGTH); diff --git a/src/drivers/generic/cbfs-uuid/cbfs-uuid.c b/src/drivers/generic/cbfs-uuid/cbfs-uuid.c index e657bdd922b..e438aa4015c 100644 --- a/src/drivers/generic/cbfs-uuid/cbfs-uuid.c +++ b/src/drivers/generic/cbfs-uuid/cbfs-uuid.c @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include +#include #include #include #include @@ -17,7 +20,12 @@ void smbios_system_set_uuid(u8 *uuid) if (uuid_len >= UUID_STRLEN && uuid_len <= UUID_STRLEN + 3) { /* Cut off any trailing whitespace like CR or LF */ uuid_str[UUID_STRLEN] = '\0'; - if (!parse_uuid(system_uuid, uuid_str)) + if (!parse_uuid(system_uuid, uuid_str)) { memcpy(uuid, system_uuid, UUID_LEN); + return; + } } + + if (get_uuid_from_efivar(system_uuid)) + memcpy(uuid, system_uuid, UUID_LEN); } diff --git a/src/drivers/gfx/nvidia/optimus/Kconfig b/src/drivers/gfx/nvidia/optimus/Kconfig new file mode 100644 index 00000000000..5b520f67dd8 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/Kconfig @@ -0,0 +1,8 @@ +config DRIVER_NVIDIA_OPTIMUS + bool + default n + depends on HAVE_ACPI_TABLES + select PMC_IPC_ACPI_INTERFACE + help + NVIDIA Optimus driver for ULT platforms with a PMC IPC ACPI interface. + and graphics cards supporting Runtime D3 power management diff --git a/src/drivers/gfx/nvidia/optimus/Makefile.mk b/src/drivers/gfx/nvidia/optimus/Makefile.mk new file mode 100644 index 00000000000..f29943943d7 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVER_NVIDIA_OPTIMUS) += optimus.c diff --git a/src/drivers/gfx/nvidia/optimus/chip.h b/src/drivers/gfx/nvidia/optimus/chip.h new file mode 100644 index 00000000000..b0eb4c6f189 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/chip.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_GFX_NVIDIA_OPTIMUS_CHIP_H__ +#define __DRIVERS_GFX_NVIDIA_OPTIMUS_CHIP_H__ + +#include + +/* Device support at least one of enable/reset GPIO. */ +struct drivers_gfx_nvidia_optimus_config { + const char *desc; + + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + + /* GPIO used to take device out of reset or to put it into reset. */ + struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + + /* + * SRCCLK assigned to this root port which will be turned off via PMC IPC. + * If set to -1 then the clock will not be disabled in D3. + */ + int srcclk_pin; + + /* + * Disable the ACPI-driven L23 Ready-to-Detect transition for the root port. + * maybe unneeded for optimus? + */ + bool disable_l23; + + /* + * EC method to call on dGPU power state change + */ + const char *ec_notify_method; +}; + +#endif diff --git a/src/drivers/gfx/nvidia/optimus/optimus.c b/src/drivers/gfx/nvidia/optimus/optimus.c new file mode 100644 index 00000000000..cc7b4da85c9 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/optimus.c @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* PCIe Root Port registers for link status and L23 control. */ +#define PCH_PCIE_CFG_SSID 0x40 /* Subsystem ID */ +#define PCH_PCIE_CFG_LSTS 0x52 /* Link Status Register */ +#define PCH_PCIE_CFG_SPR 0xe0 /* Scratchpad */ +#define PCH_PCIE_CFG_RPPGEN 0xe2 /* Root Port Power Gating Enable */ +#define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ + +/* ACPI register names corresponding to PCIe root port registers. */ +#define ACPI_REG_PCI_LINK_ACTIVE "LASX" /* Link active status */ +#define ACPI_REG_PCI_L23_RDY_ENTRY "L23E" /* L23_Rdy Entry Request */ +#define ACPI_REG_PCI_L23_RDY_DETECT "L23R" /* L23_Rdy Detect Transition */ +#define ACPI_REG_PCI_L23_SAVE_STATE "NCB7" /* Scratch bit to save L23 state */ + +/* ACPI register names corresponding to GPU port registers */ +#define ACPI_REG_PCI_SUBSYSTEM_ID "DVID" /* Subsystem DID+VID */ + +/* Called from _ON to get PCIe link back to active state. */ +static void nvidia_optimus_acpi_l23_exit(void) +{ + /* Skip if port is not in L2/L3. */ + acpigen_write_if_lequal_namestr_int(ACPI_REG_PCI_L23_SAVE_STATE, 1); + + /* Initiate L2/L3 Ready To Detect transition. */ + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_DETECT); + + /* Wait for transition to detect. */ + acpigen_write_delay_until_namestr_int(320, ACPI_REG_PCI_L23_RDY_DETECT, 0); + + acpigen_write_store_int_to_namestr(0, ACPI_REG_PCI_L23_SAVE_STATE); + + /* Once in detect, wait for link active. */ + acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_LINK_ACTIVE, 1); + + acpigen_pop_len(); /* If */ +} + +/* Called from _OFF to put PCIe link into L2/L3 state. */ +static void nvidia_optimus_acpi_l23_entry(void) +{ + /* Initiate L2/L3 Entry request. */ + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_ENTRY); + + /* Wait for L2/L3 Entry request to clear. */ + acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_L23_RDY_ENTRY, 0); + + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); +} + +/* Restore the subsystem ID after _ON to ensure the windows driver works */ +static void nvidia_optimus_acpi_subsystem_id_restore(const struct device *dev) +{ + uint32_t did, vid, dvid; + + if (CONFIG_SUBSYSTEM_VENDOR_ID) + vid = CONFIG_SUBSYSTEM_VENDOR_ID; + else if (dev->subsystem_vendor) + vid = dev->subsystem_vendor; + else + vid = 0x0000; + + if (CONFIG_SUBSYSTEM_DEVICE_ID) + did = CONFIG_SUBSYSTEM_DEVICE_ID; + else if (dev->subsystem_device) + did = dev->subsystem_device; + else + did = 0x0000; + + dvid = did << 16 | vid; + acpigen_write_store_int_to_namestr(dvid, ACPI_REG_PCI_SUBSYSTEM_ID); +} + +static void +nvidia_optimus_acpi_method_on(unsigned int pcie_rp, + const struct device *dev) +{ + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + acpigen_write_method_serialized("_ON", 0); + acpigen_write_if_lequal_namestr_int("_STA", 0x5); + + /* Assert enable GPIO to turn on device power. */ + if (config->enable_gpio.pin_count) { + acpigen_enable_tx_gpio(&config->enable_gpio); + if (config->enable_delay_ms) + acpigen_write_sleep(config->enable_delay_ms); + } + + /* Enable SRCCLK for root port if pin is defined. */ + if (config->srcclk_pin >= 0) + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); + + /* De-assert reset GPIO to bring device out of reset. */ + if (config->reset_gpio.pin_count) { + acpigen_disable_tx_gpio(&config->reset_gpio); + if (config->reset_delay_ms) + acpigen_write_sleep(config->reset_delay_ms); + } + + /* Trigger L23 ready exit flow unless disabled by config. */ + if (!config->disable_l23) + nvidia_optimus_acpi_l23_exit(); + + /* Notify EC to start polling the dGPU */ + if (config->ec_notify_method) { + acpigen_emit_namestring(config->ec_notify_method); + acpigen_write_integer(1); + } + + acpigen_pop_len(); /* If */ + + nvidia_optimus_acpi_subsystem_id_restore(dev); + acpigen_write_store_int_to_namestr(0xF, "_STA"); + acpigen_pop_len(); /* Method */ +} + +static void +nvidia_optimus_acpi_method_off(unsigned int pcie_rp, + const struct device *dev) +{ + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + acpigen_write_method_serialized("_OFF", 0); + acpigen_write_if_lequal_namestr_int("_STA", 0xF); + + /* Notify EC to stop polling the dGPU */ + if (config->ec_notify_method) { + acpigen_emit_namestring(config->ec_notify_method); + acpigen_write_integer(0); + } + + /* Trigger L23 ready entry flow unless disabled by config. */ + if (!config->disable_l23) + nvidia_optimus_acpi_l23_entry(); + + /* Assert reset GPIO to place device into reset. */ + if (config->reset_gpio.pin_count) { + acpigen_enable_tx_gpio(&config->reset_gpio); + if (config->reset_off_delay_ms) + acpigen_write_sleep(config->reset_off_delay_ms); + } + + /* Disable SRCCLK for this root port if pin is defined. */ + if (config->srcclk_pin >= 0) + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); + + /* De-assert enable GPIO to turn off device power. */ + if (config->enable_gpio.pin_count) { + acpigen_disable_tx_gpio(&config->enable_gpio); + if (config->enable_off_delay_ms) + acpigen_write_sleep(config->enable_off_delay_ms); + } + + acpigen_pop_len(); /* If */ + + acpigen_write_store_int_to_namestr(0x5, "_STA"); + acpigen_pop_len(); /* Method */ +} + +static void nvidia_optimus_acpi_fill_ssdt(const struct device *dev) +{ + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + static const char *const power_res_states[] = {"_PR0", "_PR2", "_PR3"}; + const struct device *parent = dev->upstream->dev; + const char *scope = acpi_device_path(parent); + + /* PCH RP PCIe configuration space */ + const struct opregion rp_pci_config = OPREGION("PXCS", SYSTEMMEMORY, CONFIG_ECAM_MMCONF_BASE_ADDRESS | (parent->path.pci.devfn << 12), 0x1000); + const struct fieldlist rp_fieldlist[] = { + FIELDLIST_OFFSET(PCH_PCIE_CFG_LSTS), + FIELDLIST_RESERVED(13), + FIELDLIST_NAMESTR(ACPI_REG_PCI_LINK_ACTIVE, 1), + FIELDLIST_OFFSET(PCH_PCIE_CFG_SPR), + FIELDLIST_RESERVED(7), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_SAVE_STATE, 1), + FIELDLIST_OFFSET(PCH_PCIE_CFG_RPPGEN), + FIELDLIST_RESERVED(2), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_ENTRY, 1), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_DETECT, 1), + }; + uint8_t pcie_rp; + + /* dGPU PCIe configuration space */ + const struct opregion gpu_pci_config = OPREGION("PCIC", PCI_CONFIG, 0, 0x50); + const struct fieldlist gpu_fieldlist[] = { + FIELDLIST_OFFSET(PCH_PCIE_CFG_SSID), + FIELDLIST_NAMESTR(ACPI_REG_PCI_SUBSYSTEM_ID, 32), + }; + + if (!is_dev_enabled(parent)) { + printk(BIOS_ERR, "%s: root port not enabled\n", __func__); + return; + } + if (!scope) { + printk(BIOS_ERR, "%s: root port scope not found\n", __func__); + return; + } + if (!config->enable_gpio.pin_count && !config->reset_gpio.pin_count) { + printk(BIOS_ERR, "%s: Enable and/or Reset GPIO required for %s.\n", + __func__, scope); + return; + } + if (config->srcclk_pin > CONFIG_MAX_PCIE_CLOCK_SRC) { + printk(BIOS_ERR, "%s: Invalid clock pin %u for %s.\n", __func__, + config->srcclk_pin, scope); + return; + } + + /* Read port number of root port that this device is attached to. */ + pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN); + if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { + printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp); + return; + } + /* Port number is 1-based, PMC IPC method expects 0-based. */ + pcie_rp--; + + printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), + config->desc ?: dev->chip_ops->name); + + /* The RTD3 power resource is added to the root port, not the device. */ + acpigen_write_scope(scope); + + if (config->desc) + acpigen_write_name_string("_DDN", config->desc); + + acpigen_write_power_res("PWRR", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + acpigen_write_name_integer("_STA", 1); + + acpigen_write_method_serialized("_ON", 0); + acpigen_write_store_int_to_namestr(1, "_STA"); + acpigen_pop_len(); /* Method */ + + acpigen_write_method_serialized("_OFF", 0); + acpigen_write_store_int_to_namestr(0, "_STA"); + acpigen_pop_len(); /* Method */ + + acpigen_pop_len(); /* PowerResource */ + + + /* GPU scope */ + acpigen_write_device("DEV0"); + acpigen_write_name_integer("_ADR", 0x0); + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); + + acpigen_write_opregion(&rp_pci_config); + acpigen_write_field("PXCS", rp_fieldlist, ARRAY_SIZE(rp_fieldlist), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_opregion(&gpu_pci_config); + acpigen_write_field("PCIC", gpu_fieldlist, ARRAY_SIZE(gpu_fieldlist), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_power_res("PWRR", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + acpigen_write_name_integer("_STA", 0xF); + + nvidia_optimus_acpi_method_on(pcie_rp, dev); + nvidia_optimus_acpi_method_off(pcie_rp, dev); + + acpigen_pop_len(); /* PowerResource */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *nvidia_optimus_acpi_name(const struct device *dev) +{ + /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ + return "PXSX"; +} + +static struct device_operations nvidia_optimus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = nvidia_optimus_acpi_fill_ssdt, + .acpi_name = nvidia_optimus_acpi_name, + .ops_pci = &pci_dev_ops_pci, +}; + +static void nvidia_optimus_acpi_enable(struct device *dev) +{ + dev->ops = &nvidia_optimus_ops; +} + +struct chip_operations drivers_gfx_nvidia_optimus_ops = { + .name = "NVIDIA Optimus Hybrid Graphics", + .enable_dev = nvidia_optimus_acpi_enable +}; diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk index 4cb24ffb56d..f13b1d42289 100644 --- a/src/drivers/intel/fsp2_0/Makefile.mk +++ b/src/drivers/intel/fsp2_0/Makefile.mk @@ -122,7 +122,7 @@ ifeq ($(CONFIG_PLATFORM_USES_SECOND_FSP)$(CONFIG_FSP_FULL_FD),yy) $(obj)/Fsp_2_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH_2)) $(DOTCONFIG) python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH_2) -o "$(obj)" -n "Fsp_2.fd" -$(obj)/Fsp_2_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH_2)) $(obj)/Fsp_M.fd +$(obj)/Fsp_2_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH_2)) $(obj)/Fsp_2_M.fd true endif diff --git a/src/drivers/intel/fsp2_0/fsp_mpinit.c b/src/drivers/intel/fsp2_0/fsp_mpinit.c index cda9269cb8a..79fe006a733 100644 --- a/src/drivers/intel/fsp2_0/fsp_mpinit.c +++ b/src/drivers/intel/fsp2_0/fsp_mpinit.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include -#include /* * As per FSP integration guide: @@ -10,5 +11,8 @@ */ void do_mpinit_after_fsp(void) { - init_cpus(); + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + assert(dev != NULL); + + mp_cpu_bus_init(dev); } diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 41fccd6a523..b697ccbf21f 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -61,7 +61,7 @@ efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number, processor_info_buffer->ProcessorId = dev->path.apic.apic_id; processor_info_buffer->Location.Package = dev->path.apic.package_id; - processor_info_buffer->Location.Core = dev->path.apic.core_id; + processor_info_buffer->Location.Core = dev->path.apic.core_id_within_package; processor_info_buffer->Location.Thread = dev->path.apic.thread_id; return FSP_SUCCESS; diff --git a/src/drivers/intel/ptt/Makefile.mk b/src/drivers/intel/ptt/Makefile.mk index bab1789fd93..432035d4c70 100644 --- a/src/drivers/intel/ptt/Makefile.mk +++ b/src/drivers/intel/ptt/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-$(CONFIG_HAVE_INTEL_PTT) += ptt.c romstage-$(CONFIG_HAVE_INTEL_PTT) += ptt.c ramstage-$(CONFIG_HAVE_INTEL_PTT) += ptt.c postcar-$(CONFIG_HAVE_INTEL_PTT) += ptt.c diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 93cb2a6163a..f2200f3834c 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -806,8 +806,8 @@ static void lpc_tpm_set_resources(struct device *dev) #if CONFIG(HAVE_ACPI_TABLES) static void lpc_tpm_fill_ssdt(const struct device *dev) { - /* Windows 11 requires the following path for TPM to be detected */ - const char *path = "\\_SB_.PCI0"; + const struct device *domain = dev_get_domain(dev); + const char *path = acpi_device_scope(domain); /* Device */ acpigen_write_scope(path); diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index 4f7b4bdac0a..3ac52dc3458 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -138,6 +138,9 @@ static uint32_t smmstorev2_exec(uint8_t command, void *param) uint32_t smmstore_exec(uint8_t command, void *param) { + if (smmstore_preprocess_cmd(&command, param)) + return SMMSTORE_RET_SUCCESS; + if (command != SMMSTORE_CMD_CLEAR && !param) return SMMSTORE_RET_FAILURE; diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index f1e07e41dd7..2fca79f180f 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -12,10 +12,17 @@ #define SMMSTORE_REGION "SMMSTORE" - +#if !CONFIG(SOC_INTEL_APOLLOLAKE) _Static_assert(IS_ALIGNED(FMAP_SECTION_SMMSTORE_START, SMM_BLOCK_SIZE), "SMMSTORE FMAP region not aligned to 64K"); - +#else +/* + * On APL and GLK the addresses in FMAP are off by 4KiB due to architectural + * changes in flash mapping to host memory space + */ +_Static_assert(IS_ALIGNED(FMAP_SECTION_SMMSTORE_START + 0x1000, SMM_BLOCK_SIZE), + "SMMSTORE FMAP region not aligned to 64K"); +#endif _Static_assert(SMM_BLOCK_SIZE <= FMAP_SECTION_SMMSTORE_SIZE, "SMMSTORE FMAP region must be at least 64K"); @@ -41,8 +48,43 @@ _Static_assert(SMM_BLOCK_SIZE <= FMAP_SECTION_SMMSTORE_SIZE, * crash/reboot could clear out all variables. */ +static int use_full_flash; +static int has_capsules = -1; + +int smmstore_preprocess_cmd(uint8_t *cmd, void *param) +{ + if (CONFIG(DRIVERS_EFI_UPDATE_CAPSULES)) { + if (has_capsules == -1 && *cmd == SMMSTORE_CMD_USE_FULL_FLASH) { + has_capsules = !!(uintptr_t)param; + /* + * If we have capsules, return success, otherwise let smmstore_exec() + * fail on !param check, which will be 0 in that case. This informs + * the caller whether capsule handling was enabled or not. + */ + return has_capsules; + } else if (has_capsules == 1 && *cmd & SMMSTORE_CMD_USE_FULL_FLASH) { + use_full_flash = 1; + *cmd &= ~SMMSTORE_CMD_USE_FULL_FLASH; + } else { + use_full_flash = 0; + } + } + + return 0; +} + static enum cb_err lookup_store_region(struct region *region) { + if (CONFIG(DRIVERS_EFI_UPDATE_CAPSULES) && use_full_flash) { + const struct region_device *rdev = boot_device_rw(); + + if (rdev == NULL) + return CB_ERR; + + *region = *region_device_region(rdev); + return CB_SUCCESS; + } + if (fmap_locate_area(SMMSTORE_REGION, region)) { printk(BIOS_WARNING, "smm store: Unable to find SMM store FMAP region '%s'\n", diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index 1bcc79c8e9b..42630ff44f7 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -3,8 +3,8 @@ config TPM_INIT_RAMSTAGE bool default y if TPM - depends on !VBOOT && !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT \ - && !TPM_MEASURED_BOOT_INIT_BOOTBLOCK + depends on (!VBOOT || VBOOT_NO_TPM) && !VENDORCODE_ELTAN_VBOOT \ + && !VENDORCODE_ELTAN_MBOOT && !TPM_MEASURED_BOOT_INIT_BOOTBLOCK help This driver automatically initializes the TPM if vboot is not used. The TPM driver init is done during the ramstage chip init phase. diff --git a/src/ec/dasharo/ec/Kconfig b/src/ec/dasharo/ec/Kconfig index 901d3ce514b..fac56835f44 100644 --- a/src/ec/dasharo/ec/Kconfig +++ b/src/ec/dasharo/ec/Kconfig @@ -29,3 +29,21 @@ config EC_DASHARO_EC_UPDATE_FILE config EC_DASHARO_EC_FLASH_SIZE hex default 0x20000 + +if EC_DASHARO_EC_DGPU + +config EC_DASHARO_EC_CPU_FAN_COUNT + int + range 1 1 + default 1 + +endif + +if !EC_DASHARO_EC_DGPU + +config EC_DASHARO_EC_CPU_FAN_COUNT + int + range 1 2 + default 1 + +endif diff --git a/src/ec/dasharo/ec/Makefile.mk b/src/ec/dasharo/ec/Makefile.mk index d71a2fd9981..998941f98b9 100644 --- a/src/ec/dasharo/ec/Makefile.mk +++ b/src/ec/dasharo/ec/Makefile.mk @@ -6,4 +6,9 @@ all-y += dasharo_ec.c all-y += buttons.c smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c +cbfs-files-$(CONFIG_EC_DASHARO_EC_UPDATE) += ec.rom +ec.rom-file := $(call strip_quotes,$(CONFIG_EC_DASHARO_EC_UPDATE_FILE)) +ec.rom-compression := $(CBFS_COMPRESS_FLAG) +ec.rom-type := raw + endif diff --git a/src/ec/dasharo/ec/acpi/battery.asl b/src/ec/dasharo/ec/acpi/battery.asl index 106f3d1be01..b4d98300a3d 100644 --- a/src/ec/dasharo/ec/acpi/battery.asl +++ b/src/ec/dasharo/ec/acpi/battery.asl @@ -193,22 +193,8 @@ Device (BAT0) { If (^^PCI0.LPCB.EC0.BAT0) { - Local0 = 0 - Local1 = 0 - If (^^AC.ACFG) - { - If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) - { - Local0 |= 0x02 - Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) - } - } - Else - { - Local0 |= 1 - Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) - } - + Local0 = ^^PCI0.LPCB.EC0.BST0 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) Local7 = (Local1 & 0x8000) If ((Local7 == 0x8000)) { diff --git a/src/ec/dasharo/ec/acpi/dasharo.asl b/src/ec/dasharo/ec/acpi/dasharo.asl deleted file mode 100644 index a94da6a5dd5..00000000000 --- a/src/ec/dasharo/ec/acpi/dasharo.asl +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (DASH) { - Name (_HID, "DSHR4543") - Name (_UID, 0) - // Hide the device so that Windows does not warn about a missing driver. - Name (_STA, 0xB) - - Method (INIT, 0, Serialized) { - Printf ("DASH: INIT") - If (^^PCI0.LPCB.EC0.ECOK) { - // Set flags to use software control - ^^PCI0.LPCB.EC0.ECOS = 2 - Return (0) - } Else { - Return (1) - } - } - - Method (FINI, 0, Serialized) { - Printf ("DASH: FINI") - If (^^PCI0.LPCB.EC0.ECOK) { - // Set flags to use hardware control - ^^PCI0.LPCB.EC0.ECOS = 1 - Return (0) - } Else { - Return (1) - } - } - - // Fan names - Method (NFAN, 0, Serialized) { - Return (Package() { - "CPU fan", -#if CONFIG(EC_DASHARO_EC_DGPU) - "GPU fan", -#endif - }) - } - - // Get fan duty cycle and RPM as a single value - Method (GFAN, 1, Serialized) { - Local0 = 0 - Local1 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - If (Arg0 == 0) { - Local0 = ^^PCI0.LPCB.EC0.DUT1 - Local1 = ^^PCI0.LPCB.EC0.RPM1 - } ElseIf (Arg0 == 1) { - Local0 = ^^PCI0.LPCB.EC0.DUT2 - Local1 = ^^PCI0.LPCB.EC0.RPM2 - } - } - If (Local1 != 0) { - // 60 * (EC frequency / 120) / 2 - Local1 = 2156250 / Local1 - } - Return ((Local1 << 8) | Local0) - } - - // Temperature names - Method (NTMP, 0, Serialized) { - Return (Package() { - "CPU temp", -#if CONFIG(EC_DASHARO_EC_DGPU) - "GPU temp", -#endif - }) - } - - // Get temperature - Method (GTMP, 1, Serialized) { - Local0 = 0; - If (^^PCI0.LPCB.EC0.ECOK) { - If (Arg0 == 0) { - Local0 = ^^PCI0.LPCB.EC0.TMP1 - } ElseIf (Arg0 == 1) { - Local0 = ^^PCI0.LPCB.EC0.TMP2 - } - } - Return (Local0) - } -} diff --git a/src/ec/dasharo/ec/acpi/dshr.asl b/src/ec/dasharo/ec/acpi/dshr.asl new file mode 100644 index 00000000000..45ac61366dc --- /dev/null +++ b/src/ec/dasharo/ec/acpi/dshr.asl @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../driver.h" + +Device (DASH) { + Name (_HID, "DSHR0001") + Name (_UID, 0) + // Hide the device so that Windows does not warn about a missing driver. + Name (_STA, 0xB) + + // Version of the ACPI interface + Name (DSVR, 1) + + // Get platform features + Method (GFTR, 0, Serialized) + { + Return ( + (1 << DASHARO_FEATURE_TEMPERATURE) | + (1 << DASHARO_FEATURE_FAN_PWM) | + (1 << DASHARO_FEATURE_FAN_TACH)) + } + + // Get feature capabilities + Method (GFCP, 2, Serialized) + { + Switch (ToInteger(Arg0)) + { + Case (DASHARO_FEATURE_TEMPERATURE) + { + Switch (ToInteger(Arg1)) + { + Case (DASHARO_TEMPERATURE_CPU_PACKAGE) { Return (1) } +#if CONFIG(EC_DASHARO_EC_DGPU) + Case (DASHARO_TEMPERATURE_GPU) { Return (1) } +#endif + Default { Return (0) } + } + } + + Case (DASHARO_FEATURE_FAN_PWM) + { + Switch (ToInteger(Arg1)) + { +#if CONFIG(EC_DASHARO_EC_DGPU) + Case (DASHARO_FAN_CPU) { Return (1) } + Case (DASHARO_FAN_GPU) { Return (1) } +#else + Case (DASHARO_FAN_CPU) { Return (CONFIG_EC_DASHARO_EC_CPU_FAN_COUNT) } +#endif + Default { Return (0) } + } + } + + Case (DASHARO_FEATURE_FAN_TACH) + { + Switch (ToInteger(Arg1)) + { +#if CONFIG(EC_DASHARO_EC_DGPU) + Case (DASHARO_FAN_CPU) { Return (1) } + Case (DASHARO_FAN_GPU) { Return (1) } +#else + Case (DASHARO_FAN_CPU) { Return (CONFIG_EC_DASHARO_EC_CPU_FAN_COUNT) } +#endif + Default { Return (0) } + } + } + Default { Return (0) } + } + } + + // Get temperature by capability and index + Method (GTMP, 2, Serialized) + { + If (\_SB.PCI0.LPCB.EC0.ECOK == 0) { Return (0) } + + Switch (ToInteger(Arg0)) + { + Case (DASHARO_TEMPERATURE_CPU_PACKAGE) + { + If (Arg1 == 0) { Return (\_SB.PCI0.LPCB.EC0.TMP1) } + } +#if CONFIG(EC_DASHARO_EC_DGPU) + Case (DASHARO_TEMPERATURE_GPU) + { + If (Arg1 == 0) { Return (\_SB.PCI0.LPCB.EC0.TMP2) } + } +#endif + Default { Return (0) } + } + + Return (0) + } + + // Get fan tach reading by cap and index + Method (GFTH, 2, Serialized) + { + If (\_SB.PCI0.LPCB.EC0.ECOK == 0) { Return (0) } + + Switch (ToInteger(Arg0)) + { + // FIXME: Some laptops have dual CPU fans with separate tach, + // while some share a single tach + Case (DASHARO_TEMPERATURE_CPU_PACKAGE) + { + If (Arg1 == 0) + { + Local0 = \_SB.PCI0.LPCB.EC0.RPM1 + If (Local0 == 0) { Return (0) } + + // 60 * (EC frequency (9.2MHz) / 128) / 2 + Return (2156250 / Local0) + } +#if CONFIG_EC_DASHARO_EC_CPU_FAN_COUNT == 2 + If (Arg1 == 1) + { + Local0 = \_SB.PCI0.LPCB.EC0.RPM2 + If (Local0 == 0) { Return (0) } + + // 60 * (EC frequency (9.2MHz) / 128) / 2 + Return (2156250 / Local0) + } +#endif + } +#if CONFIG(EC_DASHARO_EC_DGPU) + Case (DASHARO_FAN_GPU) + { + If (Arg1 == 0) + { + Local0 = \_SB.PCI0.LPCB.EC0.RPM2 + If (Local0 == 0) { Return (0) } + + // 60 * (EC frequency (9.2MHz) / 128) / 2 + Return (2156250 / Local0) + } + } +#endif + Default { Return (0) } + } + + Return (0) + } + + // Get fan duty cycle by cap and index + Method (GFDC, 2, Serialized) + { + If (\_SB.PCI0.LPCB.EC0.ECOK == 0) { Return (0) } + + Switch (ToInteger(Arg0)) + { + Case (DASHARO_TEMPERATURE_CPU_PACKAGE) + { + If (Arg1 == 0) { Return (\_SB.PCI0.LPCB.EC0.DUT1) } +#if CONFIG_EC_DASHARO_EC_CPU_FAN_COUNT == 2 + If (Arg1 == 1) { Return (\_SB.PCI0.LPCB.EC0.DUT2) } +#endif + } +#if CONFIG(EC_DASHARO_EC_DGPU) + Case (DASHARO_FAN_GPU) + { + If (Arg1 == 0) { Return (\_SB.PCI0.LPCB.EC0.DUT2) } + } +#endif + Default { Return (0) } + } + + Return (0) + } +} diff --git a/src/ec/dasharo/ec/acpi/dtt.asl b/src/ec/dasharo/ec/acpi/dtt.asl new file mode 100644 index 00000000000..1dd85c58963 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/dtt.asl @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Device (TPWR) +{ + Name (_HID, DPTF_TPWR_DEVICE) + Name (_UID, "TPWR") + Name (_STR, Unicode("Intel DTT Power Participant")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (PTYP, 0x11) // Device is a platform power device + + Method (PSRC, 0) // Power source + { + Return (^^AC.ACFG) + } + + Method (ARTG, 0) // Adapter rating + { + If (^^PCI0.LPCB.EC0.ECOK) + { + Return (^^PCI0.LPCB.EC0.APWR) + } + Else + { + Return (0) + } + } + + Method (PBOK, 1) // Power Boss OK + { + // Notify EC to de-assert PROCHOT# + // Required by DTT, but N/A on this hardware, PROCHOT# + // is de-asserted by board logic upon AC plug-in + } +} + +Device (TBAT) +{ + Name (_HID, DPTF_BAT1_DEVICE) + Name (_STR, Unicode("Intel DTT Battery Participant")) + + Method (_STA, 0, NotSerialized) + { + Return (^^BAT0._STA) + } + + Name (PTYP, 0x0c) // Device is a platform battery device + Name (CTYP, 0x02) // Hybrid Power Boost architecture +} diff --git a/src/ec/dasharo/ec/acpi/ec.asl b/src/ec/dasharo/ec/acpi/ec.asl index e13c52dc390..51221ee8628 100644 --- a/src/ec/dasharo/ec/acpi/ec.asl +++ b/src/ec/dasharo/ec/acpi/ec.asl @@ -6,7 +6,8 @@ Scope (\_SB) { #include "buttons.asl" #include "hid.asl" #include "lid.asl" - #include "dasharo.asl" + #include "dshr.asl" + #include "dtt.asl" } Device (\_SB.PCI0.LPCB.EC0) @@ -107,6 +108,7 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_Q0A, 0, NotSerialized) // Touchpad Toggle { Printf ("EC: Touchpad Toggle") + TPTG () } Method (_Q0B, 0, NotSerialized) // Screen Toggle @@ -175,6 +177,7 @@ Device (\_SB.PCI0.LPCB.EC0) Printf ("EC: AC Detect") ^^^^AC.ACFG = ADP Notify (AC, 0x80) // Status Change + Notify (TPWR, 0x81) // Power State Change If (BAT0) { Notify (^^^^BAT0, 0x81) // Information Change diff --git a/src/ec/dasharo/ec/acpi/ec_ram.asl b/src/ec/dasharo/ec/acpi/ec_ram.asl index 008737785bd..8cd565cbd46 100644 --- a/src/ec/dasharo/ec/acpi/ec_ram.asl +++ b/src/ec/dasharo/ec/acpi/ec_ram.asl @@ -42,6 +42,9 @@ Field (ERAM, ByteAcc, Lock, Preserve) DUT2, 8, // Fan 2 duty RPM1, 16, // Fan 1 RPM RPM2, 16, // Fan 2 RPM + Offset (0xD4), + GPUD, 8, // GPU D-notify level + APWR, 32, // AC adapter power Offset (0xD9), AIRP, 8, // Airplane mode LED WINF, 8, // Enable ACPI brightness controls diff --git a/src/ec/dasharo/ec/commands.h b/src/ec/dasharo/ec/commands.h index 0fe7db40989..00529f4a51d 100644 --- a/src/ec/dasharo/ec/commands.h +++ b/src/ec/dasharo/ec/commands.h @@ -79,9 +79,17 @@ // Persistent option definitions enum { OPT_POWER_ON_AC = 0, + OPT_KBLED_LEVEL_I, + OPT_KBLED_COLOR_I, + OPT_BAT_THRESHOLD_START, + OPT_BAT_THRESHOLD_STOP, + OPT_ALLOW_BAT_BOOST, + OPT_ALWAYS_ON_USB, + OPT_GPU_MUX_CTRL, NUM_OPTIONS }; uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data); +uint8_t dasharo_read_option(uint8_t option, uint8_t *value); uint8_t dasharo_ec_read_version(uint8_t *data); uint8_t dasharo_ec_read_board(uint8_t *data); diff --git a/src/ec/dasharo/ec/dasharo_ec.c b/src/ec/dasharo/ec/dasharo_ec.c index 571c6a06d01..4d88f5befc8 100644 --- a/src/ec/dasharo/ec/dasharo_ec.c +++ b/src/ec/dasharo/ec/dasharo_ec.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,33 @@ // When command register is 0, command is complete #define CMD_FINISHED 0 +#define SPI_WREN 0x06 /* Write Enable */ +#define SPI_WRDI 0x04 /* Write Disable */ +#define SPI_RDSR 0x05 /* Read Status Register */ +#define SPI_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define SPI_AAI_WP 0xad /* Auto Address Increment Word Program */ +#define SPI_BE 0xd7 /* 1K Block Erase */ + +#define SPI_SR_WIP (1 << 0) /* Write-in-Progress */ +#define SPI_SR_WEL (1 << 1) /* Write enable */ + +#define SPI_TIMEOUT_10MS 10000 + +#define SPI_ACCESS_SIZE 252 + +#define MAX_WRITE_RETRY 3 + +enum ec_update_error { + /* AC adapter is not connected. */ + EC_UPDATE_ERR_NO_AC, + /* EC did not jump to scratch ROM */ + EC_UPDATE_ERR_SCRATCH, + /* EC erase failed */ + EC_UPDATE_ERR_ERASE, + /* Programming EC failed */ + EC_UPDATE_ERR_PROGRAM, +}; + static inline uint8_t dasharo_ec_read(uint8_t addr) { return inb(DASHARO_EC_BASE + (uint16_t)addr); @@ -39,12 +67,14 @@ uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data) { int i; - if (len > DASHARO_EC_SIZE - REG_DATA) + if (len > DASHARO_EC_SIZE - REG_DATA) { + printk(BIOS_ERR, "dasharo_ec: Invalid command length\n"); return -1; + } // Wait for previous command completion, for up to 10 milliseconds, with a // test period of 1 microsecond - wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); // Write data first for (i = 0; i < len; ++i) @@ -55,7 +85,7 @@ uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data) // Wait for previous command completion, for up to 10 milliseconds, with a // test period of 1 microsecond - wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); return dasharo_ec_read(REG_RESULT); } @@ -91,3 +121,853 @@ void dasharo_ec_set_bat_threshold(enum bat_threshold_type type, uint8_t value) break; } } + +uint8_t dasharo_read_option(uint8_t option, uint8_t *value) +{ + dasharo_ec_smfi_cmd(CMD_OPTION_GET, 1, (uint8_t *)&option); + *value = dasharo_ec_read(REG_DATA); + + return (dasharo_ec_read(REG_RESULT)); +} + +uint8_t dasharo_ec_read_version(uint8_t *data) +{ + int i; + uint8_t result; + + if (!data) + return -1; + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + // Write command register, which starts command + dasharo_ec_write(REG_CMD, CMD_VERSION); + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + result = dasharo_ec_read(REG_RESULT); + + if (result != 0) + return result; + + // Read data bytes, index should be valid due to length test above + for (i = 0; i < (DASHARO_EC_SIZE - REG_DATA); i++) { + data[i] = dasharo_ec_read(REG_DATA + i); + if (data[i] == '\0') + break; + } + + return result; +} + +uint8_t dasharo_ec_read_board(uint8_t *data) +{ + int i; + uint8_t result; + + if (!data) + return -1; + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + // Write command register, which starts command + dasharo_ec_write(REG_CMD, CMD_BOARD); + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + result = dasharo_ec_read(REG_RESULT); + + if (result != 0) + return result; + + // Read data bytes, index should be valid due to length test above + for (i = 0; i < (DASHARO_EC_SIZE - REG_DATA); i++) { + data[i] = dasharo_ec_read(REG_DATA + i); + if (data[i] == '\0') + break; + } + + return result; +} + +/* Ported from system76_ectool */ +static int firmware_str(char *data, int data_len, const char *key, char *dest, int dest_len) +{ + int data_i, key_i, ret_i; + int key_len = strlen(key); + + data_i = key_i = ret_i = 0; + + /* Locate the key */ + while (data_i < data_len && key_i < key_len) { + if (data[data_i] == key[key_i]) + key_i += 1; + else + key_i = 0; + data_i += 1; + } + + if (key_i < key_len) + return 0; + + while (data_i < data_len && ret_i < dest_len - 1 && data[data_i] != 0) + dest[ret_i++] = data[data_i++]; + + dest[ret_i] = '\0'; + + return ret_i; +} + +/* Reset the EC SPI bus */ +static uint8_t ec_spi_reset(void) +{ + uint8_t reset_cmd = CMD_SPI_FLAG_DISABLE | CMD_SPI_FLAG_SCRATCH; + + return dasharo_ec_smfi_cmd(CMD_SPI, sizeof(reset_cmd), &reset_cmd); +} + +/* + * Read len bytes from EC SPI bus into dest. + * Returns 0 on success, <0 on error + */ +static int ec_spi_bus_read(uint8_t *dest, uint32_t len) +{ + uint32_t addr, i, rv; + + uint8_t read_cmd[2] = { + [0] = CMD_SPI_FLAG_READ | CMD_SPI_FLAG_SCRATCH, + [1] = 0, + }; + + for (addr = 0; addr + SPI_ACCESS_SIZE < len; addr += SPI_ACCESS_SIZE) { + read_cmd[1] = SPI_ACCESS_SIZE; + + if ((rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(read_cmd), read_cmd))) { + printk(BIOS_ERR, "dasharo_ec: Failed to send read SPI bus command\n"); + return -rv; + } + + if (dasharo_ec_read(REG_DATA + 1) != read_cmd[1]) { + printk(BIOS_ERR, "dasharo_ec: SPI bus read insufficient bytes\n"); + return -1; + } + + for (i = 0; i < read_cmd[1]; i++) + dest[addr + i] = dasharo_ec_read(REG_DATA + 2 + i); + } + + if (addr == len) + return 0; + + read_cmd[1] = len % SPI_ACCESS_SIZE; + + if ((rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(read_cmd), read_cmd))) { + printk(BIOS_ERR, "dasharo_ec: Failed to send read SPI bus command (remainder)\n"); + return -rv; + } + + if (dasharo_ec_read(REG_DATA + 1) != read_cmd[1]) { + printk(BIOS_ERR, "dasharo_ec: SPI bus read remainder insufficient bytes\n"); + return -1; + } + + for (i = 0; i < read_cmd[1]; i++) + dest[addr + i] = dasharo_ec_read(REG_DATA + 2 + i); + + return 0; +} + +/* + * Write len bytes from data to EC SPI bus with flags. + * Returns 0 on success, <0 on error + */ +static int ec_spi_bus_write_with_flags(uint8_t *data, uint8_t len, uint8_t flags) +{ + uint32_t addr, i, rv; + uint8_t write_cmd[2] = { + [0] = CMD_SPI_FLAG_SCRATCH | flags, + [1] = len, + }; + + for (addr = 0; addr + SPI_ACCESS_SIZE < len; addr += SPI_ACCESS_SIZE) { + write_cmd[1] = SPI_ACCESS_SIZE; + + for (i = 0; i < write_cmd[1]; ++i) + dasharo_ec_write(REG_DATA + ARRAY_SIZE(write_cmd) + i, data[addr + i]); + + rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(write_cmd), write_cmd); + if (rv) { + printk(BIOS_ERR, "dasharo_ec: Failed to send write SPI bus command\n"); + return -rv; + } + + if (dasharo_ec_read(REG_DATA + 1) != write_cmd[1]) { + printk(BIOS_ERR, "dasharo_ec: SPI bus write insufficient bytes\n"); + return -1; + } + } + + if (addr == len) + return 0; + + write_cmd[1] = len % SPI_ACCESS_SIZE; + + for (i = 0; i < write_cmd[1]; i++) + dasharo_ec_write(REG_DATA + ARRAY_SIZE(write_cmd) + i, data[addr + i]); + + rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(write_cmd), write_cmd); + if (rv) { + printk(BIOS_ERR, "dasharo_ec: Failed to send write SPI bus command (remainder)\n"); + return -rv; + } + + if (dasharo_ec_read(REG_DATA + 1) != write_cmd[1]) { + printk(BIOS_ERR, "dasharo_ec: SPI bus write remainder insufficient bytes\n"); + return -1; + } + + return 0; +} + +/* + * Write len bytes from data to EC SPI bus + * Returns 0 on success, <0 on error + */ +static int ec_spi_bus_write(uint8_t *data, uint8_t len) +{ + return ec_spi_bus_write_with_flags(data, len, 0); +} + +static int ec_spi_wait_status(uint8_t mask, uint8_t value, const char *func, + const unsigned int line) +{ + struct stopwatch sw; + uint8_t status; + int rv; + uint8_t cmd = SPI_RDSR; + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + rv = ec_spi_bus_write(&cmd, sizeof(cmd)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_10MS); + + rv = ec_spi_bus_read(&status, sizeof(status)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_read failed\n", __func__); + return rv; + } + + while ((status & mask) != value) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "%s: Timeout at %s:%u\n", __func__, func, line); + ec_spi_reset(); + return -1; + } + + /* + * Status Register can be constantly read from SPI bus. + * No need to start new RDSR command. + */ + rv = ec_spi_bus_read(&status, sizeof(status)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_read failed\n", __func__); + ec_spi_reset(); + return rv; + } + } + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + return 0; +} + +static int ec_spi_cmd_write_enable(void) +{ + int rv; + uint8_t cmd = SPI_WREN;; + + rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + if (rv) { + printk(BIOS_ERR, "%s: flash not ready\n", __func__); + return rv; + } + + rv = ec_spi_bus_write(&cmd, sizeof(cmd)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + return ec_spi_wait_status(SPI_SR_WIP | SPI_SR_WEL, SPI_SR_WEL, __func__, __LINE__); +} + +static int ec_spi_cmd_write_disable(void) +{ + int rv; + uint8_t cmd = SPI_WRDI; + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + rv = ec_spi_bus_write(&cmd, sizeof(cmd)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + return ec_spi_wait_status(SPI_SR_WIP | SPI_SR_WEL, 0, __func__, __LINE__); +} + +/* Erase a sector at addr. Returns 0 on success <0 on error. */ +static int ec_spi_erase_sector(uint32_t addr) +{ + int rv; + uint8_t buf[4] = { + [0] = SPI_BE, + [1] = (addr >> 16) & 0xFF, + [2] = (addr >> 8) & 0xFF, + [3] = addr & 0xFF, + }; + + rv = ec_spi_cmd_write_enable(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_cmd_write_enable failed\n", __func__); + return rv; + } + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + rv = ec_spi_bus_write(buf, ARRAY_SIZE(buf)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + if (rv) + return rv; + + rv = ec_spi_cmd_write_disable(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_cmd_write_disable failed\n", __func__); + return rv; + } + + return 0; +} + +/* Read a sector into dest. Returns 0 on success and <0 on error. */ +static int ec_spi_read_sector(uint8_t *dest, uint32_t addr) +{ + int rv; + uint8_t buf[5] = { + [0] = SPI_FAST_READ, + [1] = (addr >> 16) & 0xFF, + [2] = (addr >> 8) & 0xFF, + [3] = addr & 0xFF, + [4] = 0, + }; + + rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + if (rv) + return rv; + + rv = ec_spi_bus_write(buf, ARRAY_SIZE(buf)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + rv = ec_spi_bus_read(dest, SPI_SECTOR_SIZE); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_read failed\n", __func__); + return rv; + } + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + return 0; +} + +/* Read a sector and verify if it has been erased. Returns 0 on success and <0 on error. */ +static int ec_spi_verify_erased_sector(uint32_t addr) +{ + int rv, i; + uint8_t buf[5] = { + [0] = SPI_FAST_READ, /* SPI Read */ + [1] = (addr >> 16) & 0xFF, + [2] = (addr >> 8) & 0xFF, + [3] = addr & 0xFF, + [4] = 0, + }; + uint8_t data; + + rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + if (rv) + return rv; + + rv = ec_spi_bus_write(buf, ARRAY_SIZE(buf)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + for (i = 0; i < SPI_SECTOR_SIZE; i++) { + /* Read the sector byte after byte and compare. */ + rv = ec_spi_bus_read(&data, sizeof(data)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_read failed\n", __func__); + return rv; + } + + if (data != 0xff) { + printk(BIOS_ERR, "%s: sector at %x is not erased\n", __func__, addr); + return -1; + } + } + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + return 0; +} + +/* + * Program a chip with a given image at given address and size of data. + * Returns written byte count on success and <0 on error. + */ +static int ec_spi_write_at(uint32_t start, uint8_t *image, size_t size) +{ + int rv; + uint32_t addr; + uint8_t buf[6] = {0}; + + buf[0] = SPI_AAI_WP; + buf[1] = (start >> 16) & 0xff; + buf[2] = (start >> 8) & 0xff; + buf[3] = start & 0xff; + + rv = ec_spi_cmd_write_enable(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_cmd_write_enable failed\n", __func__); + return rv; + } + + for (addr = start; addr < start + size; addr += 2) { + + /* + * ec_spi_cmd_write_enable ends with ec_spi_wait_status which always calls + * ec_spi_reset. No need to do it here again. We also reset the SPI + * (make the CS# go high) after AAI WP command* by passing the + * CMD_SPI_FLAG_DISABLE to ec_spi_bus_write_with_flags. + */ + + if (addr == start) { + /* 1st cmd bytes 1,2,3 are the address */ + buf[4] = image[addr]; + buf[5] = image[addr + 1]; + + rv = ec_spi_bus_write_with_flags(buf, 6, CMD_SPI_FLAG_DISABLE); + } else { + buf[1] = image[addr]; + buf[2] = image[addr + 1]; + + rv = ec_spi_bus_write_with_flags(buf, 3, CMD_SPI_FLAG_DISABLE); + } + + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed, addr 0x%06x\n", + __func__, addr); + return rv; + } + + /* + * From the experiments it looked like the busy bit is never set. + * It is still dangerous to not probe the bit, however, AAI programming + * is quite picky and stops after first 2 bytes if we interrupt the + * process with different command than AAI word program. + * + * rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + * if (rv) return rv; + */ + } + + rv = ec_spi_cmd_write_disable(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_cmd_write_disable failed\n", __func__); + return rv; + } + + return addr - start; +} + +/* + * Program an entire chip with a given image. + * Returns written byte count on success and <0 on error. + */ +static int ec_spi_image_write(uint8_t *image, size_t size) +{ + uint8_t *sector; + uint32_t addr; + uint32_t erase_addr = CONFIG_EC_DASHARO_EC_FLASH_SIZE; + size_t length; + int rv; + + sector = malloc(SPI_SECTOR_SIZE); + if (!sector) + return -1; + + rv = 0; + addr = 0; + + while ((addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE) && + ((addr + SPI_SECTOR_SIZE) < size)) { + rv = ec_spi_read_sector(sector, addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_read_sector failed, addr 0x%06x\n", + __func__, addr); + goto cleanup; + } + + if (!memcmp(sector, image + addr, SPI_SECTOR_SIZE)) { + printk(BIOS_SPEW, "%s: Skipping identical sector, addr 0x%06x\n", + __func__, addr); + addr += SPI_SECTOR_SIZE; + continue; + } + + rv = ec_spi_erase_sector(addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_erase_sector failed, addr 0x%06x\n", + __func__, addr); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + + rv = ec_spi_verify_erased_sector(addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_verify_erased_sector failed, addr 0x%06x\n", + __func__, addr); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + + rv = ec_spi_write_at(addr, image, SPI_SECTOR_SIZE); + if (rv < 0) { + printk(BIOS_ERR, "%s: ec_spi_write_at failed, addr 0x%06x (%d)\n", + __func__, addr, rv); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_PROGRAM); + goto cleanup; + } + + addr += SPI_SECTOR_SIZE; + } + + /* Update any remainder bytes */ + rv = ec_spi_read_sector(sector, addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_read_sector failed, last addr 0x%06x\n", + __func__, addr); + goto cleanup; + } + + erase_addr = addr + SPI_SECTOR_SIZE; + + if (size % SPI_SECTOR_SIZE == 0 && addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE) + length = SPI_SECTOR_SIZE; + else + length = size % SPI_SECTOR_SIZE; + + if (memcmp(sector, image + addr, length)) { + rv = ec_spi_erase_sector(addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_erase_sector failed, addr 0x%06x\n", + __func__, addr); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + + rv = ec_spi_write_at(addr, image, length); + if (rv < 0) { + printk(BIOS_ERR, "%s: ec_spi_write_at failed, addr 0x%06x (%d)\n", + __func__, addr, rv); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_PROGRAM); + goto cleanup; + } + + addr += length; + } else { + printk(BIOS_SPEW, "%s: Skipping identical sector, addr 0x%06x\n", + __func__, addr); + addr += length; + } + + /* Erase remaining sectors if any */ + while (erase_addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE) { + rv = ec_spi_erase_sector(erase_addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_erase_sector failed, addr 0x%06x\n", + __func__, erase_addr); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + erase_addr += SPI_SECTOR_SIZE; + } + +cleanup: + free(sector); + + return rv ? rv : addr; +} + +/* Verify an image sector by sector. Returns 0 on success and <0 on error. */ +static int ec_spi_image_verify(uint8_t *image, ssize_t image_sz) +{ + uint8_t *sector; + uint32_t addr; + int rv; + int error = 0; + + sector = malloc(SPI_SECTOR_SIZE); + if (!sector) + return -1; + + rv = 0; + addr = 0; + + while ((addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE) && + ((addr + SPI_SECTOR_SIZE) < image_sz)) { + rv = ec_spi_read_sector(sector, addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_read_sector failed, addr 0x%06x\n", + __func__, addr); + return rv; + } + + rv = memcmp(sector, image + addr, SPI_SECTOR_SIZE) ? -1 : 0; + if (rv) { + printk(BIOS_ERR, "%s: failed to verify sector, addr 0x%06x\n", + __func__, addr); + error = rv; + } + + addr += SPI_SECTOR_SIZE; + } + + if (addr == image_sz) + goto exit; + + rv = ec_spi_read_sector(sector, addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_read_sector failed, last addr 0x%06x\n", + __func__, addr); + goto exit; + } + + rv = memcmp(sector, image + addr, image_sz % SPI_SECTOR_SIZE) ? -1 : 0; + if (rv) { + printk(BIOS_ERR, "%s: failed to verify last sector, addr 0x%06x size 0x%lx\n", + __func__, addr, image_sz % SPI_SECTOR_SIZE); + goto exit; + } + +exit: + free(sector); + + if (error) + return error; + + return rv; +} + +/* Sync the EC firmware with an image contained in CBFS. */ +static void dasharo_ec_fw_sync(void *unused) +{ + size_t image_sz; + char *image; + char img_board_str[64]; + char img_version_str[64]; + char cur_board_str[64]; + char cur_version_str[64]; + uint8_t smfi_cmd; + int rv; + + if (!CONFIG(EC_DASHARO_EC_UPDATE)) + return; + + if (vboot_recovery_mode_enabled()) { + printk(BIOS_INFO, "EC: skipping update in recovery mode.\n"); + return; + } + + image = malloc(CONFIG_EC_DASHARO_EC_FLASH_SIZE); + if (image == NULL) { + printk(BIOS_ERR, "EC: failed to allocate memory for update."); + return; + } + + image_sz = cbfs_load("ec.rom", image, CONFIG_EC_DASHARO_EC_FLASH_SIZE); + if (!image_sz) { + printk(BIOS_ERR, "EC: failed to load update from CBFS."); + goto cleanup; + } + + printk(BIOS_INFO, "EC: update found (%ld bytes)\n", image_sz); + + /* Sanity checks */ + if (image_sz % 2 || image_sz > CONFIG_EC_DASHARO_EC_FLASH_SIZE) { + printk(BIOS_ERR, "EC: incorrect update size.\n"); + goto cleanup; + } + + if (!firmware_str(image, image_sz, "76EC_BOARD=", img_board_str, + ARRAY_SIZE(img_board_str))) { + printk(BIOS_ERR, "EC: could not determine update target board.\n"); + goto cleanup; + } + + if (!firmware_str(image, image_sz, "76EC_VERSION=", img_version_str, + ARRAY_SIZE(img_version_str))) { + printk(BIOS_ERR, "EC: could not determine update version.\n"); + goto cleanup; + } + + printk(BIOS_INFO, "EC: update target: %s\n", img_board_str); + printk(BIOS_INFO, "EC: update version: %s\n", img_version_str); + + dasharo_ec_read_board((uint8_t *)cur_board_str); + dasharo_ec_read_version((uint8_t *)cur_version_str); + + if (strcmp(img_board_str, cur_board_str)) { + printk(BIOS_ERR, "EC: update target mismatch detected! Found %s, expected %s\n", + img_board_str, cur_board_str); + goto cleanup; + } + + printk(BIOS_INFO, "EC: current version: %s\n", cur_version_str); + if (!strcmp(img_version_str, cur_version_str)) { + printk(BIOS_INFO, "EC: update not needed.\n"); + goto cleanup; + } else { + printk(BIOS_INFO, "EC: update required!\n"); + } + + if ((ec_read(0x10) & 0x01) != 0x01) { + printk(BIOS_WARNING, "EC: AC adapter not connected, skipping update.\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_NO_AC); + goto cleanup; + } + + /* Jump to Scratch ROM */ + smfi_cmd = CMD_SPI_FLAG_SCRATCH; + if (dasharo_ec_smfi_cmd(CMD_SPI, sizeof(smfi_cmd), &smfi_cmd)) { + /* If we failed to jump to scratch ROM, then we can probably continue booting. */ + printk(BIOS_ERR, "EC: failed to jump to scratch ROM!\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_SCRATCH); + goto cleanup; + } + + for (int i = 0; i < MAX_WRITE_RETRY; i++) { + rv = ec_spi_image_write((uint8_t *)image, image_sz); + if (rv < 0) { + /* EC is now in an unknown state. It may still boot from backup. */ + printk(BIOS_ALERT, "EC: update failed!\n"); + } else { + printk(BIOS_INFO, "EC: wrote %x bytes\n", rv); + } + + rv = ec_spi_image_verify((uint8_t *)image, image_sz); + if (rv < 0) { + printk(BIOS_ALERT, "EC: update verification failed! (try: %d)\n", + i + 1); + } else { + printk(BIOS_INFO, "EC: update verified.\n"); + rv = 0; + break; + } + } + + if (rv < 0) { + /* EC is now in an unknown state. It may still boot from backup. */ + printk(BIOS_ALERT, "EC: update failed!\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_PROGRAM); + goto cleanup; + } + + smfi_cmd = CMD_SPI_FLAG_DISABLE; + if (dasharo_ec_smfi_cmd(CMD_SPI, sizeof(smfi_cmd), &smfi_cmd)) { + printk(BIOS_ERR, "EC: failed to disable SPI bus!\n"); + goto cleanup; + } + + smfi_cmd = 0; + if (dasharo_ec_smfi_cmd(CMD_RESET, sizeof(smfi_cmd), &smfi_cmd)) + printk(BIOS_ERR, "EC: failed to trigger reset!\n"); + +cleanup: + free(image); + return; +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, dasharo_ec_fw_sync, NULL); diff --git a/src/ec/dasharo/ec/driver.h b/src/ec/dasharo/ec/driver.h new file mode 100644 index 00000000000..49c4e2291c9 --- /dev/null +++ b/src/ec/dasharo/ec/driver.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* ID of each feature supported by the ACPI interface. */ +#define DASHARO_FEATURE_TEMPERATURE 0 +#define DASHARO_FEATURE_FAN_PWM 1 +#define DASHARO_FEATURE_FAN_TACH 2 +#define DASHARO_FEATURE_FAN_POINTS 3 + +/* Temperature sensor type. */ +#define DASHARO_TEMPERATURE_CPU_PACKAGE 0 +#define DASHARO_TEMPERATURE_CPU_CORE 1 +#define DASHARO_TEMPERATURE_GPU 2 +#define DASHARO_TEMPERATURE_BOARD 3 +#define DASHARO_TEMPERATURE_CHASSIS 4 + +/* Fan type */ +#define DASHARO_FAN_CPU 0 +#define DASHARO_FAN_GPU 1 +#define DASHARO_FAN_CHASSIS 2 + +/* Fan PWM mode */ +#define DASHARO_FAN_PWM_MODE_AUTO 0 +#define DASHARO_FAN_PWM_MODE_MANUAL 1 diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index 75c12a8be95..95454f6e8ea 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -10,6 +10,12 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define TPR_UPDATES_DISABLE (1 << 10) +/* Public key hash of ACM signing key. */ +#define MSR_ACM_CPU_KEY_HASH_0 0x20 +#define MSR_ACM_CPU_KEY_HASH_1 0x21 +#define MSR_ACM_CPU_KEY_HASH_2 0x22 +#define MSR_ACM_CPU_KEY_HASH_3 0x23 + #define MSR_PLATFORM_INFO 0xce #define MSR_BC_PBEC 0x139 diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 0e1384fe7ed..bd448e3df15 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -8,8 +8,11 @@ #include #include #include +#include #include +extern atomic_t parked_ap_count; + static __always_inline uint32_t xapic_read(unsigned int reg) { return read32((volatile void *)(uintptr_t)(LAPIC_DEFAULT_BASE + reg)); @@ -172,6 +175,7 @@ static __always_inline void lapic_send_ipi_others(uint32_t icrlow) */ static __always_inline void stop_this_cpu(void) { + atomic_inc(&parked_ap_count); /* Called by an AP when it is ready to halt and wait for a new task */ halt(); } diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index dd86dce2c54..f80d309bbb8 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -135,6 +135,13 @@ enum cb_err mp_run_on_all_cpus_synchronously(void (*func)(void *), void *arg); */ enum cb_err mp_park_aps(void); +/* + * Restart APs after they have been parked. Used by Intel TXT, which requires + * parking APs before running ACM , to restart APs and let coreboot program + * MTRRs on APs. For use only after mp_init. + */ +enum cb_err restart_aps(void); + /* * SMM helpers to use with initializing CPUs. */ diff --git a/src/include/device/path.h b/src/include/device/path.h index 8e9ec3bdd50..03aa909d889 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -81,6 +81,12 @@ struct apic_path { unsigned int node_id; unsigned int core_id; unsigned int thread_id; + unsigned int module_id; + /* + * Core identifier within the package, including the die group, die, tile, module, and + * specific core. + */ + unsigned int core_id_within_package; unsigned char core_type; }; diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 6748b356b73..a824dd55db8 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -574,7 +574,8 @@ #define PCI_REBAR_CTRL_NBARS_SHIFT 5 #define PCI_REBAR_CTRL_IDX_MASK 0x07 #define PCI_REBAR_CTRL_SIZE_MASK 0xffff0000 -#define PCI_REBAR_CTRL_SIZE_SHIFT 16 +#define PCI_REBAR_CTRL_BAR_SIZE_MASK 0xffff00ff +#define PCI_REBAR_CTRL_BAR_SIZE_SHIFT 8 /* Root Complex Event Collector Endpoint Association */ #define PCI_RCECEA_BITMAP 4 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 60ed807f31e..604dd6dcfaa 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3535,6 +3535,7 @@ #define PCI_DID_INTEL_ADL_P_PCIE_RP1 0x464d #define PCI_DID_INTEL_ADL_P_PCIE_RP2 0x460d #define PCI_DID_INTEL_ADL_P_PCIE_RP3 0x463d +#define PCI_DID_INTEL_ADL_P_PCIE_RP4 0x462d #define PCI_DID_INTEL_ADP_P_PCIE_RP1 0x51b8 #define PCI_DID_INTEL_ADP_P_PCIE_RP2 0x51b9 @@ -4276,6 +4277,8 @@ #define PCI_DID_INTEL_ADL_N_GT1 0x46D0 #define PCI_DID_INTEL_ADL_N_GT2 0x46D1 #define PCI_DID_INTEL_ADL_N_GT3 0x46D2 +#define PCI_DID_INTEL_ADL_N_GT4 0x46D3 +#define PCI_DID_INTEL_ADL_N_GT5 0x46D4 #define PCI_DID_INTEL_MTL_M_GT2 0x7d40 #define PCI_DID_INTEL_MTL_P_GT2_1 0x7d45 #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 @@ -4290,6 +4293,8 @@ #define PCI_DID_INTEL_RPL_S_GT1_1 0xa780 #define PCI_DID_INTEL_RPL_S_GT1_2 0xa782 #define PCI_DID_INTEL_RPL_S_GT1_3 0xa783 +#define PCI_DID_INTEL_RPL_S_GT1_4 0xa792 +#define PCI_DID_INTEL_RPL_S_GT1_5 0xa793 #define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 @@ -4444,6 +4449,7 @@ #define PCI_DID_INTEL_RPL_S_ID_3 0xa703 #define PCI_DID_INTEL_RPL_S_ID_4 0xa704 #define PCI_DID_INTEL_RPL_S_ID_5 0xa705 +#define PCI_DID_INTEL_RPL_S_ID_6 0xa740 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index a5e8ec3014b..76ab55378a4 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -4,6 +4,12 @@ #ifndef __EFI_DATATYPE_H__ #define __EFI_DATATYPE_H__ +/* + * Make sure NULL is defined before including EDK2 headers. Otherwise, Base.h + * defines it causing to fail on redefinition. + */ +#include + /* * EDK2 EFIAPI macro definition relies on compiler flags such as __GNUC__ which * is not working well when included by coreboot. While it has no side-effect on diff --git a/src/include/smbios.h b/src/include/smbios.h index fd44e098d4e..1446d22a25e 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -90,6 +90,7 @@ const char *smbios_chassis_version(void); const char *smbios_chassis_serial_number(void); const char *smbios_processor_serial_number(void); u8 smbios_chassis_power_cords(void); +const char *smbios_chassis_sku(void); /* This string could be filled late in payload. */ void smbios_type0_bios_version(uintptr_t address); @@ -122,7 +123,9 @@ int smbios_write_type8(unsigned long *current, int *handle, #define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) #define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) +#define BIOS_EXT2_CHARACTERISTICS_BIOS_BOOT (1 << 1) #define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) +#define BIOS_EXT2_CHARACTERISTICS_UEFI (1 << 3) #define BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING (1 << 3) #define BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING (1 << 4) @@ -1201,7 +1204,7 @@ typedef enum { SMBIOS_DEVICE_TYPE_UFS, } smbios_onboard_device_type; -#define SMBIOS_DEVICE_TYPE_COUNT 10 +#define SMBIOS_DEVICE_TYPE_COUNT 16 struct smbios_type41 { struct smbios_header header; diff --git a/src/include/smmstore.h b/src/include/smmstore.h index 6805cbc0696..202e681ab9f 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -21,6 +21,9 @@ #define SMMSTORE_CMD_RAW_WRITE 6 #define SMMSTORE_CMD_RAW_CLEAR 7 +/* Used by capsule updates as a standalone command or modifier to v2 commands */ +#define SMMSTORE_CMD_USE_FULL_FLASH 0x80 + /* Version 1 */ struct smmstore_params_read { void *buf; @@ -117,6 +120,8 @@ int smmstore_get_info(struct smmstore_params_info *info); #endif struct region_device; int smmstore_lookup_region(struct region_device *rstore); +/* Returns 0 if normal parsing should continue, 1 otherwise */ +int smmstore_preprocess_cmd(uint8_t *cmd, void *param); /* Advertise SMMSTORE v2 support */ struct lb_header; diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 434d674755a..d9fffe89c38 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -9,6 +9,7 @@ #define SPD_PAGE_LEN 256 #define SPD_PAGE_LEN_DDR4 512 +#define SPD_LEN_DDR5 1024 #define SPD_PAGE_0 (0x6C >> 1) #define SPD_PAGE_1 (0x6E >> 1) #define SPD_DRAM_TYPE 2 @@ -36,6 +37,18 @@ #define DDR4_SPD_PART_OFF 329 #define DDR4_SPD_PART_LEN 20 #define DDR4_SPD_SN_OFF 325 +#define MAX_SPD_PAGE_SIZE_SPD5 128 +#define MAX_SPD_SIZE (SPD_PAGE_LEN * 4) +#define SPD_HUB_MEMREG(addr) ((u8)(0x80 | (addr))) +#define SPD5_MR11 0x0B +#define SPD5_MR0 0x00 +#define SPD5_MEMREG_REG(addr) ((u8)((~0x80) & (addr))) +#define SPD5_MR0_SPD5_HUB_DEV 0x51 + +struct spd_offset_table { + u16 start; /* Offset 0 */ + u16 end; /* Offset 2 */ +}; struct spd_block { u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ diff --git a/src/include/version.h b/src/include/version.h index 926756a5345..1698e371b38 100644 --- a/src/include/version.h +++ b/src/include/version.h @@ -3,6 +3,12 @@ #ifndef VERSION_H #define VERSION_H +/* Dasharo version */ +extern const char dasharo_version[]; +extern const unsigned int dasharo_major_revision; +extern const unsigned int dasharo_minor_revision; +extern const unsigned int dasharo_patch_revision; + /* coreboot Version */ extern const char coreboot_version[]; extern const char coreboot_extra_version[]; diff --git a/src/lib/Kconfig.cbfs_verification b/src/lib/Kconfig.cbfs_verification index 6482e06b200..5e87a4f7c73 100644 --- a/src/lib/Kconfig.cbfs_verification +++ b/src/lib/Kconfig.cbfs_verification @@ -26,7 +26,7 @@ config TOCTOU_SAFETY depends on !NO_CBFS_MCACHE depends on !USE_OPTION_TABLE && !FSP_CAR # Known to access CBFS before CBMEM init depends on !VBOOT || VBOOT_CBFS_INTEGRATION - depends on NO_XIP_EARLY_STAGES + depends on NO_XIP_EARLY_STAGES || INTEL_CBNT_SUPPORT help Say yes here to eliminate time-of-check vs. time-of-use vulnerabilities for CBFS verification. This means that data from flash must be verified diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 03624bf2d7b..df34594a53c 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -189,9 +189,9 @@ static bool cbfs_file_hash_mismatch(const void *buffer, size_t size, struct vb2_hash calculated_hash; /* No need to re-hash file if we already have it from verification. */ - if (!hash || hash->algo != TPM_MEASURE_ALGO) { + if (!hash || hash->algo != tpm_log_alg()) { if (vb2_hash_calculate(vboot_hwcrypto_allowed(), buffer, size, - TPM_MEASURE_ALGO, &calculated_hash)) + tpm_log_alg(), &calculated_hash)) hash = NULL; else hash = &calculated_hash; @@ -481,6 +481,7 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, struct region_device rdev; bool preload_successful = false; union cbfs_mdata mdata; + bool skip_verification = false; DEBUG("%s(name='%s', alloc=%p(%p), force_ro=%s, type=%d)\n", __func__, name, allocator, arg, force_ro ? "true" : "false", type ? *type : -1); @@ -503,7 +504,14 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, if (!force_ro && get_preload_rdev(&rdev, name) == CB_SUCCESS) preload_successful = true; - void *ret = do_alloc(&mdata, &rdev, allocator, arg, size_out, false); + /* + * Bootblock will never have its hash due to how CBFS_VERIFICATION works. + * Skip its verification to let CRTM initialization pass. + */ + if (type && *type == CBFS_TYPE_BOOTBLOCK) + skip_verification = true; + + void *ret = do_alloc(&mdata, &rdev, allocator, arg, size_out, skip_verification); /* When using cbfs_preload we need to free the preload buffer after populating the * destination buffer. We know we must have a mem_rdev here, so extra mmap is fine. */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3902c88eff5..1c126a7a7fe 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -274,6 +274,7 @@ static void add_cbmem_pointers(struct lb_header *header) {CBMEM_ID_FMAP, LB_TAG_FMAP}, {CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF}, {CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO}, + {CBMEM_ID_TIANOCORE_LOGO, LB_TAG_LOGO}, }; int i; @@ -422,6 +423,37 @@ void __weak lb_board(struct lb_header *header) { /* NOOP */ } */ void __weak lb_spi_flash(struct lb_header *header) { /* NOOP */ } + +/* + * Allocator for bootlogo that prepends a header to the logo CBMEM entry + */ +static void *logo_cbmem_allocator(void *arg, size_t size, const union cbfs_mdata *unused) +{ + struct bootlogo_header header; + void *logo_loc; + + header.size = size; + logo_loc = cbmem_entry_start(cbmem_entry_add((uintptr_t)arg, size + sizeof(header))); + memcpy(logo_loc, &header, sizeof(header)); + return logo_loc + sizeof(header); +} + +/* + * Loads the logo bitmap file from the BOOTSPLASH fmap region into CBMEM + */ +static void tianocore_logo_load(int ignored) +{ + size_t logo_size; + + cbfs_unverified_area_alloc("BOOTSPLASH", + "logo.bmp", + logo_cbmem_allocator, + (void *)CBMEM_ID_TIANOCORE_LOGO, + &logo_size); +} + +CBMEM_READY_HOOK(tianocore_logo_load); + static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) { diff --git a/src/lib/smbios.c b/src/lib/smbios.c index 9cee637b695..85fffe49082 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -391,8 +391,8 @@ static int smbios_write_type0(unsigned long *current, int handle) else t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, MiB); - t->system_bios_major_release = coreboot_major_revision; - t->system_bios_minor_release = coreboot_minor_revision; + t->system_bios_major_release = dasharo_major_revision; + t->system_bios_minor_release = dasharo_minor_revision; smbios_ec_revision(&t->ec_major_release, &t->ec_minor_release); @@ -408,6 +408,13 @@ static int smbios_write_type0(unsigned long *current, int handle) t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI; t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET; + + if (CONFIG(PAYLOAD_SEABIOS)) + t->bios_characteristics_ext2 |= BIOS_EXT2_CHARACTERISTICS_BIOS_BOOT; + + if (CONFIG(PAYLOAD_EDK2)) + t->bios_characteristics_ext2 |= BIOS_EXT2_CHARACTERISTICS_UEFI; + const int len = smbios_full_table_len(&t->header, t->eos); *current += len; return len; @@ -507,6 +514,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->asset_tag_number = smbios_add_string(t->eos, smbios_mainboard_asset_tag()); t->version = smbios_add_string(t->eos, smbios_chassis_version()); t->serial_number = smbios_add_string(t->eos, smbios_chassis_serial_number()); + t->sku_number = smbios_add_string(t->eos, smbios_chassis_sku()); const int len = smbios_full_table_len(&t->header, t->eos); *current += len; return len; diff --git a/src/lib/smbios_defaults.c b/src/lib/smbios_defaults.c index 0ad6442a4f4..83e6609288c 100644 --- a/src/lib/smbios_defaults.c +++ b/src/lib/smbios_defaults.c @@ -162,3 +162,8 @@ __weak u8 smbios_chassis_power_cords(void) { return 1; } + +__weak const char *smbios_chassis_sku(void) +{ + return ""; +} diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index dff6ede8609..1398da6fb78 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -209,7 +209,9 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk) dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE); - if (dram_type == SPD_DRAM_DDR4) + if (dram_type == SPD_DRAM_DDR5) + blk->len = SPD_LEN_DDR5; + else if (dram_type == SPD_DRAM_DDR4) blk->len = SPD_PAGE_LEN_DDR4; else blk->len = SPD_PAGE_LEN; diff --git a/src/lib/version.c b/src/lib/version.c index 43d6a458212..49e6647c1e2 100644 --- a/src/lib/version.c +++ b/src/lib/version.c @@ -18,6 +18,22 @@ #define COREBOOT_EXTRA_VERSION "" #endif +#ifndef DASHARO_VERSION +#define DASHARO_VERSION "*INVALID*" +#endif + +#ifndef DASHARO_MAJOR_VERSION +#define DASHARO_MAJOR_VERSION 0 +#endif + +#ifndef DASHARO_MINOR_VERSION +#define DASHARO_MINOR_VERSION 0 +#endif + +#ifndef DASHARO_PATCH_VERSION +#define DASHARO_PATCH_VERSION 0 +#endif + const char coreboot_version[] = COREBOOT_VERSION; const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION; const char coreboot_build[] = COREBOOT_BUILD; @@ -25,6 +41,11 @@ const unsigned int coreboot_version_timestamp = COREBOOT_VERSION_TIMESTAMP; const unsigned int coreboot_major_revision = COREBOOT_MAJOR_VERSION; const unsigned int coreboot_minor_revision = COREBOOT_MINOR_VERSION; +const char dasharo_version[] = DASHARO_VERSION; +const unsigned int dasharo_major_revision = DASHARO_MAJOR_VERSION; +const unsigned int dasharo_minor_revision = DASHARO_MINOR_VERSION; +const unsigned int dasharo_patch_revision = DASHARO_PATCH_VERSION; + const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME; const char coreboot_dmi_date[] = COREBOOT_DMI_DATE; diff --git a/src/mainboard/asrock/spc741d8/Kconfig b/src/mainboard/asrock/spc741d8/Kconfig new file mode 100644 index 00000000000..fe2f9227705 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/Kconfig @@ -0,0 +1,40 @@ +if BOARD_ASROCK_SPC741D8 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select IPMI_OCP + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 + select PLATFORM_USES_FSP2_X86_32 + select SOC_INTEL_SAPPHIRERAPIDS_SP + select SUPERIO_ASPEED_AST2400 + select DRIVERS_ASPEED_AST2050 + select SUPERIO_NUVOTON_NCT6791D + select HAVE_ACPI_TABLES + select OCP_EWL + select HAVE_INTEL_FSP_REPO + select HAVE_X86_64_SUPPORT + select PAGE_TABLES_IN_CBFS + select SOC_INTEL_COMMON_BLOCK_SPI + +config MAINBOARD_DIR + default "asrock/spc741d8" + +config MAINBOARD_PART_NUMBER + default "SPC741D8-2L2T/BCM" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config FSP_FD_PATH + default "3rdparty/fsp/EagleStreamFspBinPkg/Fsp.fd" + +config MAX_SOCKET + int + default 1 + +endif diff --git a/src/mainboard/asrock/spc741d8/Kconfig.name b/src/mainboard/asrock/spc741d8/Kconfig.name new file mode 100644 index 00000000000..7723156609a --- /dev/null +++ b/src/mainboard/asrock/spc741d8/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_SPC741D8 + bool "SPC741D8-2L2T/BCM" diff --git a/src/mainboard/asrock/spc741d8/Makefile.mk b/src/mainboard/asrock/spc741d8/Makefile.mk new file mode 100644 index 00000000000..b28d73c27a7 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +romstage-y += util.c +ramstage-y += ramstage.c +ramstage-y += util.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/asrock/spc741d8/acpi/platform.asl b/src/mainboard/asrock/spc741d8/acpi/platform.asl new file mode 100644 index 00000000000..4853874f8c0 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/acpi/platform.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ +#include +#include + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/asrock/spc741d8/board.fmd b/src/mainboard/asrock/spc741d8/board.fmd new file mode 100644 index 00000000000..bc31f00177c --- /dev/null +++ b/src/mainboard/asrock/spc741d8/board.fmd @@ -0,0 +1,18 @@ +FLASH 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + # SI_GBE@0x1000 0x2000 + # SI_ME@0x3000 0x2fed000 + SI_ME@0x1000 0x2fef000 + SI_PT@0x2ff0000 0x10000 + } + RW_MRC_CACHE@0x3000000 0x10000 + SMMSTORE(PRESERVE) 256K + BOOTSPLASH(CBFS) 1M + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + # For CONSOLE_SPI_FLASH support + CONSOLE 0x20000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/asrock/spc741d8/board_info.txt b/src/mainboard/asrock/spc741d8/board_info.txt new file mode 100644 index 00000000000..ae7ac07b9a7 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: ASRock Rack +Board name: SPC741D8-2L2T/BCM +Category: server +ROM protocol: SPI +ROM package: SOIC-16 +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/asrock/spc741d8/bootblock.c b/src/mainboard/asrock/spc741d8/bootblock.c new file mode 100644 index 00000000000..eff2b728d1a --- /dev/null +++ b/src/mainboard/asrock/spc741d8/bootblock.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +void bootblock_mainboard_early_init(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + */ + const uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE); + const uint16_t lpcioe = (LPC_IOE_EC_4E_4F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN); + + /* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); + + /* Enable com1 (0x3f8), com2 (0x2f8) and superio (0x4e) */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); + pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); + /* AST2600 is on eSPI CS1# */ + pci_write_config16(PCH_DEV_LPC, ESPI_CS1_ENABLE, lpcioe); + + /* + * Disable the Nuvoton NCT6791D SuperIO UART1. It is enabled by + * default, but the AST2600's is connected to the serial port. + */ + const pnp_devfn_t nvt_serial_dev = PNP_DEV(0x2E, NCT6791D_SP1); + nuvoton_pnp_enter_conf_state(nvt_serial_dev); + pnp_set_logical_device(nvt_serial_dev); + pnp_set_enable(nvt_serial_dev, 0); + nuvoton_pnp_exit_conf_state(nvt_serial_dev); + + /* Enable AST2600 SuperIO UART1 */ + const pnp_devfn_t ast_serial_dev = PNP_DEV(0x4E, AST2400_SUART1); + aspeed_enable_serial(ast_serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/spc741d8/devicetree.cb b/src/mainboard/asrock/spc741d8/devicetree.cb new file mode 100644 index 00000000000..0aef44c1de8 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/devicetree.cb @@ -0,0 +1,31 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/spr + device domain 0 on + device pci 1f.0 on # Intel device 1b81: PCH eSPI controller + chip superio/common + device pnp 4e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 4e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 0x04 + end + device pnp 4e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 0x03 + end + end + end + end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + end + end +end diff --git a/src/mainboard/asrock/spc741d8/dsdt.asl b/src/mainboard/asrock/spc741d8/dsdt.asl new file mode 100644 index 00000000000..817c61bff98 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include "acpi/platform.asl" + + #include + + #include + + #include + + // LPC related entries + Scope (\_SB.PC00) + { + #include + } +} diff --git a/src/mainboard/asrock/spc741d8/gpio.h b/src/mainboard/asrock/spc741d8/gpio.h new file mode 100644 index 00000000000..78c93f8889d --- /dev/null +++ b/src/mainboard/asrock/spc741d8/gpio.h @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPPC_A ------- */ + PAD_CFG_NF(GPPC_A0, NONE, RSMRST, NF1), /* ESPI_ALERT0_N */ + PAD_CFG_NF(GPPC_A1, NONE, RSMRST, NF1), /* ESPI_ALERT1_N */ + PAD_CFG_NF(GPPC_A2, NONE, RSMRST, NF1), /* ESPI_IO_0 */ + PAD_CFG_NF(GPPC_A3, NONE, RSMRST, NF1), /* ESPI_IO_1 */ + PAD_CFG_NF(GPPC_A4, NONE, RSMRST, NF1), /* ESPI_IO_2 */ + PAD_CFG_NF(GPPC_A5, NONE, RSMRST, NF1), /* ESPI_IO_3 */ + PAD_CFG_NF(GPPC_A6, NONE, RSMRST, NF1), /* ESPI_CS0_N */ + PAD_CFG_NF(GPPC_A7, NONE, RSMRST, NF1), /* ESPI_CS1_N */ + PAD_CFG_NF(GPPC_A8, NONE, RSMRST, NF1), /* ESPI_RESET_N */ + PAD_CFG_NF(GPPC_A9, NONE, RSMRST, NF1), /* ESPI_CLK */ + PAD_CFG_GPI_TRIG_OWN(GPPC_A10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_A11, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_A12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPPC_A13, 0, RSMRST), /* GPIO */ + PAD_NC(GPPC_A14, NONE), /* GPIO */ + PAD_NC(GPPC_A15, NONE), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPPC_A16, 0, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_A17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_A18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_A19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPPC_B ------- */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B1, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPPC_B5, NONE, RSMRST, NF1), /* USB2_OC0_N */ + PAD_CFG_NF(GPPC_B6, NONE, RSMRST, NF1), /* USB2_OC1_N */ + PAD_CFG_NF(GPPC_B7, NONE, RSMRST, NF1), /* USB2_OC2_N */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPPC_B11, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPPC_B12, NONE, DEEP, NF4), /* 1P8_PTI_DATA5 */ + PAD_CFG_NF(GPPC_B13, NONE, DEEP, NF4), /* 1P8_PTI_DATA6 */ + PAD_CFG_NF(GPPC_B14, NONE, DEEP, NF4), /* 1P8_PTI_DATA7 */ + PAD_CFG_NF(GPPC_B15, NONE, DEEP, NF4), /* 1P8_PTI_DATA8 */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B20, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPPC_B22, 0, RSMRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_B23, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPPC_S ------- */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPPC_S1, NONE, DEEP, NF1), /* SPRK */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S3, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S6, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPPC_S7, NONE, RSMRST, NF1), /* SUSACK_N */ + PAD_CFG_NF(GPPC_S8, NONE, RSMRST, NF1), /* NMI_N */ + PAD_CFG_GPI_SMI(GPPC_S9, NONE, DEEP, LEVEL, INVERT), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S11, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPPC_C ------- */ + /* GPPC_C0 - RESERVED */ + /* GPPC_C1 - RESERVED */ + PAD_CFG_NF(GPPC_C2, NONE, DEEP, NF1), /* ME_SML0ALERT_N */ + PAD_CFG_GPI_TRIG_OWN(GPPC_C3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_C4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPPC_C5, 1, PLTRST), /* GPIO */ + /* GPPC_C6 - RESERVED */ + /* GPPC_C7 - RESERVED */ + /* GPPC_C8 - RESERVED */ + PAD_NC(GPPC_C9, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_C10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPPC_C11 - RESERVED */ + /* GPPC_C12 - RESERVED */ + /* GPPC_C13 - RESERVED */ + /* GPPC_C14 - RESERVED */ + PAD_NC(GPPC_C15, NONE), /* GPIO */ + PAD_NC(GPPC_C16, NONE), /* GPIO */ + PAD_CFG_GPO(GPPC_C17, 0, RSMRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_C18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_C19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_C20, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_SCI(GPPC_C21, NONE, DEEP, LEVEL, INVERT), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - RESERVED */ + /* GPP_D1 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_D8, NONE, RSMRST, NF1), /* CRASHLOG_TRIG_N */ + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_D11, NONE, RSMRST, NF1), /* PLTRST_N */ + PAD_CFG_NF(GPP_D12, NONE, RSMRST, NF1), /* PCHHOT_N */ + /* GPP_D13 - RESERVED */ + PAD_CFG_NF(GPP_D14, NONE, RSMRST, NF1), /* ADR_TRIGGER */ + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_D16, NONE, RSMRST, NF1), /* ADR_ACK */ + /* GPP_D17 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_D21, NONE, RSMRST, NF1), /* GLB_RST_WARN_N */ + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_NMI(GPP_E0, NONE, PLTRST, LEVEL, INVERT), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_E2, NONE, RSMRST, NF1), /* SATA1_XPCIE_2 */ + PAD_CFG_NF(GPP_E3, NONE, RSMRST, NF1), /* SATA1_XPCIE_3 */ + PAD_CFG_NF(GPP_E4, NONE, RSMRST, NF1), /* SATA0_XPCIE_2 */ + PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA0_XPCIE_1 */ + PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA0_USB3_XPCIE_0 */ + PAD_CFG_NF(GPP_E7, NONE, RSMRST, NF1), /* SATA0_USB3_XPCIE_1 */ + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF2), /* SATA0_LED_N */ + PAD_CFG_GPI_TRIG_OWN(GPP_E9, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPPC_H ------- */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPPC_H1 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H6, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H11, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H13, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPPC_H15, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPPC_H18, 0, PLTRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), /* CPUPWRGD */ + /* GPP_J1 - RESERVED */ + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), /* PLTRST_CPU_N */ + PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), /* TRIGGER0_N */ + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), /* TRIGGER1_N */ + /* GPP_J5 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, DEEP, OFF, ACPI), /* GPIO */ + /* GPP_J8 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J12, UP_20K, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J13, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J14, UP_20K, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_J15, UP_20K, DEEP, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I1, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I11, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I13, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_L ------- */ + /* GPP_L0 - RESERVED */ + /* GPP_L1 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + /* GPP_L4 - RESERVED */ + PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_M ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M4, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M9, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M10, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M12, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M13, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M14, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M15, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M16, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_M17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Group GPP_N ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_N0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_N1, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_N2, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_N3, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_N4, NONE, RSMRST, OFF, ACPI), /* GPIO */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/asrock/spc741d8/include/mainboard_iio.h b/src/mainboard/asrock/spc741d8/include/mainboard_iio.h new file mode 100644 index 00000000000..940e9331c46 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/include/mainboard_iio.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _MAINBOARD_IIO_H_ +#define _MAINBOARD_IIO_H_ + +#include +#include + +/* For now only set 3 fields and hard-coded others, should be extended in the future */ +#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ + { \ + .SLOTEIP = 0, \ + .SLOTHPCAP = 0, \ + .SLOTHPSUP = 0, \ + .SLOTPIP = 0, \ + .SLOTAIP = 0, \ + .SLOTMRLSP = 0, \ + .SLOTPCP = 0, \ + .SLOTABP = 0, \ + .SLOTIMP = slotimp, \ + .SLOTSPLS = 0, \ + .SLOTSPLV = 0, \ + .SLOTPSP = slotpsp, \ + .VppEnabled = 0, \ + .VppPort = 0, \ + .VppAddress = 0, \ + .MuxAddress = 0, \ + .ChannelID = 0, \ + .PciePortEnable = 1, \ + .PEXPHIDE = pexphide, \ + .HidePEXPMenu = 0, \ + .PciePortOwnership = 0, \ + .RetimerConnectCount = 0, \ + .PcieMaxPayload = 0x7, \ + .PciePortLinkSpeed = 0, \ + .DfxDnTxPresetGen3 = 0xFF \ + } + +#define CFG_UPD_PCIE_PORT_DISABLED CFG_UPD_PCIE_PORT(1, 0, 0) + +/* + * SPC741D8-2L2T IIO PCIe Port Table + */ +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY iio_pci_port[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { + { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(0, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 */ + CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + /* IOU1 (PE1): array index 9 ~ 16 */ + CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + /* IOU2 (PE2): array index 17 ~ 24 */ + CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + /* IOU3 (PE3): array index 25 ~ 32 */ + CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + /* IOU4 (PE4): array index 33 ~ 40 */ + CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT(0, 1, 37), /* 59:05.0 */ + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + CFG_UPD_PCIE_PORT_DISABLED, + }, +}; + +static const UINT8 iio_bifur[CONFIG_MAX_SOCKET][5] = { + // Note: When changing, also update port configurations above. + { + IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE3 */ + IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE5 */ + IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE1 (farthest from CPU) */ + IIO_BIFURCATE_xxxxxx16, /* physical slot PCIE7 (closest to CPU) */ + IIO_BIFURCATE_xxx8xxx8, /* MCIO */ + }, +}; +#endif /* _MAINBOARD_IIO_H_ */ diff --git a/src/mainboard/asrock/spc741d8/ramstage.c b/src/mainboard/asrock/spc741d8/ramstage.c new file mode 100644 index 00000000000..e622c9647a9 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/ramstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + /* configure Emmitsburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size) +{ + soc_ubox_store_resources(slots, size); +} + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + const u8 so = dimm->soc_num; + const u8 ch = dimm->channel_num; + const u8 mm = dimm->dimm_num; + + // generate locator strings matching OEM firmware (CPU1_DIMM_A1, CPU1_DIMM_B1, ..., CPU1_DIMM_H1) + char dev_loc[40] = { "\x00" }; + snprintf(dev_loc, sizeof(dev_loc), "CPU%u_DIMM_%c%u", so + 1, 'A' + ch, mm + 1); + t->device_locator = smbios_add_string(t->eos, dev_loc); + + // memory controllers are numbered 0-3 (e.g. "NODE 0" used for DIMMs A1 and B1, "NODE 1" for C1 and D1, ...) + char bnk_loc[40] = { "\x00" }; + snprintf(bnk_loc, sizeof(bnk_loc), "NODE %u", ch / 2); + t->bank_locator = smbios_add_string(t->eos, bnk_loc); +} + +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count) +{ + // GENERIC_LINEAR_FRAMEBUFFER enables I2C compilation for the Aspeed VGA controller. + // This is not supported (or needed) on the SPC741D8, so stub the function. + return -1; +} diff --git a/src/mainboard/asrock/spc741d8/romstage.c b/src/mainboard/asrock/spc741d8/romstage.c new file mode 100644 index 00000000000..785a905241b --- /dev/null +++ b/src/mainboard/asrock/spc741d8/romstage.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void mainboard_ewl_check(void) +{ + get_ewl(); +} + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + /* Set socket 0 IIO PCIe PE0,PE1,PE2,PE3 to CXL mode */ + mupd->FspmConfig.IioPcieSubSystemMode0[0] = IIO_MODE_CXL; + mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL; + mupd->FspmConfig.IioPcieSubSystemMode2[0] = IIO_MODE_CXL; + mupd->FspmConfig.IioPcieSubSystemMode3[0] = IIO_MODE_CXL; + + mupd->FspmConfig.DfxCxlHeaderBypass = 0; + mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED; + + mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; /* ms */ +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* Send FSP log message to main serial port */ + mupd->FspmConfig.SerialIoUartDebugEnable = 1; + mupd->FspmConfig.SerialIoUartDebugIoBase = CONFIG_TTYS0_BASE; + + /* Set Rank Margin Tool to disable. */ + mupd->FspmConfig.EnableRMT = 0x0; + /* Enable - Portions of memory reference code will be skipped + * when possible to increase boot speed on warm boots. + * Disable - Disables this feature. + * Auto - Sets it to the MRC default setting. + */ + mupd->FspmConfig.AttemptFastBoot = 0x1; + mupd->FspmConfig.AttemptFastBootCold = 0x1; + + /* Set Adv MemTest Option to 0. */ + mupd->FspmConfig.AdvMemTestOptions = 0x0; + /* Set MRC Promote Warnings to disable. + Determines if MRC warnings are promoted to system level. */ + mupd->FspmConfig.promoteMrcWarnings = 0x0; + /* Set Promote Warnings to disable. + Determines if warnings are promoted to system level. */ + mupd->FspmConfig.promoteWarnings = 0x0; + soc_config_iio(mupd, iio_pci_port, iio_bifur); + mainboard_config_iio(mupd); +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + if (socket >= CONFIG_MAX_SOCKET) + return false; + // SPC741D8 supports 8 channels with 1 DIMM each + if (channel >= 8) + return false; + if (dimm >= 1) + return false; + + return true; +} diff --git a/src/mainboard/asrock/spc741d8/util.c b/src/mainboard/asrock/spc741d8/util.c new file mode 100644 index 00000000000..ca27f725c35 --- /dev/null +++ b/src/mainboard/asrock/spc741d8/util.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#if CONFIG(SOC_INTEL_HAS_CXL) +enum xeonsp_cxl_mode get_cxl_mode(void) +{ + return XEONSP_CXL_SYS_MEM; +} +#endif diff --git a/src/mainboard/bytedance/bd_egs/romstage.c b/src/mainboard/bytedance/bd_egs/romstage.c index e1e976b7c5d..7f20c2a956d 100644 --- a/src/mainboard/bytedance/bd_egs/romstage.c +++ b/src/mainboard/bytedance/bd_egs/romstage.c @@ -5,6 +5,7 @@ #include #include #include +#include static void mainboard_config_iio(FSPM_UPD *mupd) { diff --git a/src/mainboard/clevo/adl-p/Kconfig b/src/mainboard/clevo/adl-p/Kconfig new file mode 100644 index 00000000000..4eeb6309c2c --- /dev/null +++ b/src/mainboard/clevo/adl-p/Kconfig @@ -0,0 +1,134 @@ +config BOARD_CLEVO_ADLP_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select EC_DASHARO_EC + select EC_ACPI + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_CLEVO_NS50PU_BASE + bool + select BOARD_CLEVO_ADLP_COMMON + select DRIVERS_GENERIC_BAYHUB_LV2 + +config BOARD_CLEVO_NS50PU + bool + select BOARD_CLEVO_NS50PU_BASE + +config BOARD_CLEVO_NV40PZ_BASE + bool + select BOARD_CLEVO_ADLP_COMMON + select EC_DASHARO_EC_DGPU + select DRIVERS_GENERIC_BAYHUB_LV2 + +config BOARD_CLEVO_NV40PZ + bool + select BOARD_CLEVO_NV40PZ_BASE + +if BOARD_CLEVO_ADLP_COMMON + +config MAINBOARD_DIR + default "clevo/adl-p" + +config VARIANT_DIR + default "ns50pu" if BOARD_CLEVO_NS50PU_BASE + default "nv40pz" if BOARD_CLEVO_NV40PZ_BASE + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + default "ns50pu" if BOARD_CLEVO_NS50PU_BASE + default "nv40pz" if BOARD_CLEVO_NV40PZ_BASE + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "NS5x_NS7xPU" if BOARD_CLEVO_NS50PU_BASE + default "NV4xPZ" if BOARD_CLEVO_NV40PZ_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" + +config MAINBOARD_VERSION + default "ns50pu" if BOARD_CLEVO_NS50PU_BASE + default "nv40pz" if BOARD_CLEVO_NV40PZ_BASE + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match stock firmware + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_SPD_SIZE + default 512 + +config ONBOARD_VGA_IS_PRIMARY + default y + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 0 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_ENABLE_CBFS_FALLBACK + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config VBOOT_VBNV_OFFSET + default 0x28 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +config TPM_PIRQ + default 0x27 # GPP_E1 + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config VBOOT_FWID_VERSION + default "\$(CONFIG_LOCALVERSION)" + +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 20 + +endif + +endif diff --git a/src/mainboard/clevo/adl-p/Kconfig.name b/src/mainboard/clevo/adl-p/Kconfig.name new file mode 100644 index 00000000000..fa3a0fd11a8 --- /dev/null +++ b/src/mainboard/clevo/adl-p/Kconfig.name @@ -0,0 +1,7 @@ +comment "Alder Lake P" + +config BOARD_CLEVO_NS50PU + bool "NS5xPU / NS7xPU" + +config BOARD_CLEVO_NV40PZ + bool "NV4xPZ" diff --git a/src/mainboard/clevo/adl-p/Makefile.mk b/src/mainboard/clevo/adl-p/Makefile.mk new file mode 100644 index 00000000000..771d702af51 --- /dev/null +++ b/src/mainboard/clevo/adl-p/Makefile.mk @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c + +SPD_SOURCES = samsung-P4AAF165WA-BCWDE diff --git a/src/mainboard/clevo/adl-p/acpi/backlight.asl b/src/mainboard/clevo/adl-p/acpi/backlight.asl new file mode 100644 index 00000000000..01fa83ea610 --- /dev/null +++ b/src/mainboard/clevo/adl-p/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/clevo/adl-p/acpi/mainboard.asl b/src/mainboard/clevo/adl-p/acpi/mainboard.asl new file mode 100644 index 00000000000..da2a78c694a --- /dev/null +++ b/src/mainboard/clevo/adl-p/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#define CPU_CRIT_TEMP 100 +#define GPU_CRIT_TEMP 105 +#include + +Scope (\_SB) { + #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } +} + +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +If (S0IX == 0) { + Name(\_S3, Package(){0x5,0x0,0x0,0x0}) +} Else { + Name(\_S1, Package(){0x1,0x0,0x0,0x0}) +} +#if !CONFIG(DISABLE_ACPI_HIBERNATE) +Name(\_S4, Package(){0x6,0x0,0x0,0x0}) +#endif +Name(\_S5, Package(){0x7,0x0,0x0,0x0}) diff --git a/src/mainboard/clevo/adl-p/acpi/sleep.asl b/src/mainboard/clevo/adl-p/acpi/sleep.asl new file mode 100644 index 00000000000..4e7d79798dd --- /dev/null +++ b/src/mainboard/clevo/adl-p/acpi/sleep.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + + /* Bring system out of TC cold before enter Sx */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* HACK: Inform EC to apply PMC hack for S0ix issue */ + \_SB.PCI0.LPCB.EC0.PTS (0) + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + /* Bring system out of TC cold */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () + } +} diff --git a/src/mainboard/clevo/adl-p/acpi/touchpad.asl b/src/mainboard/clevo/adl-p/acpi/touchpad.asl new file mode 100644 index 00000000000..0ac407185f4 --- /dev/null +++ b/src/mainboard/clevo/adl-p/acpi/touchpad.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External (\_SB.PCI0.I2C0.H038, DeviceObj) +External (\_SB.PCI0.I2C0.H038._STA, IntObj) + +External (\_SB.PCI0.I2C0.H015, DeviceObj) +External (\_SB.PCI0.I2C0.H015._STA, IntObj) + +Method (TPTG, 0, Serialized) +{ + If (CondRefOf (\_SB.PCI0.I2C0.H038)) { + If (\_SB.PCI0.I2C0.H038._STA == Zero) { + \_SB.PCI0.I2C0.H038._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H038._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H038, One) + } + + If (CondRefOf (\_SB.PCI0.I2C0.H015)) { + If (\_SB.PCI0.I2C0.H015._STA == Zero) { + \_SB.PCI0.I2C0.H015._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H015._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H015, One) + } +} diff --git a/src/mainboard/clevo/adl-p/board_info.txt b/src/mainboard/clevo/adl-p/board_info.txt new file mode 100644 index 00000000000..5220e452c84 --- /dev/null +++ b/src/mainboard/clevo/adl-p/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Clevo +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/adl-p/bootblock.c b/src/mainboard/clevo/adl-p/bootblock.c new file mode 100644 index 00000000000..8d06adc9d7f --- /dev/null +++ b/src/mainboard/clevo/adl-p/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/clevo/adl-p/cmos.default b/src/mainboard/clevo/adl-p/cmos.default new file mode 100644 index 00000000000..972deace70b --- /dev/null +++ b/src/mainboard/clevo/adl-p/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable +kbl_brightness=0xff +kbl_color=0x00ffffff diff --git a/src/mainboard/clevo/adl-p/cmos.layout b/src/mainboard/clevo/adl-p/cmos.layout new file mode 100644 index 00000000000..fa2067eb9f0 --- /dev/null +++ b/src/mainboard/clevo/adl-p/cmos.layout @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 304 r 0 reserved_memory + +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# Vboot non-volatile data +432 128 r 0 vbnv + +984 16 h 0 check_sum + +# embedded controller settings +1024 8 h 0 kbl_brightness +1032 32 h 0 kbl_color + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 431 984 diff --git a/src/mainboard/clevo/adl-p/devicetree.cb b/src/mainboard/clevo/adl-p/devicetree.cb new file mode 100644 index 00000000000..2420dd51a62 --- /dev/null +++ b/src/mainboard/clevo/adl-p/devicetree.cb @@ -0,0 +1,127 @@ +chip soc/intel/alderlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable S0ix / Modern Standby + register "s0ix_enable" = "1" + + # Enable C6 DRAM + register "enable_c6dram" = "1" + + # Thermal + register "tcc_offset" = "20" # TCC of 80C + + # Noise mitigation + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "PreWake" = "150" + + # VR configuration + # +-----------+-------+-------+---------+-------------+----------+ + # | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | + # | |(mOhms)|(mOhms)| (A) | (A) | (msec) | + # +-----------+-------+-------+---------+-------------+----------+ + # | IA | 2.3 | 2.3 | 109 | 63 | 28000 | + # +-----------+-------+-------+---------+-------------+----------+ + # | GT | 3.1 | 3.1 | 50 | 30 | 28000 | + # +-----------+-------+-------+---------+-------------+----------+ + register "domain_vr_config[VR_DOMAIN_IA]" = "{ + .vr_config_enable = 1, + .ac_loadline = 230, + .dc_loadline = 230, + .icc_max = VR_CFG_AMP(109), + .tdc_timewindow = 28000, + .tdc_currentlimit = VR_CFG_TDC_AMP(63), + }" + + register "domain_vr_config[VR_DOMAIN_GT]" = "{ + .vr_config_enable = 1, + .ac_loadline = 310, + .dc_loadline = 310, + .icc_max = VR_CFG_AMP(50), + .tdc_timewindow = 28000, + .tdc_currentlimit = VR_CFG_TDC_AMP(30), + }" + + device cpu_cluster 0 on end + device domain 0 on + device ref system_agent on end + device ref igpu on + # DDIA is eDP, DDIB is HDMI + register "ddi_portA_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref tbt_pcie_rp0 on end + device ref shared_sram on end + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref uart0 on # BIOS Debug Port + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci" + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + + device ref heci1 on end + device ref pch_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0e01" # AP/EC command + register "gen3_dec" = "0x00fc0f01" # AP/EC debug + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref hda on + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/adl-p/dsdt.asl b/src/mainboard/clevo/adl-p/dsdt.asl new file mode 100644 index 00000000000..f911aae34a2 --- /dev/null +++ b/src/mainboard/clevo/adl-p/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" + #include "acpi/touchpad.asl" +} diff --git a/src/mainboard/clevo/adl-p/fadt.c b/src/mainboard/clevo/adl-p/fadt.c new file mode 100644 index 00000000000..0967bc9a95b --- /dev/null +++ b/src/mainboard/clevo/adl-p/fadt.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + /* Control method power button (EC) */ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/clevo/adl-p/include/mainboard/gpio.h b/src/mainboard/clevo/adl-p/include/mainboard/gpio.h new file mode 100644 index 00000000000..57924a615fa --- /dev/null +++ b/src/mainboard/clevo/adl-p/include/mainboard/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/clevo/adl-p/ramstage.c b/src/mainboard/clevo/adl-p/ramstage.c new file mode 100644 index 00000000000..0c340bab811 --- /dev/null +++ b/src/mainboard/clevo/adl-p/ramstage.c @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct smfi_cmd_set_fan_curve { + uint8_t fan; + struct fan_curve curve; +} __packed; + +struct fan_curve fan_curve_silent = { + { .temp = 0, .duty = 20 }, + { .temp = 65, .duty = 25 }, + { .temp = 75, .duty = 35 }, + { .temp = 85, .duty = 100 } +}; + +struct fan_curve fan_curve_performance = { + { .temp = 0, .duty = 25 }, + { .temp = 55, .duty = 35 }, + { .temp = 75, .duty = 60 }, + { .temp = 85, .duty = 100} +}; + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +static void set_fan_curve(void) +{ + int i; + uint8_t selection = get_fan_curve_option(); + struct smfi_cmd_set_fan_curve cmd; + + switch (selection) { + case FAN_CURVE_OPTION_SILENT: + cmd.curve = fan_curve_silent; + break; + case FAN_CURVE_OPTION_PERFORMANCE: + cmd.curve = fan_curve_performance; + break; + default: + cmd.curve = fan_curve_silent; + break; + } + + for (i = 0; i < (CONFIG(EC_DASHARO_EC_DGPU) ? 2 : 1); ++i) { + cmd.fan = i; + dasharo_ec_smfi_cmd(CMD_FAN_CURVE_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); + } +} + +static void set_camera_enablement(void) +{ + bool enabled = get_camera_option(); + + dasharo_ec_smfi_cmd(CMD_CAMERA_ENABLEMENT_SET, sizeof(enabled) / sizeof(uint8_t), (uint8_t *)&enabled); +} + +static void set_battery_thresholds(void) +{ + struct battery_config bat_cfg; + + get_battery_config(&bat_cfg); + + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_START, bat_cfg.start_threshold); + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_STOP, bat_cfg.stop_threshold); +} + +static void set_power_on_ac(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_POWER_ON_AC, + 0 + }; + + cmd.value = dasharo_get_power_on_after_fail(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); +} + +static void set_usb_charge_port(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_ALWAYS_ON_USB, + 0 + }; + + cmd.value = dasharo_get_usb_port_power(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); +} + +static void mainboard_init(void *chip_info) +{ + config_t *cfg = config_of_soc(); + struct device *wlan_dev = pcidev_on_root(0x1c, 4); + struct device *cnvi_dev = pcidev_on_root(0x14, 3); + bool radio_enable = get_wireless_option(); + + printk(BIOS_DEBUG, "Wireless is %sabled\n", radio_enable ? "en" : "dis"); + + wlan_dev->enabled = radio_enable; + cnvi_dev->enabled = radio_enable; + cfg->cnvi_bt_core = radio_enable; + cfg->cnvi_bt_audio_offload = radio_enable; + cfg->usb2_ports[9].enable = radio_enable; + + dasharo_ec_smfi_cmd(CMD_WIFI_BT_ENABLEMENT_SET, 1, (uint8_t *)&radio_enable); + + mainboard_configure_gpios(); + set_fan_curve(); + set_camera_enablement(); + set_battery_thresholds(); + set_power_on_ac(); + set_usb_charge_port(); +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static uint8_t read_proprietary_ec_version(uint8_t *data) +{ + int i, result; + char ec_version[16]; + + if (!data) + return -1; + + if (send_ec_command(0x93)) + return -1; + + for (i = 0; i < 16 - 1; i++) { + + result = recv_ec_data(); + if (result != -1) + ec_version[i] = result & 0xff; + + if (ec_version[i] == '$') { + ec_version[i] = '\0'; + break; + } + } + ec_version[15] = '\0'; + + data[0] = '1'; + data[1] = '.'; + + strcpy((char *)&data[2], ec_version); + + return 0; +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ec_version[256]; + uint8_t result; + + result = dasharo_ec_read_version((uint8_t *)ec_version); + + /* If the command fails it mean we are running proprietary EC most likely */ + if (result != 0) { + printk(BIOS_ERR, "Failed to read open EC firmware version\n"); + result = read_proprietary_ec_version((uint8_t *)ec_version); + if (result == 0) + t->count = smbios_add_string(t->eos, "EC: proprietary"); + else + t->count = smbios_add_string(t->eos, "EC: unknown"); + } else { + t->count = smbios_add_string(t->eos, "EC: open-source"); + } + + if (result == 0) { + printk(BIOS_DEBUG, "EC firmware version: %s\n", ec_version); + t->count = smbios_add_string(t->eos, strconcat("EC firmware version: ", + ec_version)); + } else { + printk(BIOS_ERR, "Unable to probe EC firmware version\n"); + t->count = smbios_add_string(t->eos, "EC firmware version: unknown"); + } + +} +#endif + + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_strings = mainboard_smbios_strings; +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->CnviRfResetPinMux = 0x194CE404; // GPP_F4 + params->CnviClkreqPinMux = 0x394CE605; // GPP_F5 + + params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6 + params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7 + + // DEVSLP doesn't work due to broken board design (crossed wiring) + params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12 + params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 + + params->SataPortsSolidStateDrive[1] = 1; + + params->PcieRpEnableCpm[4] = 1; + params->PcieRpEnableCpm[5] = 1; + params->PcieRpEnableCpm[7] = 1; + params->PcieRpEnableCpm[8] = 1; + params->PcieRpEnableCpm[9] = 1; + + params->PcieRpAcsEnabled[4] = 1; + params->PcieRpAcsEnabled[5] = 1; + params->PcieRpAcsEnabled[7] = 1; + params->PcieRpAcsEnabled[8] = 1; + params->PcieRpAcsEnabled[9] = 1; + + params->PcieRpMaxPayload[4] = 1; + params->PcieRpMaxPayload[5] = 1; + params->PcieRpMaxPayload[7] = 1; + params->PcieRpMaxPayload[8] = 1; + params->PcieRpMaxPayload[9] = 1; + + params->PcieRpPmSci[4] = 1; + params->PcieRpPmSci[5] = 1; + params->PcieRpPmSci[7] = 1; + params->PcieRpPmSci[8] = 1; + params->PcieRpPmSci[9] = 1; + + params->CpuPcieRpPmSci[0] = 1; + params->CpuPcieRpEnableCpm[0] = 1; + params->CpuPcieClockGating[0] = 1; + params->CpuPciePowerGating[0] = 1; + params->CpuPcieRpMultiVcEnabled[0] = 1; + params->CpuPcieRpPeerToPeerMode[0] = 1; + params->CpuPcieRpMaxPayload[0] = 2; // 512B + params->CpuPcieRpAcsEnabled[0] = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + params->LidStatus = dasharo_ec_get_lid_state(); +} + +void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3) + config->s0ix_enable = 0; + else + config->s0ix_enable = 1; +} + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + switch (dimm->ctrlr_num) { + case 0: + t->device_locator = smbios_add_string(t->eos, "RAM1"); + break; + case 1: + t->device_locator = smbios_add_string(t->eos, "RAM2"); + break; + default: + t->device_locator = smbios_add_string(t->eos, "UNKNOWN"); + break; + } +} diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/board_info.txt b/src/mainboard/clevo/adl-p/variants/ns50pu/board_info.txt new file mode 100644 index 00000000000..119a5d914cf --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/board_info.txt @@ -0,0 +1,2 @@ +Board name: NS5x_NS7xPU +Release year: 2022 diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/data.vbt b/src/mainboard/clevo/adl-p/variants/ns50pu/data.vbt new file mode 100644 index 00000000000..93dc627011d Binary files /dev/null and b/src/mainboard/clevo/adl-p/variants/ns50pu/data.vbt differ diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/gpio.c b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio.c new file mode 100644 index 00000000000..ed1b050cf58 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio.c @@ -0,0 +1,1334 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, ACPI), + + /* GPP_B3 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, ACPI), + + /* GPP_B4 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), + + /* GPP_B5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, ACPI), + + /* GPP_B6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, DEEP, OFF, ACPI), + + /* GPP_B7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, DEEP, OFF, ACPI), + + /* GPP_B8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, ACPI), + + /* GPP_B9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, ACPI), + + /* GPP_B10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), + + /* GPP_B11 - PMCALERT# */ + /* DW0: 0x04000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + /* GPP_B15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), + + /* GPP_B16 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + + /* GPP_B17 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), + + /* GPP_B18 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, ACPI), + + /* GPP_B19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI), + + /* GPP_B20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, DEEP, OFF, ACPI), + + /* GPP_B21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, ACPI), + + /* GPP_B22 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, DEEP, OFF, ACPI), + + /* GPP_B23 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, DEEP, OFF, ACPI), + + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + /* GPP_T0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T0, NONE), + + /* GPP_T1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T1, NONE), + + /* GPP_T2 - Reserved */ + /* DW0: 0x44000b00, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), + + /* GPP_T3 - Reserved */ + /* DW0: 0x44000b00, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), + + /* GPP_T4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T4, NONE), + + /* GPP_T5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T5, NONE), + + /* GPP_T6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T6, NONE), + + /* GPP_T7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T7, NONE), + + /* GPP_T8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T8, NONE), + + /* GPP_T9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T9, NONE), + + /* GPP_T10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T10, NONE), + + /* GPP_T11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T11, NONE), + + /* GPP_T12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T12, NONE), + + /* GPP_T13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T13, NONE), + + /* GPP_T14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T14, NONE), + + /* GPP_T15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS0# */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_ALERT0# */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + + /* GPP_A6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A6, UP_20K, DEEP, OFF, ACPI), + + /* GPP_A7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), + + /* GPP_A8 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A8, 1, PLTRST), + + /* GPP_A9 - ESPI_CLK */ + /* DW0: 0x44000700, DW1: 0x0003d000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - ESPI_RESET# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, ACPI), + + /* GPP_A12 - SATAXPCIE1 */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + + /* GPP_A13 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, ACPI), + + /* GPP_A15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, ACPI), + + /* GPP_A16 - USB_OC3# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPP_A17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, ACPI), + + /* GPP_A18 - DDSP_HPDB */ + /* DW0: 0x44000500, DW1: 0x00024000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A19, NONE, DEEP, OFF, ACPI), + + /* GPP_A20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, ACPI), + + /* GPP_A21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, DEEP, OFF, ACPI), + + /* GPP_A22 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, ACPI), + + /* GPP_A23 - ESPI_CS1# */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), + + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, DEEP, OFF, ACPI), + + /* GPP_S1 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, DEEP, OFF, ACPI), + + /* GPP_S2 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, DEEP, OFF, ACPI), + + /* GPP_S3 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, DEEP, OFF, ACPI), + + /* GPP_S4 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, DEEP, OFF, ACPI), + + /* GPP_S5 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, DEEP, OFF, ACPI), + + /* GPP_S6 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, DEEP, OFF, ACPI), + + /* GPP_S7 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* GPP_H1 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + + /* GPP_H2 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + + /* GPP_H3 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, ACPI), + + /* GPP_H4 - I2C0_SDA */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* GPP_H5 - I2C0_SCL */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* GPP_H6 - I2C1_SDA */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + + /* GPP_H7 - I2C1_SCL */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* GPP_H8 - CNV_MFUART2_RXD */ + /* DW0: 0x44000902, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + + /* GPP_H9 - CNV_MFUART2_TXD */ + /* DW0: 0x44000900, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /* GPP_H10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, DEEP, OFF, ACPI), */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0_RXD */ + + /* GPP_H11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, DEEP, OFF, ACPI), */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + + /* GPP_H12 - DEVSLP0B */ + /* DW0: 0x44001500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + + /* GPP_H13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, DEEP, OFF, ACPI), + + /* GPP_H14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, DEEP, OFF, ACPI), + + /* GPP_H15 - DDPB_CTRLCLK */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + + /* GPP_H16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, DEEP, OFF, ACPI), + + /* GPP_H17 - DDPB_CTRLDATA */ + /* DW0: 0x44000502, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - PROC_C10_GATE# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - SRCCLKREQ4# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + + /* GPP_H20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, ACPI), + + /* GPP_H21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, DEEP, OFF, ACPI), + + /* GPP_H22 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, DEEP, OFF, ACPI), + + /* GPP_H23 - SRCCLKREQ5# */ + /* DW0: 0x44000b02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + + /* GPP_D1 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, DEEP, OFF, ACPI), + + /* GPP_D2 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D2, 1, PLTRST), + + /* GPP_D3 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D3, 1, PLTRST), + + /* GPP_D4 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D4, 1, PLTRST), + + /* GPP_D5 - SRCCLKREQ0# */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + + /* GPP_D7 - SRCCLKREQ2# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* GPP_D8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, ACPI), + + /* GPP_D9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D12 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, ACPI), + + /* GPP_D14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + + /* GPP_D16 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + + /* GPP_D17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, ACPI), + + /* GPP_D18 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, ACPI), + + /* GPP_D19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI), + + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group RESERVED ------- */ + + /* GPP_CPU_RSVD_1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_1, NONE), + + /* GPP_CPU_RSVD_2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_2, NONE), + + /* GPP_CPU_RSVD_3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_3, NONE), + + /* GPP_CPU_RSVD_4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_4, NONE), + + /* GPP_CPU_RSVD_5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_5, NONE), + + /* GPP_CPU_RSVD_6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_6, NONE), + + /* GPP_CPU_RSVD_7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_7, NONE), + + /* GPP_CPU_RSVD_8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_8, NONE), + + /* GPP_CPU_RSVD_9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_9, NONE), + + /* GPP_CPU_RSVD_10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_10, NONE), + + /* GPP_CPU_RSVD_11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_11, NONE), + + /* GPP_CPU_RSVD_12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_12, NONE), + + /* GPP_CPU_RSVD_13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_13, NONE), + + /* GPP_CPU_RSVD_14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_14, NONE), + + /* GPP_CPU_RSVD_15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_15, NONE), + + /* GPP_CPU_RSVD_16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_16, NONE), + + /* GPP_CPU_RSVD_17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_17, NONE), + + /* GPP_CPU_RSVD_18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_18, NONE), + + /* GPP_CPU_RSVD_19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_19, NONE), + + /* GPP_CPU_RSVD_20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_20, NONE), + + /* GPP_CPU_RSVD_21 - GPP_CPU_RSVD_21 */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_CPU_RSVD_21, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_22 - GPP_CPU_RSVD_22 */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_CPU_RSVD_22, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_23 - GPP_CPU_RSVD_23 */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_CPU_RSVD_23, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_24 - GPP_CPU_RSVD_24 */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_CPU_RSVD_24, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + /* DW0: 0x40000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + + /* GPP_VGPIO_4 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO_5 - GPIO */ + /* DW0: 0x40000003, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + /* DW0: 0x04000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - GPIO */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, LEVEL, INVERT), + + /* GPD3 - PWRBTN# */ + /* DW0: 0x04000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + + /* GPD7 - GPIO */ + /* DW0: 0x04000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PWROK, OFF, ACPI), + + /* GPD8 - SUSCLK */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD9, 0, PWROK), + + /* GPD10 - SLP_S5# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + + /* GPD11 - LANPHYPC */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + + /* GPD_SLP_LANB - GPD_SLP_LANB */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + + /* GPD_WAKEB - GPD_WAKEB */ + /* DW0: 0x00000702, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + /* DW0: 0x44000502, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + /* DW0: 0x44000502, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + + /* GPP_C3 - SML0CLK */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, DEEP, OFF, ACPI), + + /* GPP_C6 - SML1CLK */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + + /* GPP_C7 - SML1DATA */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + + /* GPP_C8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C14, NONE), + + /* GPP_C15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C18, NONE), + + /* GPP_C19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C19, NONE), + + /* GPP_C20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - CNV_BRI_DT */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + + /* GPP_F1 - CNV_BRI_RSP */ + /* DW0: 0x44000502, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + + /* GPP_F2 - CNV_RGI_DT */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + /* DW0: 0x44000502, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - CNV_RF_RESET# */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* GPP_F5 - CRF_XTAL_CLKREQ */ + /* DW0: 0x44000d00, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + + /* GPP_F6 - CNV_PA_BLANKING */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + + /* GPP_F7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, DEEP, OFF, ACPI), + + /* GPP_F8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), + + /* GPP_F9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, DEEP, OFF, ACPI), + + /* GPP_F10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), + + /* GPP_F11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), + + /* GPP_F12 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, ACPI), + + /* GPP_F13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + + /* GPP_F14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + + /* GPP_F15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + + /* GPP_F16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), + + /* GPP_F17 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + + /* GPP_F18 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + + /* GPP_F19 - SRCCLKREQ6# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* GPP_F20 - GPIO */ + /* DW0: 0x84000201, DW1: 0x0003c000 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + + /* GPP_F21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x0003c000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, DEEP, OFF, ACPI), + + /* GPP_F22 - VNN_CTRL */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* GPP_F23 - V1P05_CTRL */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* GPP_F_CLK_LOOPBK - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + + /* GPP_L_BKLTCTL - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + + /* GPP_L_VDDEN - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + + /* GPP_SYS_PWROK - n/a */ + /* DW0: 0x40000702, DW1: 0x0003c000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + + /* GPP_SYS_RESETB - n/a */ + /* DW0: 0x40000702, DW1: 0x0003c000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + + /* GPP_MLK_RSTB - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI), + + /* GPP_E1 - GPIO */ + /* DW0: 0x40100102, DW1: 0x00003000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_APIC(GPP_E1, UP_20K, DEEP, LEVEL, NONE), + + /* GPP_E2 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI), + + /* GPP_E3 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + + /* GPP_E4 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + + /* GPP_E5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, ACPI), + + /* GPP_E6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI), + + /* GPP_E7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), + + /* GPP_E8 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E8, NONE, DEEP, OFF, ACPI), + + /* GPP_E9 - USB_OC0# */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + + + /* GPP_E10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, ACPI), + + + /* GPP_E11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), + + /* GPP_E12 - GPIO INT */ + /* DW0: 0x40100102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), + + /* GPP_E13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, DEEP, OFF, ACPI), + + /* GPP_E14 - DDSP_HPDA */ + /* DW0: 0x44000700, DW1: 0x00024000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, DEEP, OFF, ACPI), + + /* GPP_E16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, DEEP, OFF, ACPI), + + /* GPP_E17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), + + /* GPP_E18 - TBT_LSX0_TXD */ + /* DW0: 0x44000300, DW1: 0x00003c00 */ + //PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + + /* GPP_E19 - TBT_LSX0_RXD */ + /* DW0: 0x44000300, DW1: 0x00003c00 */ + //PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + + /* GPP_E20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E20, NATIVE, DEEP, OFF, ACPI), + + /* GPP_E21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E21, NATIVE, DEEP, OFF, ACPI), + + /* GPP_E22 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00001000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E22, DN_20K, DEEP, OFF, ACPI), + + /* GPP_E23 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E23, NONE, DEEP, OFF, ACPI), + + /* GPP_E_CLK_LOOPBK - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + + /* GPP_R1 - HDA_SYNC */ + /* DW0: 0x44000500, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + + /* GPP_R2 - HDA_SDO */ + /* DW0: 0x44000500, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - HDA_SDI0 */ + /* DW0: 0x44000500, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + + /* GPP_R4 - HDA_RST# */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* GPP_R5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, DEEP, OFF, ACPI), + + /* GPP_R6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, DEEP, OFF, ACPI), + + /* GPP_R7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, DEEP, OFF, ACPI), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/gpio_early.c b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio_early.c new file mode 100644 index 00000000000..616d17da2b8 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/hda_verb.c b/src/mainboard/clevo/adl-p/variants/ns50pu/hda_verb.c new file mode 100644 index 00000000000..4abb6736026 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/hda_verb.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x15587717, /* Subsystem ID */ + 18, /* Number of entries */ + 0x0205001a, + 0x02048003, + 0x0205001a, + 0x0204c003, + AZALIA_SUBVENDOR(0, 0x15587717), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), + 0x02050038, + 0x02047901, + 0x02050007, + 0x02040202, + 0x02050008, + 0x02046a0e, + 0x0205001b, + 0x02040a4b, + 0x0205003c, + 0x02040354, + 0x0205003c, + 0x02040314, + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409a2, + 0x02050036, + 0x02045050, + 0x02050036, + 0x02045050, + + /* Intel Alderlake-P HDMI */ + 0x8086281c, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 7, /* Number of entries */ + 0x20278111, + 0x20278111, + 0x20278111, + 0x20278111, + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x20278100, + 0x20278100, + 0x20278100, + 0x20278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/overridetree.cb b/src/mainboard/clevo/adl-p/variants/ns50pu/overridetree.cb new file mode 100644 index 00000000000..f475d67aa8f --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/overridetree.cb @@ -0,0 +1,200 @@ +chip soc/intel/alderlake + # Default values at boot, to be adjusted by EC at runtime according + # to available wall brick capabilities. + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 56, + .tdp_psyspl2 = 90, + .tdp_psyspl3 = 92, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x7716 inherit + + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST# + register "srcclk_pin" = "0" # SSD2_CLKREQ# + device generic 0 on end + end + end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Motherboard + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Multi Board + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 (USB 3.2 Gen 2) + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 (Thunderbolt) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Motherboard + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH2 + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 UJ_USB1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1 CH0"" + register "type" = "UPC_TYPE_A" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1 CH1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port3 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end + device ref pcie_rp6 on + # PCIe RP#6 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F17)" # GPIO_SDCARD_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)" # GPP_D2_SDCARD_RST# + register "srcclk_pin" = "5" # CARD_CLKREQ5# + device generic 0 on end + end + end + device ref pcie_rp8 on + # PCIe RP#8 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_BUILT_IN, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" # LAN_PLT_RST# + register "srcclk_pin" = "6" # GLAN_CLKREQ6# + device generic 0 on end + end + end + device ref pcie_rp9 on + # PCIe RP#9 x4, Clock 4 (SSD1) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST# + register "srcclk_pin" = "4" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref sata on + register "sata_salp_support" = "1" + register "sata_ports_enable[1]" = "1" # SSD1 + register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC2 + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/romstage.c b/src/mainboard/clevo/adl-p/variants/ns50pu/romstage.c new file mode 100644 index 00000000000..f2b3861b404 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/romstage.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + .rcomp = { .resistor = 100, }, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.PchHdaSdiEnable[0] = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.DmiAspm = 2; // ASPM L1 + mupd->FspmConfig.DmiAspmCtrl = 2; // ASPM L1 + mupd->FspmConfig.GpioOverride = 0; + + mupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 1; + +/* Use pre-processor because CONFIG_INTEL_TXT_CBFS_BIOS_ACM is not defined otherwise */ +#if CONFIG(INTEL_TXT) + size_t acm_size = 0; + uintptr_t acm_base; + + intel_txt_log_spad(); + + if (CONFIG(INTEL_CBNT_LOGGING)) + intel_cbnt_log_registers(); + + if (CONFIG(INTEL_TXT_LOGGING)) { + intel_txt_log_bios_acm_error(); + txt_dump_chipset_info(); + } + + acm_base = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, &acm_size); + + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL: %08x %08x\n", msr.hi, msr.lo); + + mupd->FspmConfig.VmxEnable = 1; + mupd->FspmConfig.TxtImplemented = 1; + mupd->FspmConfig.Txt = 1; + mupd->FspmConfig.SinitMemorySize = CONFIG_INTEL_TXT_SINIT_SIZE; + mupd->FspmConfig.TxtHeapMemorySize = CONFIG_INTEL_TXT_HEAP_SIZE; + mupd->FspmConfig.TxtDprMemorySize = CONFIG_INTEL_TXT_DPR_SIZE << 20; + mupd->FspmConfig.TxtDprMemoryBase = 1; // Set to non-zero, FSP will update it + mupd->FspmConfig.BiosAcmBase = acm_base; + mupd->FspmConfig.BiosAcmSize = acm_size; + mupd->FspmConfig.ApStartupBase = 1; // Set to non-zero, FSP does NULL check +#endif + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/board_info.txt b/src/mainboard/clevo/adl-p/variants/nv40pz/board_info.txt new file mode 100644 index 00000000000..6eb5949ebde --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/board_info.txt @@ -0,0 +1,2 @@ +Board name: NV4xPZ +Release year: 2022 diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/data.vbt b/src/mainboard/clevo/adl-p/variants/nv40pz/data.vbt new file mode 100644 index 00000000000..d58825f3265 Binary files /dev/null and b/src/mainboard/clevo/adl-p/variants/nv40pz/data.vbt differ diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/gpio.c b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio.c new file mode 100644 index 00000000000..d88cc33f601 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio.c @@ -0,0 +1,881 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - GPIO */ + PAD_CFG_GPO(GPP_B2, 0, DEEP), + + /* GPP_B3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, ACPI), + + /* GPP_B4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), + + /* GPP_B5 - I2C2_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + + /* GPP_B6 - I2C2_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + + /* GPP_B7 - GPIO */ + PAD_CFG_GPO(GPP_B7, 0, DEEP), + + /* GPP_B8 - GPIO */ + PAD_NC(GPP_B8, NONE), + + /* GPP_B9 - GPIO */ + PAD_CFG_GPO(GPP_B9, 0, DEEP), + + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + /* GPP_B15 - GPIO */ + PAD_CFG_GPO(GPP_B15, 0, DEEP), + + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), + + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + + /* GPP_B18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, ACPI), + + /* GPP_B19 - GPIO */ + PAD_CFG_GPO(GPP_B19, 0, DEEP), + + /* GPP_B20 - GPIO */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), + + /* GPP_B21 - GPIO */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, DEEP, OFF, ACPI), + + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + /* GPP_T0 - GPIO */ + PAD_NC(GPP_T0, NONE), + + /* GPP_T1 - GPIO */ + PAD_NC(GPP_T1, NONE), + + /* GPP_T2 - GPIO */ + PAD_CFG_GPO(GPP_T2, 0, DEEP), + + /* GPP_T3 - GPIO */ + PAD_NC(GPP_T3, NONE), + + /* GPP_T4 - GPIO */ + PAD_NC(GPP_T4, NONE), + + /* GPP_T5 - GPIO */ + PAD_NC(GPP_T5, NONE), + + /* GPP_T6 - GPIO */ + PAD_NC(GPP_T6, NONE), + + /* GPP_T7 - GPIO */ + PAD_NC(GPP_T7, NONE), + + /* GPP_T8 - GPIO */ + PAD_NC(GPP_T8, NONE), + + /* GPP_T9 - GPIO */ + PAD_NC(GPP_T9, NONE), + + /* GPP_T10 - GPIO */ + PAD_NC(GPP_T10, NONE), + + /* GPP_T11 - GPIO */ + PAD_NC(GPP_T11, NONE), + + /* GPP_T12 - GPIO */ + PAD_NC(GPP_T12, NONE), + + /* GPP_T13 - GPIO */ + PAD_NC(GPP_T13, NONE), + + /* GPP_T14 - GPIO */ + PAD_NC(GPP_T14, NONE), + + /* GPP_T15 - GPIO */ + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + + /* GPP_A6 - GPIO */ + PAD_CFG_GPO(GPP_A6, 0, DEEP), + + /* GPP_A7 - GPIO */ + PAD_CFG_GPO(GPP_A7, 0, DEEP), + + /* GPP_A8 - GPIO */ + PAD_NC(GPP_A8, NONE), + + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), + + /* GPP_A13 - GPIO */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - GPIO */ + PAD_CFG_GPO(GPP_A14, 1, DEEP), + + /* GPP_A15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, ACPI), + + /* GPP_A16 - USB_OC3# */ + PAD_NC(GPP_A16, NONE), + + /* GPP_A17 - GPIO */ + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), + + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A19, NONE, DEEP, OFF, ACPI), + + /* GPP_A20 - GPIO */ + PAD_NC(GPP_A20, NONE), + + /* GPP_A21 - GPIO */ + PAD_NC(GPP_A21, NONE), + + /* GPP_A22 - GPIO */ + PAD_CFG_GPO(GPP_A22, 1, PLTRST), + + /* GPP_A23 - GPIO */ + PAD_NC(GPP_A23, NONE), + + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_CFG_GPO(GPP_S0, 0, DEEP), + + /* GPP_S1 - GPIO */ + PAD_CFG_GPO(GPP_S1, 0, DEEP), + + /* GPP_S2 - GPIO */ + PAD_CFG_GPO(GPP_S2, 0, DEEP), + + /* GPP_S3 - GPIO */ + PAD_CFG_GPO(GPP_S3, 0, DEEP), + + /* GPP_S4 - GPIO */ + PAD_CFG_GPO(GPP_S4, 0, DEEP), + + /* GPP_S5 - GPIO */ + PAD_CFG_GPO(GPP_S5, 0, DEEP), + + /* GPP_S6 - GPIO */ + PAD_CFG_GPO(GPP_S6, 0, DEEP), + + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* GPP_H1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, ACPI), + + /* GPP_H2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, DEEP, OFF, ACPI), + + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, ACPI), + + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* GPP_H6 - I2C1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + + /* GPP_H7 - I2C1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* GPP_H8 - CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + + /* GPP_H9 - CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /* GPP_H10 - UART0_RXD */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + + /* GPP_H11 - UART0_TXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* GPP_H12 - GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16, NONE), + + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19, NONE), + + /* GPP_H20 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, ACPI), + + /* GPP_H21 - GPIO */ + PAD_CFG_GPO(GPP_H21, 0, DEEP), + + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - SRCCLKREQ5# */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + + /* GPP_D1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, DEEP, OFF, ACPI), + + /* GPP_D2 - GPIO */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + + /* GPP_D3 - GPIO */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - GPIO */ + PAD_NC(GPP_D6, NONE), + + /* GPP_D7 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* GPP_D8 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NONE), + + /* GPP_D10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, ACPI), + + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group RESERVED ------- */ + + /* GPP_CPU_RSVD_1 - GPIO */ + PAD_NC(GPP_CPU_RSVD_1, NONE), + + /* GPP_CPU_RSVD_2 - GPIO */ + PAD_NC(GPP_CPU_RSVD_2, NONE), + + /* GPP_CPU_RSVD_3 - GPIO */ + PAD_NC(GPP_CPU_RSVD_3, NONE), + + /* GPP_CPU_RSVD_4 - GPIO */ + PAD_NC(GPP_CPU_RSVD_4, NONE), + + /* GPP_CPU_RSVD_5 - GPIO */ + PAD_NC(GPP_CPU_RSVD_5, NONE), + + /* GPP_CPU_RSVD_6 - GPIO */ + PAD_NC(GPP_CPU_RSVD_6, NONE), + + /* GPP_CPU_RSVD_7 - GPIO */ + PAD_NC(GPP_CPU_RSVD_7, NONE), + + /* GPP_CPU_RSVD_8 - GPIO */ + PAD_NC(GPP_CPU_RSVD_8, NONE), + + /* GPP_CPU_RSVD_9 - GPIO */ + PAD_NC(GPP_CPU_RSVD_9, NONE), + + /* GPP_CPU_RSVD_10 - GPIO */ + PAD_NC(GPP_CPU_RSVD_10, NONE), + + /* GPP_CPU_RSVD_11 - GPIO */ + PAD_NC(GPP_CPU_RSVD_11, NONE), + + /* GPP_CPU_RSVD_12 - GPIO */ + PAD_NC(GPP_CPU_RSVD_12, NONE), + + /* GPP_CPU_RSVD_13 - GPIO */ + PAD_NC(GPP_CPU_RSVD_13, NONE), + + /* GPP_CPU_RSVD_14 - GPIO */ + PAD_NC(GPP_CPU_RSVD_14, NONE), + + /* GPP_CPU_RSVD_15 - GPIO */ + PAD_NC(GPP_CPU_RSVD_15, NONE), + + /* GPP_CPU_RSVD_16 - GPIO */ + PAD_NC(GPP_CPU_RSVD_16, NONE), + + /* GPP_CPU_RSVD_17 - GPIO */ + PAD_NC(GPP_CPU_RSVD_17, NONE), + + /* GPP_CPU_RSVD_18 - GPIO */ + PAD_NC(GPP_CPU_RSVD_18, NONE), + + /* GPP_CPU_RSVD_19 - GPIO */ + PAD_NC(GPP_CPU_RSVD_19, NONE), + + /* GPP_CPU_RSVD_20 - GPIO */ + PAD_NC(GPP_CPU_RSVD_20, NONE), + + /* GPP_CPU_RSVD_21 - GPP_CPU_RSVD_21 */ + PAD_CFG_NF(GPP_CPU_RSVD_21, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_22 - GPP_CPU_RSVD_22 */ + PAD_CFG_NF(GPP_CPU_RSVD_22, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_23 - GPP_CPU_RSVD_23 */ + PAD_CFG_NF(GPP_CPU_RSVD_23, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_24 - GPP_CPU_RSVD_24 */ + PAD_CFG_NF(GPP_CPU_RSVD_24, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD2, NATIVE, PWROK, OFF, ACPI), + + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + + /* GPD7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PWROK, OFF, ACPI), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + + /* GPD11 - LANPHYPC */ + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Group PCIe vGPIO ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C2, NONE, DEEP, OFF, ACPI), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + /* GPP_F2 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* GPP_F5 - CRF_XTAL_CLKREQ */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + + /* GPP_F6 - CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + + /* GPP_F7 - GPIO */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /* GPP_F11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), + + /* GPP_F12 - GPIO */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI), + + /* GPP_F14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + + /* GPP_F15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + + /* GPP_F16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), + + /* GPP_F17 - GPIO */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + + /* GPP_F18 - GPIO */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + + /* GPP_F19 - SRCCLKREQ6# */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* GPP_F20 - GPIO */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + + /* GPP_F21 - GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + + /* GPP_F22 - GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), + + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + + /* GPP_L_BKLTCTL - n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + + /* GPP_L_VDDEN - n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI), + + /* GPP_E1 - GPIO */ + PAD_CFG_GPI_APIC(GPP_E1, UP_20K, DEEP, LEVEL, NONE), + + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + + /* GPP_E3 - GPIO */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + + /* GPP_E4 - GPIO */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + + /* GPP_E5 - GPIO */ + PAD_NC(GPP_E5, NONE), + + /* GPP_E6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI), + + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), + + /* GPP_E8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E8, NONE, DEEP, OFF, ACPI), + + /* GPP_E9 - USB_OC0# */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, ACPI), + + /* GPP_E11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), + + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, DEEP, OFF, ACPI), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), + + /* GPP_E16 - GPIO */ + PAD_NC(GPP_E16, NONE), + + /* GPP_E17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), + + /* GPP_E18 - TBT_LSX0_TXD */ + //PAD_NC(GPP_E18, NATIVE), + + /* GPP_E19 - TBT_LSX0_RXD */ + //PAD_NC(GPP_E19, NATIVE), + + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NONE), + + /* GPP_E21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E21, NATIVE, DEEP, OFF, ACPI), + + /* GPP_E22 - GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), + + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* GPP_R5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, DEEP, OFF, ACPI), + + /* GPP_R6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, DEEP, OFF, ACPI), + + /* GPP_R7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, DEEP, OFF, ACPI), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/gpio_early.c b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio_early.c new file mode 100644 index 00000000000..8503bb7925d --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), // UART0_RXD + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), // UART0_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/hda_verb.c b/src/mainboard/clevo/adl-p/variants/nv40pz/hda_verb.c new file mode 100644 index 00000000000..614576f06cb --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/hda_verb.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x15584041, /* Subsystem ID */ + 18, /* Number of entries */ + 0x0205001a, + 0x02048003, + 0x0205001a, + 0x0204c003, + AZALIA_SUBVENDOR(0, 0x15584041), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), + 0x02050038, + 0x02047901, + 0x02050007, + 0x02040202, + 0x02050008, + 0x02046a0e, + 0x0205001b, + 0x02040a4b, + 0x0205003c, + 0x02040354, + 0x0205003c, + 0x02040314, + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409a2, + 0x02050036, + 0x02045050, + 0x02050036, + 0x02045050, + + /* Intel Alderlake-P HDMI */ + 0x8086281c, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 7, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + 0x20278111, + 0x20278111, + 0x20278111, + 0x20278111, + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x20278100, + 0x20278100, + 0x20278100, + 0x20278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/overridetree.cb b/src/mainboard/clevo/adl-p/variants/nv40pz/overridetree.cb new file mode 100644 index 00000000000..12cb8561f7e --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/overridetree.cb @@ -0,0 +1,201 @@ +chip soc/intel/alderlake + # Default values at boot, to be adjusted by EC at runtime according + # to available wall brick capabilities. + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 60, + .tdp_psyspl2 = 90, + .tdp_psyspl3 = 92, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x4041 inherit + + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD1_RST# + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_2"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_2"" + register "type" = "UPC_TYPE_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end + device ref pcie_rp9 on + # PCIe RP#9 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F17)" # GPIO_CARD_PWR + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # GPP_D2_SDCARD_RST# + register "srcclk_pin" = "5" # CARD_CLKREQ5# + device generic 0 on end + end + end + device ref pcie_rp10 on + # PCIe RP#10 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_BUILT_IN, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A22)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST# + register "srcclk_pin" = "6" # LAN_CLKREQ# + device generic 0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC2 + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/romstage.c b/src/mainboard/clevo/adl-p/variants/nv40pz/romstage.c new file mode 100644 index 00000000000..e5f5260fb1e --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/romstage.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + +/* Use pre-processor because CONFIG_INTEL_TXT_CBFS_BIOS_ACM is not defined otherwise */ +#if CONFIG(INTEL_TXT) + size_t acm_size = 0; + uintptr_t acm_base; + + intel_txt_log_spad(); + + if (CONFIG(INTEL_CBNT_LOGGING)) + intel_cbnt_log_registers(); + + if (CONFIG(INTEL_TXT_LOGGING)) { + intel_txt_log_bios_acm_error(); + txt_dump_chipset_info(); + } + + acm_base = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, &acm_size); + + msr_t msr = rdmsr(IA32_FEATURE_CONTROL); + printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL: %08x %08x\n", msr.hi, msr.lo); + + mupd->FspmConfig.VmxEnable = 1; + mupd->FspmConfig.TxtImplemented = 1; + mupd->FspmConfig.Txt = 1; + mupd->FspmConfig.SinitMemorySize = CONFIG_INTEL_TXT_SINIT_SIZE; + mupd->FspmConfig.TxtHeapMemorySize = CONFIG_INTEL_TXT_HEAP_SIZE; + mupd->FspmConfig.TxtDprMemorySize = CONFIG_INTEL_TXT_DPR_SIZE << 20; + mupd->FspmConfig.TxtDprMemoryBase = 1; // Set to non-zero, FSP will update it + mupd->FspmConfig.BiosAcmBase = acm_base; + mupd->FspmConfig.BiosAcmSize = acm_size; + mupd->FspmConfig.ApStartupBase = 1; // Set to non-zero, FSP does NULL check +#endif + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/clevo/adl-p/vboot-rwa.fmd b/src/mainboard/clevo/adl-p/vboot-rwa.fmd new file mode 100644 index 00000000000..93cd54a8b78 --- /dev/null +++ b/src/mainboard/clevo/adl-p/vboot-rwa.fmd @@ -0,0 +1,41 @@ +FLASH 32M { + SI_ALL 5M { + SI_DESC 4K + SI_ME + } + + UNUSED 11M + + RW_MISC 424K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_SHARED 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_NVRAM(PRESERVE) 24K + } + + CONSOLE 128K + BOOTSPLASH(CBFS) 1M + + RW_SECTION_A { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + + WP_RO 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } +} diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index 5961b68cb47..15d4fc7d1d4 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -22,7 +22,7 @@ config BOARD_CLEVO_CMLU_COMMON config BOARD_CLEVO_L140CU_BASE bool select BOARD_CLEVO_CMLU_COMMON - select EC_CLEVO_IT5570E + select EC_DASHARO_EC select HAVE_SPD_IN_CBFS config BOARD_CLEVO_L140CU @@ -77,7 +77,7 @@ config SEABIOS_PS2_TIMEOUT depends on PAYLOAD_SEABIOS default 500 -config EC_CLEVO_IT5570E_MEM_BASE - default 0xfe700000 +config EC_DASHARO_EC_BAT_THRESHOLDS + default n if BOARD_CLEVO_L140CU_BASE endif diff --git a/src/mainboard/clevo/cml-u/Makefile.mk b/src/mainboard/clevo/cml-u/Makefile.mk index babadf538a3..6404f801342 100644 --- a/src/mainboard/clevo/cml-u/Makefile.mk +++ b/src/mainboard/clevo/cml-u/Makefile.mk @@ -1,7 +1,6 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/acpi bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c @@ -12,9 +11,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads -smm-$(CONFIG_EC_CLEVO_IT5570E) += smihandler.c - subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/cml-u/acpi/gpe.asl b/src/mainboard/clevo/cml-u/acpi/gpe.asl new file mode 100644 index 00000000000..c1bc04dc9a3 --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/gpe.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_D9 SCI +Method (_L29, 0, Serialized) { + Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/clevo/cml-u/acpi/mainboard.asl b/src/mainboard/clevo/cml-u/acpi/mainboard.asl new file mode 100644 index 00000000000..ba84732f35f --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x50 /* GPP_E16 */ +#define EC_GPE_SWI 0x29 /* GPP_D9 */ +#include + +Scope (\_SB) { + #include "sleep.asl" +} + +Scope (\_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/clevo/cml-u/acpi/sleep.asl b/src/mainboard/clevo/cml-u/acpi/sleep.asl new file mode 100644 index 00000000000..48c50e075e3 --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/clevo/cml-u/bootblock.c b/src/mainboard/clevo/cml-u/bootblock.c index ee6c0b31ce6..b351fbd8ef6 100644 --- a/src/mainboard/clevo/cml-u/bootblock.c +++ b/src/mainboard/clevo/cml-u/bootblock.c @@ -1,21 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include void bootblock_mainboard_early_init(void) { variant_configure_early_gpios(); - - /* Open LGMR window for EC */ - if (CONFIG(EC_CLEVO_IT5570E)) - lpc_open_mmio_window(CONFIG_EC_CLEVO_IT5570E_MEM_BASE, 64 * KiB); -} - -void bootblock_mainboard_init(void) -{ - if (CONFIG(EC_CLEVO_IT5570E)) - ec_configure_kbled_booteffect(); } diff --git a/src/mainboard/clevo/cml-u/cmos.default b/src/mainboard/clevo/cml-u/cmos.default index aaf4c6ea4a4..79961f43d82 100644 --- a/src/mainboard/clevo/cml-u/cmos.default +++ b/src/mainboard/clevo/cml-u/cmos.default @@ -2,16 +2,4 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable power_on_after_fail=Disable - -# EC options -ac_fan_always_on=Disable -camera_boot_state=Keep -fn_win_swap=Disable -tp_toggle_mode=CtrlAltF9 -flexicharger_on=Disable -flexicharger_start=95 -flexicharger_stop=100 -kbled_booteffect=Disable -kbled_timeout=15 diff --git a/src/mainboard/clevo/cml-u/cmos.layout b/src/mainboard/clevo/cml-u/cmos.layout index 8350704ff06..b527f81b083 100644 --- a/src/mainboard/clevo/cml-u/cmos.layout +++ b/src/mainboard/clevo/cml-u/cmos.layout @@ -17,26 +17,12 @@ entries # ----------------------------------------------------------------- # coreboot config options: cpu -400 1 e 1 hyper_threading +400 1 e 2 hyper_threading # ----------------------------------------------------------------- # coreboot config options: southbridge 410 2 e 7 power_on_after_fail -# ----------------------------------------------------------------- -# EC options -500 1 e 1 ac_fan_always_on -502 2 e 7 camera_boot_state -504 1 e 1 fn_win_swap -505 1 e 8 tp_toggle_mode - -519 1 e 1 flexicharger_on -520 8 h 0 flexicharger_start -528 8 h 0 flexicharger_stop - -543 1 e 1 kbled_booteffect -544 16 h 0 kbled_timeout - # ----------------------------------------------------------------- # vboot nv area 800 128 r 0 vbnv @@ -52,6 +38,8 @@ enumerations #ID value text 1 0 Disable 1 1 Enable +2 0 Enable +2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency @@ -66,8 +54,6 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep -8 0 CtrlAltF9 -8 1 KeycodeF7F8 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/clevo/cml-u/dsdt.asl b/src/mainboard/clevo/cml-u/dsdt.asl index 71556dbf10e..203f39e702f 100644 --- a/src/mainboard/clevo/cml-u/dsdt.asl +++ b/src/mainboard/clevo/cml-u/dsdt.asl @@ -29,8 +29,5 @@ DefinitionBlock( #include } -#if CONFIG(EC_CLEVO_IT5570E) - #include - #include -#endif + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.mk b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.mk index 7f547fb03a5..617592897e0 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.mk +++ b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.mk @@ -1,3 +1,3 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = samsung-K4AAG165WA-BCTD diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 2fa7a30b1f8..1a4ef105326 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/cannonlake - register "s0ix_enable" = "true" register "common_soc_config" = "{ /* Touchpad */ .i2c[0] = { @@ -145,10 +144,13 @@ chip soc/intel/cannonlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end device ref lpc_espi on - chip ec/clevo/it5570e - device generic 0 on end - register "pl2_on_battery" = "15" - end + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) + register "gen1_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen2_dec" = "0x00fc0e01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen3_dec" = "0x00fc0f01" chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c index 258f07698e4..fb658dddd4f 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c @@ -233,9 +233,6 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H21, NONE), PAD_NC(GPP_H22, UP_20K), PAD_NC(GPP_H23, UP_20K), - - /* ------- GPIO Group CPU ------- */ - PAD_CFG_NF(PECI_IO, DN_20K, DEEP, NF1), /* PECI */ }; void variant_configure_gpios(void) diff --git a/src/mainboard/clevo/tgl-u/Kconfig b/src/mainboard/clevo/tgl-u/Kconfig index 3ab0e9190f4..ab6169341fd 100644 --- a/src/mainboard/clevo/tgl-u/Kconfig +++ b/src/mainboard/clevo/tgl-u/Kconfig @@ -7,6 +7,7 @@ config BOARD_CLEVO_TGLU_COMMON select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT @@ -19,31 +20,73 @@ config BOARD_CLEVO_TGLU_COMMON select SOC_INTEL_TIGERLAKE select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP + select EC_DASHARO_EC + select EC_DASHARO_EC_BAT_THRESHOLDS + select EC_ACPI -config BOARD_CLEVO_L140MU +config BOARD_CLEVO_L140MU_BASE + bool select BOARD_CLEVO_TGLU_COMMON - select EC_CLEVO_IT5570E select HAVE_SPD_IN_CBFS +config BOARD_CLEVO_NV40MZ_BASE + bool + select BOARD_CLEVO_TGLU_COMMON + select EC_DASHARO_EC_DGPU + select DRIVER_NVIDIA_OPTIMUS + +config BOARD_CLEVO_NS50MU_BASE + bool + select BOARD_CLEVO_TGLU_COMMON + select DRIVERS_GENERIC_BAYHUB_LV2 + +config BOARD_CLEVO_L140MU + select BOARD_CLEVO_L140MU_BASE + +config BOARD_CLEVO_NV40MZ + select BOARD_CLEVO_NV40MZ_BASE + +config BOARD_CLEVO_NS50MU + select BOARD_CLEVO_NS50MU_BASE + if BOARD_CLEVO_TGLU_COMMON config MAINBOARD_DIR default "clevo/tgl-u" config VARIANT_DIR - default "l140mu" if BOARD_CLEVO_L140MU + default "l140mu" if BOARD_CLEVO_L140MU_BASE + default "nv40mz" if BOARD_CLEVO_NV40MZ_BASE + default "ns50mu" if BOARD_CLEVO_NS50MU_BASE config MAINBOARD_PART_NUMBER default "L140MU" if BOARD_CLEVO_L140MU + default "NV40MZ" if BOARD_CLEVO_NV40MZ + default "NS50MU" if BOARD_CLEVO_NS50MU + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "NS50_70MU" if BOARD_CLEVO_NS50MU_BASE + default "NV4XMB,ME,MZ" if BOARD_CLEVO_NV40MZ_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" config MAINBOARD_VERSION - default "2.2A" if BOARD_CLEVO_L140MU + default "2.2A" if BOARD_CLEVO_L140MU_BASE + default "2.2A" if BOARD_CLEVO_NV40MZ_BASE + default "2.2A" if BOARD_CLEVO_NS50MU_BASE + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match stock firmware config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" config CBFS_SIZE - default 0xb00000 if BOARD_CLEVO_L140MU + default 0xb00000 if BOARD_CLEVO_L140MU_BASE + default 0xb00000 if BOARD_CLEVO_NV40MZ_BASE + default 0xb00000 if BOARD_CLEVO_NS50MU_BASE config CONSOLE_POST default y @@ -52,7 +95,32 @@ config UART_FOR_CONSOLE default 2 config TPM_PIRQ - default 0x77 if BOARD_CLEVO_L140MU # GPP_C9_IRQ + default 0x77 if BOARD_CLEVO_L140MU_BASE # GPP_C9_IRQ + default 0x1C if BOARD_CLEVO_NV40MZ_BASE # GPP_C14_IRQ + default 0x1C if BOARD_CLEVO_NS50MU_BASE # GPP_C14_IRQ + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_ENABLE_CBFS_FALLBACK + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config VBOOT_VBNV_OFFSET + hex + default 0x28 + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A config POST_DEVICE default n @@ -63,7 +131,14 @@ config SEABIOS_PS2_TIMEOUT config USE_PM_ACPI_TIMER default n -config EC_CLEVO_IT5570E_MEM_BASE - default 0xfe0b0000 +config VBOOT_FWID_VERSION + default "\$(CONFIG_LOCALVERSION)" + +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 20 + +endif endif diff --git a/src/mainboard/clevo/tgl-u/Kconfig.name b/src/mainboard/clevo/tgl-u/Kconfig.name index adbc401e97e..c172f742146 100644 --- a/src/mainboard/clevo/tgl-u/Kconfig.name +++ b/src/mainboard/clevo/tgl-u/Kconfig.name @@ -4,3 +4,9 @@ comment "Tiger Lake U" config BOARD_CLEVO_L140MU bool "L140MU / L141MU / L142MU" + +config BOARD_CLEVO_NV40MZ + bool "NV4xMB / NV4xME / NV4xMZ" + +config BOARD_CLEVO_NS50MU + bool "NS5xMU / NS7xMU" diff --git a/src/mainboard/clevo/tgl-u/Makefile.mk b/src/mainboard/clevo/tgl-u/Makefile.mk index ae492df4298..ffa1cb92a22 100644 --- a/src/mainboard/clevo/tgl-u/Makefile.mk +++ b/src/mainboard/clevo/tgl-u/Makefile.mk @@ -1,7 +1,6 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/acpi bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c @@ -15,6 +14,4 @@ ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -smm-$(CONFIG_EC_CLEVO_IT5570E) += smihandler.c - subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/tgl-u/acpi/backlight.asl b/src/mainboard/clevo/tgl-u/acpi/backlight.asl new file mode 100644 index 00000000000..01fa83ea610 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/clevo/tgl-u/acpi/mainboard.asl b/src/mainboard/clevo/tgl-u/acpi/mainboard.asl new file mode 100644 index 00000000000..68e9645dade --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#define CPU_CRIT_TEMP 100 +#define GPU_CRIT_TEMP 105 +#include + +Scope (\_SB) { + #include "sleep.asl" + #include "touchpad.asl" + Scope (PCI0) { + #include "backlight.asl" + } +} diff --git a/src/mainboard/clevo/tgl-u/acpi/sleep.asl b/src/mainboard/clevo/tgl-u/acpi/sleep.asl new file mode 100644 index 00000000000..239c5dc2c6e --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/sleep.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + + /* Bring system out of TC cold before enter Sx */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + /* Bring system out of TC cold */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () + } +} diff --git a/src/mainboard/clevo/tgl-u/acpi/touchpad.asl b/src/mainboard/clevo/tgl-u/acpi/touchpad.asl new file mode 100644 index 00000000000..5e25e1de38d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/touchpad.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External (\_SB.PCI0.I2C0.H015, DeviceObj) +External (\_SB.PCI0.I2C0.H015._STA, IntObj) +External (\_SB.PCI0.I2C0.H038, DeviceObj) +External (\_SB.PCI0.I2C0.H038._STA, IntObj) + +Scope (PCI0.LPCB.EC0) +{ + Method (TPTG, 0, Serialized) + { + If (CondRefOf(\_SB.PCI0.I2C0.H015)) { + If (\_SB.PCI0.I2C0.H015._STA == Zero) { + \_SB.PCI0.I2C0.H015._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H015._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H015, One) + } ElseIf (CondRefOf(\_SB.PCI0.I2C0.H038)) { + If (\_SB.PCI0.I2C0.H038._STA == Zero) { + \_SB.PCI0.I2C0.H038._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H038._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H038, One) + } + } +} diff --git a/src/mainboard/clevo/tgl-u/bootblock.c b/src/mainboard/clevo/tgl-u/bootblock.c index ee6c0b31ce6..b351fbd8ef6 100644 --- a/src/mainboard/clevo/tgl-u/bootblock.c +++ b/src/mainboard/clevo/tgl-u/bootblock.c @@ -1,21 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include void bootblock_mainboard_early_init(void) { variant_configure_early_gpios(); - - /* Open LGMR window for EC */ - if (CONFIG(EC_CLEVO_IT5570E)) - lpc_open_mmio_window(CONFIG_EC_CLEVO_IT5570E_MEM_BASE, 64 * KiB); -} - -void bootblock_mainboard_init(void) -{ - if (CONFIG(EC_CLEVO_IT5570E)) - ec_configure_kbled_booteffect(); } diff --git a/src/mainboard/clevo/tgl-u/cmos.default b/src/mainboard/clevo/tgl-u/cmos.default index e5228b5742b..3808ffb7658 100644 --- a/src/mainboard/clevo/tgl-u/cmos.default +++ b/src/mainboard/clevo/tgl-u/cmos.default @@ -3,14 +3,5 @@ boot_option=Fallback debug_level=Debug power_on_after_fail=Disable - -# EC options -ac_fan_always_on=Disable -camera_boot_state=Keep -fn_win_swap=Disable -tp_toggle_mode=CtrlAltF9 -flexicharger_on=Disable -flexicharger_start=95 -flexicharger_stop=100 -kbled_booteffect=Disable -kbled_timeout=15 +kbl_brightness=0xff +kbl_color=0x00ffffff diff --git a/src/mainboard/clevo/tgl-u/cmos.layout b/src/mainboard/clevo/tgl-u/cmos.layout index b31964f0a9d..3863b242ff9 100644 --- a/src/mainboard/clevo/tgl-u/cmos.layout +++ b/src/mainboard/clevo/tgl-u/cmos.layout @@ -6,6 +6,8 @@ entries # start-bit length config config-ID name 0 120 r 0 reserved_memory +# coreboot config options: ramtop +304 80 h 0 ramtop # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option @@ -19,23 +21,9 @@ entries # coreboot config options: southbridge 410 2 e 7 power_on_after_fail -# ----------------------------------------------------------------- -# EC options -500 1 e 1 ac_fan_always_on -502 2 e 7 camera_boot_state -504 1 e 1 fn_win_swap -505 1 e 8 tp_toggle_mode - -519 1 e 1 flexicharger_on -520 8 h 0 flexicharger_start -528 8 h 0 flexicharger_stop - -543 1 e 1 kbled_booteffect -544 16 h 0 kbled_timeout - # ----------------------------------------------------------------- # vboot nv area -800 128 r 0 vbnv +432 128 r 0 vbnv # ----------------------------------------------------------------- # coreboot config options: check sums @@ -43,6 +31,10 @@ entries # ----------------------------------------------------------------- +# embedded controller settings +1024 8 h 0 kbl_brightness +1032 32 h 0 kbl_color + enumerations #ID value text @@ -64,10 +56,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep -8 0 CtrlAltF9 -8 1 KeycodeF7F8 # ----------------------------------------------------------------- checksums -checksum 392 799 984 +checksum 392 431 984 diff --git a/src/mainboard/clevo/tgl-u/dsdt.asl b/src/mainboard/clevo/tgl-u/dsdt.asl index 10ad9df6d9b..a9a7085dd3e 100644 --- a/src/mainboard/clevo/tgl-u/dsdt.asl +++ b/src/mainboard/clevo/tgl-u/dsdt.asl @@ -20,7 +20,6 @@ DefinitionBlock( #include #include #include - #include } Scope (\_SB.PCI0.LPCB) @@ -30,8 +29,5 @@ DefinitionBlock( #include -#if CONFIG(EC_CLEVO_IT5570E) - #include - #include -#endif + #include } diff --git a/src/mainboard/clevo/tgl-u/fadt.c b/src/mainboard/clevo/tgl-u/fadt.c index 28ed7e97c33..0967bc9a95b 100644 --- a/src/mainboard/clevo/tgl-u/fadt.c +++ b/src/mainboard/clevo/tgl-u/fadt.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include void mainboard_fill_fadt(acpi_fadt_t *fadt) { /* Control method power button (EC) */ - fadt->flags |= ACPI_FADT_POWER_BUTTON; + fadt->preferred_pm_profile = PM_MOBILE; } diff --git a/src/mainboard/clevo/tgl-u/include/variant/ramstage.h b/src/mainboard/clevo/tgl-u/include/variant/ramstage.h index 4b5b29db0a5..b519bbb24ee 100644 --- a/src/mainboard/clevo/tgl-u/include/variant/ramstage.h +++ b/src/mainboard/clevo/tgl-u/include/variant/ramstage.h @@ -4,5 +4,6 @@ #define VARIANT_RAMSTAGE_H void variant_configure_fsps(FSP_S_CONFIG *params); +void variant_init(void); #endif diff --git a/src/mainboard/clevo/tgl-u/ramstage.c b/src/mainboard/clevo/tgl-u/ramstage.c index 0768e515c93..4e931587839 100644 --- a/src/mainboard/clevo/tgl-u/ramstage.c +++ b/src/mainboard/clevo/tgl-u/ramstage.c @@ -1,20 +1,244 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include +#include +#include +#include +#include +#include +#include #include #include #include +struct smfi_cmd_set_fan_curve { + uint8_t fan; + struct fan_curve curve; +} __packed; + +struct fan_curve fan_curve_silent = { + { .temp = 0, .duty = 20 }, + { .temp = 65, .duty = 25 }, + { .temp = 75, .duty = 35 }, + { .temp = 85, .duty = 100 } +}; + +struct fan_curve fan_curve_performance = { + { .temp = 0, .duty = 25 }, + { .temp = 55, .duty = 35 }, + { .temp = 75, .duty = 60 }, + { .temp = 85, .duty = 100} +}; + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + void mainboard_silicon_init_params(FSP_S_CONFIG *params) { variant_configure_fsps(params); + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + + // Acoustic / RFI optimizations + // TODO optimize + params->PreWake = 150; + params->RampUp = 150; + params->RampDown = 150; + params->RfiMitigation = 1; +} + +static void set_fan_curve(void) +{ + int i; + uint8_t selection = get_fan_curve_option(); + struct smfi_cmd_set_fan_curve cmd; + + switch (selection) { + case FAN_CURVE_OPTION_SILENT: + cmd.curve = fan_curve_silent; + break; + case FAN_CURVE_OPTION_PERFORMANCE: + cmd.curve = fan_curve_performance; + break; + default: + cmd.curve = fan_curve_silent; + break; + } + + for (i = 0; i < (CONFIG(EC_DASHARO_EC_DGPU) ? 2 : 1); ++i) { + cmd.fan = i; + dasharo_ec_smfi_cmd(CMD_FAN_CURVE_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); + } +} + +static void set_camera_enablement(void) +{ + bool enabled = get_camera_option(); + + dasharo_ec_smfi_cmd(CMD_CAMERA_ENABLEMENT_SET, sizeof(enabled) / sizeof(uint8_t), (uint8_t *)&enabled); +} + +static void set_battery_thresholds(void) +{ + struct battery_config bat_cfg; + + get_battery_config(&bat_cfg); + + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_START, bat_cfg.start_threshold); + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_STOP, bat_cfg.stop_threshold); +} + +static void set_power_on_ac(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_POWER_ON_AC, + 0 + }; + + cmd.value = dasharo_get_power_on_after_fail(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); +} + +static void set_usb_charge_port(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_ALWAYS_ON_USB, + 0 + }; + + cmd.value = dasharo_get_usb_port_power(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); } static void init_mainboard(void *chip_info) { variant_configure_gpios(); + variant_init(); + + set_fan_curve(); + set_camera_enablement(); + set_battery_thresholds(); + set_power_on_ac(); + set_usb_charge_port(); +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static uint8_t read_proprietary_ec_version(uint8_t *data) +{ + int i, result; + char ec_version[16]; + + if (!data) + return -1; + + if (send_ec_command(0x93)) + return -1; + + for (i = 0; i < 16 - 1; i++) { + + result = recv_ec_data(); + if (result != -1) + ec_version[i] = result & 0xff; + + if (ec_version[i] == '$') { + ec_version[i] = '\0'; + break; + } + } + ec_version[15] = '\0'; + + data[0] = '1'; + data[1] = '.'; + + strcpy((char *)&data[2], ec_version); + + return 0; +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ec_version[256]; + uint8_t result; + + result = dasharo_ec_read_version((uint8_t *)ec_version); + + /* If the command fails it mean we are running proprietary EC most likely */ + if (result != 0) { + printk(BIOS_ERR, "Failed to read open EC firmware version\n"); + result = read_proprietary_ec_version((uint8_t *)ec_version); + if (result == 0) + t->count = smbios_add_string(t->eos, "EC: proprietary"); + else + t->count = smbios_add_string(t->eos, "EC: unknown"); + } else { + t->count = smbios_add_string(t->eos, "EC: open-source"); + } + + if (result == 0) { + printk(BIOS_DEBUG, "EC firmware version: %s\n", ec_version); + t->count = smbios_add_string(t->eos, strconcat("EC firmware version: ", + ec_version)); + } else { + printk(BIOS_ERR, "Unable to probe EC firmware version\n"); + t->count = smbios_add_string(t->eos, "EC firmware version: unknown"); + } + +} +#endif + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_strings = mainboard_smbios_strings; +#endif +} + +void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config) +{ + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3) + config->s0ix_enable = 0; + else + config->s0ix_enable = 1; } struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, .init = init_mainboard, }; + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + switch (dimm->ctrlr_num) { + case 0: + t->device_locator = smbios_add_string(t->eos, "RAM1"); + break; + case 1: + t->device_locator = smbios_add_string(t->eos, "RAM2"); + break; + default: + t->device_locator = smbios_add_string(t->eos, "UNKNOWN"); + break; + } +} diff --git a/src/mainboard/clevo/tgl-u/smihandler.c b/src/mainboard/clevo/tgl-u/smihandler.c deleted file mode 100644 index e53ab452a6f..00000000000 --- a/src/mainboard/clevo/tgl-u/smihandler.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -void mainboard_smi_sleep(u8 slp_typ) -{ - printk(BIOS_DEBUG, "Mainboard SMI sleep handler: %02x\n", slp_typ); - ec_smi_sleep(slp_typ); -} - -int mainboard_smi_apmc(u8 apmc) -{ - printk(BIOS_DEBUG, "Mainboard SMI APMC handler: %02x\n", apmc); - ec_smi_apmc(apmc); - - return 0; -} diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.mk b/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.mk index 361cbcd7bc9..1f81db75f35 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.mk +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.mk @@ -1,3 +1,3 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = samsung-M471A1G44AB0-CWE diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index 0131e219482..66669b4a5ae 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -138,7 +138,7 @@ chip soc/intel/tigerlake register "generic.hid" = ""ELAN040D"" register "generic.desc" = ""ELAN Touchpad"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "generic.detect" = "1" + register "generic.probed" = "true" register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end @@ -199,10 +199,6 @@ chip soc/intel/tigerlake end end device ref pch_espi on - chip ec/clevo/it5570e - device generic 0 on end - register "pl2_on_battery" = "15" - end chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c index 831b5fe9b15..6919baf4188 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -233,7 +232,4 @@ static const struct pad_config gpio_table[] = { void variant_configure_gpios(void) { gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - /* PECI idle workaround */ - pcr_rmw32(0x6b, 0x744, ~PAD_CFG1_PULL_MASK, PAD_CFG1_PULL_DN_20K); } diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c index b6bf5c5b550..1785e136dde 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include const u32 cim_verb_data[] = { /* Realtek ALC293 */ diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c b/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c index 6933e9904d2..c0e286595ad 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c @@ -9,3 +9,5 @@ void variant_configure_fsps(FSP_S_CONFIG *params) params->CpuPcieRpLtrEnable[0] = 1; params->CpuPcieRpSlotImplemented[0] = 1; } + +void variant_init(void) {} diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c index a1cfb03749e..14e81fe2fec 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include void variant_configure_fspm(FSPM_UPD *memupd) diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/Makefile.mk b/src/mainboard/clevo/tgl-u/variants/ns50mu/Makefile.mk new file mode 100644 index 00000000000..24384073fd5 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/board_info.txt b/src/mainboard/clevo/tgl-u/variants/ns50mu/board_info.txt new file mode 100644 index 00000000000..6758d0fbb0d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/board_info.txt @@ -0,0 +1,2 @@ +Board name: NS50_70MU +Release year: 2021 diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/data.vbt b/src/mainboard/clevo/tgl-u/variants/ns50mu/data.vbt new file mode 100644 index 00000000000..af16a2d54e6 Binary files /dev/null and b/src/mainboard/clevo/tgl-u/variants/ns50mu/data.vbt differ diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/ns50mu/devicetree.cb new file mode 100644 index 00000000000..7615396956a --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/devicetree.cb @@ -0,0 +1,317 @@ +chip soc/intel/tigerlake +# CPU (soc/intel/tigerlake/cpu.c) + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_psyspl2 = 65, + .tdp_psyspl3 = 67, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_psyspl2 = 65, + .tdp_psyspl3 = 67, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable s0ix, required for TGL-U + register "s0ix_enable" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + register "enable_c6dram" = "1" + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SLEW_FAST_8" + register "FastPkgCRampDisable" = "1" + register "tcc_offset" = "20" # TCC of 80C + +# Actual device tree + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x1558 0x51a1 inherit + + #From CPU EDS(575683) + device ref system_agent on end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + # ACPI brightness control + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref peg on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD1"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref tbt_pcie_rp0 on end # TBT Type-C + device ref north_xhci on # TBT Type-C + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # TBT Type-C + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // USB-A daughterboard + [1] = USB2_PORT_TYPE_C(OC_SKIP), // USB-C mainboard + [2] = USB2_PORT_MID(OC_SKIP), // USB-A mainboard + [4] = USB2_PORT_MID(OC_SKIP), // Fingerprint Reader + [5] = USB2_PORT_TYPE_C(OC_SKIP), // TBT USB-C + [6] = USB2_PORT_MID(OC_SKIP), // CCD + [9] = USB2_PORT_MID(OC_SKIP), // BT + }" + register "usb3_ports" = "{ + [1] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C port2 (lane 0) + [2] = USB3_PORT_DEFAULT(OC_SKIP), // USB-A port3 + [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C port4 (lane 1) + }" + # USB2 + register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # USB-A daughterboard + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C motherboard + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB-A motherboard + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint Reader + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TBT + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # CCD + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + # USB3 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C (lane 0) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C (lane 1) + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C (Lane 0)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C (Lane 1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""Elantech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref sata on + # SATA1 (SSD0) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" + register "SataSalpSupport" = "1" + end + device ref shared_ram on end + device ref cnvi_wifi on + register "CnviBtCore" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c1 on + # USB-PD + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref heci1 on end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref pcie_rp5 off end + device ref pcie_rp6 on + # PCIe root port #6 x1, Clock 2 (CARD) + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end + device ref pcie_rp7 on + # PCIe root port #7 x1, Clock 3 (GLAN) + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[3]" = "6" + register "PcieClkSrcClkReq[3]" = "3" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST + register "srcclk_pin" = "3" # GLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp8 on + # PCIe root port #8 x1, Clock 1 (WLAN) + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[1]" = "7" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[7]" = "1" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_23" # GPP_C23 + device pci 00.0 on end + end + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 4 (SSD0) + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[8]" = "1" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD0"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "4" # SSD0_CLKREQ# + device generic 0 on end + end + end + device ref pch_espi on + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x00fc0e01" + register "gen4_dec" = "0x00fc0f01" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # TBT Type-C + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio.c new file mode 100644 index 00000000000..16a1f1441cf --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio.c @@ -0,0 +1,636 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, UP_20K, DEEP, OFF, ACPI), + + /* GPP_B3 - GPIO */ + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + PAD_CFG_GPO(GPP_B8, 1, DEEP), + + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - GPIO */ + PAD_CFG_GPO(GPP_B14, 0, DEEP), + + /* GPP_B15 - GPIO */ + PAD_CFG_GPO(GPP_B15, 1, DEEP), + + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + + /* GPP_B18 - GPIO */ + PAD_NC(GPP_B18, NONE), + + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* ------- GPIO Group GPP_T (TGL UP3 only) ------- */ + + /* GPP_T2 - GPIO */ + PAD_NC(GPP_T2, NONE), + + /* GPP_T3 - GPIO */ + PAD_NC(GPP_T3, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_CLK */ + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + + /* GPP_A6 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - GPIO */ + PAD_NC(GPP_A7, NONE), + + /* GPP_A8 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + + /* GPP_A9 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + + /* GPP_A10 - GPIO */ + PAD_NC(GPP_A10, NONE), + + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + + /* GPP_A13 - GPIO */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - GPIO */ + PAD_NC(GPP_A14, NONE), + + /* GPP_A15 - GPIO */ + PAD_NC(GPP_A15, NONE), + + /* GPP_A16 - GPIO */ + PAD_NC(GPP_A16, NONE), + + /* GPP_A17 - GPIO */ + PAD_NC(GPP_A17, NONE), + + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - GPIO */ + PAD_NC(GPP_A19, NONE), + + /* GPP_A20 - GPIO */ + PAD_NC(GPP_A20, NONE), + + /* GPP_A21 - GPIO */ + PAD_NC(GPP_A21, NONE), + + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NONE), + + /* GPP_A23 - GPIO */ + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + + /* GPP_H2 - GPIO */ + PAD_NC(GPP_H2, NONE), + + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H4 - GPIO */ + PAD_NC(GPP_H4, NONE), + + /* GPP_H5 - GPIO */ + PAD_NC(GPP_H5, NONE), + + /* GPP_H6 - GPIO */ + PAD_NC(GPP_H6, NONE), + + /* GPP_H7 - GPIO */ + PAD_NC(GPP_H7, NONE), + + /* GPP_H8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H9, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H10 - SRCCLKREQ4# */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11, NONE), + + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12, NONE), + + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - GPIO */ + PAD_NC(GPP_H15, NONE), + + /* GPP_H16 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19, NONE), + + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), + + /* GPP_D1 - GPIO */ + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + + /* GPP_D2 - GPIO */ + PAD_CFG_GPO(GPP_D2, 1, PLTRST), + + /* GPP_D3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + + /* GPP_D7 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* GPP_D8 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NONE), + + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, DEEP, OFF, ACPI), + + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, DN_20K, DEEP, OFF, ACPI), + + /* GPP_D13 - GPIO */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_U (TGL UP3 only) ------- */ + + /* GPP_U4 - GPIO */ + PAD_CFG_GPO(GPP_U4, 0, PLTRST), + + /* GPP_U5 - GPIO */ + PAD_CFG_GPO(GPP_U5, 1, PLTRST), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, PWROK, OFF, ACPI), + + /* GPD3 - PRWBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + + /* GPD7 - GPIO */ + PAD_CFG_GPO(GPD7, 1, PWROK), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - GPIO */ + PAD_CFG_GPO(GPD9, 0, PWROK), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), + + /* GPD11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD11, UP_20K, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + PAD_NC(GPP_C2, NONE), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + PAD_NC(GPP_C5, NONE), + + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + PAD_CFG_GPI_APIC_HIGH(GPP_C14, UP_20K, DEEP), + + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - I2C0_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + + /* GPP_C17 - I2C0_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + + /* GPP_C18 - I2C1_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + + /* GPP_C19 - I2C1_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + + /* GPP_C23 - GPIO */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + /* GPP_F2 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - GPIO */ + PAD_NC(GPP_F4, NONE), + + /* GPP_F5 - GPIO */ + PAD_NC(GPP_F5, NONE), + + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - GPIO */ + PAD_CFG_GPO(GPP_F7, 1, DEEP), + + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + + /* GPP_F10 - GPIO */ + PAD_NC(GPP_F10, NONE), + + /* GPP_F11 - GPIO */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - GPIO */ + PAD_NC(GPP_F13, NONE), + + /* GPP_F14 - GPIO */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), + + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - GPIO */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F21, DN_20K, DEEP, OFF, ACPI), + + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + PAD_CFG_GPO(GPP_E1, 1, PLTRST), + + /* GPP_E2 - GPIO */ + PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + + /* GPP_E3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E3, DN_20K, DEEP, OFF, ACPI), + + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E5 - DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + + /* GPP_E6 - GPIO */ + PAD_NC(GPP_E6, NONE), + + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), + + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + PAD_NC(GPP_E13, NONE), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_NC(GPP_E15, NONE), + + /* GPP_E16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E16, DN_20K, DEEP, OFF, ACPI), + + /* GPP_E17 - GPIO */ + PAD_NC(GPP_E17, NONE), + + /* GPP_E18 - GPIO */ + PAD_NC(GPP_E18, NATIVE), + + /* GPP_E19 - GPIO */ + PAD_NC(GPP_E19, NATIVE), + + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NONE), + + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NONE), + + /* GPP_E22 - GPIO */ + PAD_NC(GPP_E22, NONE), + + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE), +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio_early.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio_early.c new file mode 100644 index 00000000000..f92d993ff70 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio_early.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Name format: / */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */ +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/hda_verb.c new file mode 100644 index 00000000000..d980767d1ef --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x155851a1, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155851a1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Tigerlake HDMI */ + 0x80862812, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/ramstage.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/ramstage.c new file mode 100644 index 00000000000..2e238c2cf48 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/ramstage.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void variant_configure_fsps(FSP_S_CONFIG *params) +{ + /* + * Disable AER for the SSD slot to support S0ix with SSDs running + * buggy firmware + */ + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpSlotImplemented[0] = 1; + + /* + * VR configuration + * Only one VR domain in TGL-U (VCCIN) + * ICCMax: 55A + * DC_LL: 2mOhm + * OCP: 72A + */ + params->AcLoadline[0] = 200; + params->DcLoadline[0] = 200; + params->IccMax[0] = 220; +} + +void variant_init(void) +{ + config_t *cfg = config_of_soc(); + struct device *cnvi_dev = pcidev_on_root(0x14, 3); + struct device *wlan_dev = pcidev_on_root(0x1c, 7); + bool radio_enable = get_wireless_option(); + + printk(BIOS_DEBUG, "Wireless is %sabled\n", radio_enable ? "en" : "dis"); + + wlan_dev->enabled = radio_enable; + cnvi_dev->enabled = radio_enable; + cfg->usb2_ports[9].enable = radio_enable; + + dasharo_ec_smfi_cmd(CMD_WIFI_BT_ENABLEMENT_SET, 1, (uint8_t *)&radio_enable); +} diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/romstage.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/romstage.c new file mode 100644 index 00000000000..ffdaf81eaab --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/romstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + memcfg_init(memupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt b/src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt new file mode 100644 index 00000000000..61b2b0eca90 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt @@ -0,0 +1,2 @@ +Board name: NV4xMZ/MB/ME +Release year: 2021 diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt b/src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt new file mode 100644 index 00000000000..af16a2d54e6 Binary files /dev/null and b/src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt differ diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb new file mode 100644 index 00000000000..b5089c9e74f --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb @@ -0,0 +1,301 @@ +chip soc/intel/tigerlake +# CPU (soc/intel/tigerlake/cpu.c) + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_psyspl2 = 65, + .tdp_psyspl3 = 67, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_psyspl2 = 65, + .tdp_psyspl3 = 67, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable s0ix, required for TGL-U + register "s0ix_enable" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + register "enable_c6dram" = "1" + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SLEW_FAST_8" + register "FastPkgCRampDisable" = "1" + register "tcc_offset" = "20" # TCC of 80C + +# Actual device tree + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x1558 0x4018 inherit + + #From CPU EDS(575683) + device ref system_agent on end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + # ACPI brightness control + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref peg on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD1"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref tbt_pcie_rp0 on end # TBT Type-C + device ref north_xhci on # TBT Type-C + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # TBT Type-C + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // USB-A port1 + [1] = USB2_PORT_TYPE_C(OC_SKIP), // USB-C port2 + [2] = USB2_PORT_MID(OC_SKIP), // USB-A port3 + [4] = USB2_PORT_MID(OC_SKIP), // Fingerprint Reader + [5] = USB2_PORT_TYPE_C(OC_SKIP), // TBT USB-C + [6] = USB2_PORT_MID(OC_SKIP), // CCD + [9] = USB2_PORT_MID(OC_SKIP), // BT + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // USB-A port1 + [1] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C port2 (right port, lane 0) + [2] = USB3_PORT_DEFAULT(OC_SKIP), // USB-A port3 + [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C port4 (right port, lane 1) + }" + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 4"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port4 on end + end + end + end + end + device ref shared_ram on end + device ref cnvi_wifi on + register "CnviBtCore" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 on + # USB-PD + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c2 on + # Pantone ROM + register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" + end + device ref heci1 on end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref pcie_rp5 on + # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[2]" = "4" + register "PcieClkSrcClkReq[2]" = "2" + chip drivers/gfx/nvidia/optimus + register "desc" = ""DGPU"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH + register "enable_delay_ms" = "16" + register "enable_off_delay_ms" = "4" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "4" + register "srcclk_pin" = "2" # PEG_CLKREQ# + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref pcie_rp9 on + # PCIe root port #9 x1, Clock 3 (CARD) + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device ref pcie_rp10 on + # PCIe root port #10 x1, Clock 4 (GLAN) + register "PcieRpLtrEnable[9]" = "1" + register "PcieClkSrcUsage[4]" = "9" + register "PcieClkSrcClkReq[4]" = "4" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST + register "srcclk_pin" = "4" # LAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp11 on + # PCIe root port #11 x1, Clock 1 (WLAN) + register "PcieRpSlotImplemented[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_23" # GPP_C23 + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref pch_espi on + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x00fc0e01" + register "gen4_dec" = "0x00fc0f01" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_C" + register "pmc_gpe0_dw1" = "PMC_GPP_E" + register "pmc_gpe0_dw2" = "PMC_GPD" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # TBT Type-C + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + subsystemid 0x1558 0x4019 + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c new file mode 100644 index 00000000000..637aeb0745b --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B15, 1, DEEP), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), + /* ------- GPIO Group GPP_T (TGL UP3 only) ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D13, 0, DEEP), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + PAD_CFG_NF(GPD2, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPD7, 1, RSMRST), + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + PAD_CFG_GPI_TRIG_OWN(GPD9, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPD11, UP_20K, DEEP, OFF, ACPI), + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_NC(GPP_C5, NONE), + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, DEEP), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT), + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPO(GPP_F7, 1, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_CFG_GPO(GPP_F9, 1, DEEP), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_GPO(GPP_E1, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_E17, NONE), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c new file mode 100644 index 00000000000..3e426ccd986 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Name format: / */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */ + PAD_CFG_GPO(GPP_U4, 0, DEEP), /* DGPU_RST#_PCH */ + PAD_CFG_GPO(GPP_U5, 0, DEEP), /* DGPU_PWR_EN */ +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c new file mode 100644 index 00000000000..1979c95b74c --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15584019, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15584018), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Tigerlake HDMI */ + 0x80862812, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c new file mode 100644 index 00000000000..5582df2218d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DGPU_RST_N GPP_U4 +#define DGPU_PWR_EN GPP_U5 + +void variant_configure_fsps(FSP_S_CONFIG *params) +{ + /* + * Disable AER for the SSD slot to support S0ix with SSDs running + * buggy firmware + */ + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpSlotImplemented[0] = 1; +} + +static void dgpu_power_enable(int onoff) { + printk(BIOS_DEBUG, "nvidia: DGPU power %d\n", onoff); + if (onoff) { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + mdelay(4); + gpio_set(DGPU_RST_N, 1); + } else { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 0); + } + mdelay(50); +} + +static void mainboard_pre_device(void *unused) { + dgpu_power_enable(dasharo_dgpu_state() != 0); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, mainboard_pre_device, NULL); + +void variant_init(void) { + config_t *cfg = config_of_soc(); + struct device *cnvi_dev = pcidev_on_root(0x14, 3); + struct device *wlan_dev = pcidev_on_root(0x1d, 2); + bool radio_enable = get_wireless_option(); + + printk(BIOS_DEBUG, "Wireless is %sabled\n", radio_enable ? "en" : "dis"); + + wlan_dev->enabled = radio_enable; + cnvi_dev->enabled = radio_enable; + cfg->usb2_ports[9].enable = radio_enable; + + dasharo_ec_smfi_cmd(CMD_WIFI_BT_ENABLEMENT_SET, 1, (uint8_t *)&radio_enable); +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c new file mode 100644 index 00000000000..ffdaf81eaab --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + memcfg_init(memupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/clevo/tgl-u/vboot-rwa.fmd b/src/mainboard/clevo/tgl-u/vboot-rwa.fmd new file mode 100644 index 00000000000..f20b4b1d1ef --- /dev/null +++ b/src/mainboard/clevo/tgl-u/vboot-rwa.fmd @@ -0,0 +1,39 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL 5M { + SI_DESC 4K + SI_ME + } + + RW_MISC 424K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_SHARED 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_NVRAM(PRESERVE) 24K + } + + CONSOLE 0x20000 + BOOTSPLASH(CBFS) 1M + + RW_SECTION_A { + VBLOCK_A 0x2000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + # align this with a WP region? + WP_RO 0x500000 { + RO_SECTION { + FMAP@0x0 0x800 + RO_FRID@0x800 0x100 + RO_FRID_PAD@0x900 0x700 + GBB@0x1000 0x3000 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig b/src/mainboard/dell/snb_ivb_workstations/Kconfig index a1e446ebe0c..1d31076686a 100644 --- a/src/mainboard/dell/snb_ivb_workstations/Kconfig +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig @@ -58,6 +58,9 @@ config USBDEBUG_HCD_INDEX config CBFS_SIZE default 0x600000 +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" + config INCLUDE_SMSC_SCH5545_EC_FW bool "Include SMSC SCH5545 EC firmware binary" default n diff --git a/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl b/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl index f890b5af541..9877edfa22f 100644 --- a/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl +++ b/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl @@ -38,17 +38,4 @@ Scope (\_GPE) Notify (\_SB.PCI0.EHC2, 0x02) Notify (\_SB.PCI0.GLAN, 0x02) } - - Method (_L09, 0, NotSerialized) - { - Notify (\_SB.PCI0.RP01, 0x02) - Notify (\_SB.PCI0.RP02, 0x02) - Notify (\_SB.PCI0.RP03, 0x02) - Notify (\_SB.PCI0.RP04, 0x02) - Notify (\_SB.PCI0.RP05, 0x02) - Notify (\_SB.PCI0.RP06, 0x02) - Notify (\_SB.PCI0.RP07, 0x02) - Notify (\_SB.PCI0.RP08, 0x02) - Notify (\_SB.PCI0.PEGP, 0x02) - } } diff --git a/src/mainboard/dell/snb_ivb_workstations/default.fmd b/src/mainboard/dell/snb_ivb_workstations/default.fmd new file mode 100644 index 00000000000..4313ea03360 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/default.fmd @@ -0,0 +1,19 @@ +FLASH@0xff400000 12M { + SI_ALL 6M { + SI_DESC 4K + SI_GBE 16K + SI_ME + } + UNUSED 2M + SI_BIOS 4M { + MISC_RW 384K { + SMMSTORE(PRESERVE) 256K + RW_MRC_CACHE 64K + RW_ELOG(PRESERVE) 64K + } + WP_RO { + FMAP 2K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/dell/snb_ivb_workstations/gpio.c b/src/mainboard/dell/snb_ivb_workstations/gpio.c index d01e6221a64..c4d48df21a4 100644 --- a/src/mainboard/dell/snb_ivb_workstations/gpio.c +++ b/src/mainboard/dell/snb_ivb_workstations/gpio.c @@ -32,7 +32,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio26 = GPIO_MODE_NATIVE, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, .gpio30 = GPIO_MODE_NATIVE, .gpio31 = GPIO_MODE_GPIO, /* Password Clear Jumper */ }; @@ -59,7 +59,6 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio24 = GPIO_DIR_INPUT, .gpio27 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, .gpio31 = GPIO_DIR_INPUT, }; @@ -69,7 +68,6 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio15 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, }; static const struct pch_gpio_set1 pch_gpio_set1_reset = { diff --git a/src/mainboard/dell/snb_ivb_workstations/mainboard.c b/src/mainboard/dell/snb_ivb_workstations/mainboard.c index c32121112a9..699a511ed27 100644 --- a/src/mainboard/dell/snb_ivb_workstations/mainboard.c +++ b/src/mainboard/dell/snb_ivb_workstations/mainboard.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -149,6 +150,15 @@ static void mainboard_enable(struct device *dev) } } +static void mainboard_init(void *chip_info) +{ + struct device *ps2_dev = dev_find_slot_pnp(0x2e, SCH5545_LDN_KBC); + bool ps2_en = get_ps2_option(); + + ps2_dev->enabled = ps2_en & 1; + printk(BIOS_DEBUG, "PS2 Controller state: %d\n", ps2_en); +} + static void mainboard_final(void *chip_info) { int pin_sts; @@ -186,6 +196,7 @@ static void mainboard_final(void *chip_info) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, + .init = mainboard_init, }; BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5545_ec_hwm_init, NULL); diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 2ba11b436ca..31f5cde69fc 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gpe0_en" = "0x00002a46" - register "alt_gp_smi_en" = "0x0004" - register "gpi2_routing" = "1" - register "gpi12_routing" = "2" register "gen1_dec" = "0x007c0a01" register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 70a7437fc8e..8f5b0fab4cb 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -31,6 +31,7 @@ config VBOOT config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-8M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-8M.fmd" if VBOOT_SLOTS_RW_AB + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" if ARCH_BOOTBLOCK_X86_64 diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd new file mode 100644 index 00000000000..17b4bedeff4 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xff800000 0x800000 { + BIOS 0x800000 { + SMMSTORE 0x40000 + FMAP 0x200 + BOOTSPLASH(CBFS) 0x40000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd index 55a38b79a94..ce2f686095c 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd @@ -6,6 +6,7 @@ FLASH@0xff800000 0x800000 { RW_FWID_A 0x40 } RW_VPD(PRESERVE) 0x1000 + BOOTSPLASH(CBFS) 0x40000 WP_RO { FMAP 0x800 diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd index 8064fdfeafe..63b6ad2c9ff 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd @@ -16,6 +16,7 @@ FLASH@0xff800000 0x800000 { } RW_VPD(PRESERVE) 0x1000 RW_LEGACY(CBFS) 0x10000 + BOOTSPLASH(CBFS) 0x40000 WP_RO { FMAP 0x800 RO_FRID 0x40 diff --git a/src/mainboard/hardkernel/odroid-h4/Kconfig b/src/mainboard/hardkernel/odroid-h4/Kconfig index 3e03116db75..35114a74e0d 100644 --- a/src/mainboard/hardkernel/odroid-h4/Kconfig +++ b/src/mainboard/hardkernel/odroid-h4/Kconfig @@ -23,6 +23,48 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "ODROID-H4" +config MAINBOARD_VENDOR + default "HARDKERNEL" + +config MAINBOARD_FAMILY + default "H4" + +config DIMM_SPD_SIZE + default 1024 + +config DIMM_MAX + default 2 + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config CBFS_SIZE + default 0xa00000 + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select HAS_RECOVERY_MRC_CACHE + select VBOOT_NO_TPM + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + config ODROID_H4_ENABLE_SAGV bool "Enable SAGV" default y @@ -38,4 +80,21 @@ config ODROID_H4_ENABLE_SAGV If unsure, keep enabled. If reflashing often, disabling this option can be useful to reduce memory training time. +config ODROID_H4_NETCARD_SUPPORT + bool "Enable 4x1 PCIe for Net Card 2 support in M.2 NVME slot" + default n + help + Enables 4x1 PCIe for Net Card 2 support in the project. Enable + this option when the M.2 NVMe slot is bifurcated as 4x1 to + support the Net Card 2. The option alone does not guarantee + that the bifurcation is enabled in the Intel Flash Descriptor. + Use proper flash desriptor when enabling this option. + + By default the slot is bifurcated as 1x4 for NVMe. + +config OVERRIDE_DEVICETREE + string + default "overridetree_netcard.cb" if ODROID_H4_NETCARD_SUPPORT + default "overridetree_nvme.cb" + endif #BOARD_HARDKERNEL_ODROID_H4 diff --git a/src/mainboard/hardkernel/odroid-h4/Makefile.mk b/src/mainboard/hardkernel/odroid-h4/Makefile.mk index 2e6759f0936..6e2926fa3b0 100644 --- a/src/mainboard/hardkernel/odroid-h4/Makefile.mk +++ b/src/mainboard/hardkernel/odroid-h4/Makefile.mk @@ -5,3 +5,9 @@ bootblock-y += bootblock.c romstage-y += romstage_fsp_params.c ramstage-y += mainboard.c + +romstage-y += gpio.c +ramstage-y += gpio.c + +bootblock-y += die.c +romstage-y += die.c diff --git a/src/mainboard/hardkernel/odroid-h4/acpi/superio.asl b/src/mainboard/hardkernel/odroid-h4/acpi/superio.asl new file mode 100644 index 00000000000..b7d6a64799d --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/acpi/superio.asl @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8613E_SHOW_UARTA + +#include diff --git a/src/mainboard/hardkernel/odroid-h4/bootblock.c b/src/mainboard/hardkernel/odroid-h4/bootblock.c index 31db1352812..0999067b150 100644 --- a/src/mainboard/hardkernel/odroid-h4/bootblock.c +++ b/src/mainboard/hardkernel/odroid-h4/bootblock.c @@ -1,18 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include #include #define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) #define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) +#define ITE_GPIO_BASE 0xa00 +#define ITE_GPIO_PIN(x) (1 << ((x) % 10)) +#define ITE_GPIO_SET(x) (((x) / 10) - 1) +#define ITE_GPIO_IO_ADDR(x) (ITE_GPIO_BASE + ITE_GPIO_SET(x)) + +static void ite_set_gpio_iobase(u16 iobase) +{ + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(GPIO_DEV); +} + void bootblock_mainboard_early_init(void) { - /* Set up Super I/O GPIOs, values are dumped from vendor firmware */ + /* Set up Super I/O GPIOs, some values are dumped from vendor firmware */ + + /* Internal VCC_OK */ + ite_reg_write(GPIO_DEV, 0x23, 0x40); + /* Pin7 as GP23 - USB2_EN */ ite_reg_write(GPIO_DEV, 0x26, 0xfb); + /* Pin24 as GPO50 (value of 0 on bit0 is reserved, JP1 strapping)*/ ite_reg_write(GPIO_DEV, 0x29, 0x01); + /* K8 power sequence software disabled */ ite_reg_write(GPIO_DEV, 0x2c, 0x41); + /* PCICLK 25MHz */ ite_reg_write(GPIO_DEV, 0x2d, 0x02); ite_reg_write(GPIO_DEV, 0xbc, 0xc0); ite_reg_write(GPIO_DEV, 0xbd, 0x03); @@ -22,6 +44,19 @@ void bootblock_mainboard_early_init(void) ite_reg_write(GPIO_DEV, 0xda, 0xb0); ite_reg_write(GPIO_DEV, 0xdb, 0x44); + ite_kill_watchdog(GPIO_DEV); + /* GP21 - USB3_EN, VBUS power gate for the USB3.x ports */ + ite_gpio_setup(GPIO_DEV, 21, + ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_CONTROL_DEFAULT); + /* GP23 - USB2_EN, VBUS power gate for the USB2.x ports */ + ite_gpio_setup(GPIO_DEV, 23, + ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_CONTROL_DEFAULT); + + ite_set_gpio_iobase(ITE_GPIO_BASE); + /* GP21 and GP23 to low to enable USB ports VBUS */ + outb(inb(ITE_GPIO_IO_ADDR(21)) & ~ITE_GPIO_PIN(21), ITE_GPIO_IO_ADDR(21)); + outb(inb(ITE_GPIO_IO_ADDR(23)) & ~ITE_GPIO_PIN(23), ITE_GPIO_IO_ADDR(23)); + ite_delay_pwrgd3(GPIO_DEV); ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/hardkernel/odroid-h4/data.vbt b/src/mainboard/hardkernel/odroid-h4/data.vbt index a3c168fce30..c0432b81166 100644 Binary files a/src/mainboard/hardkernel/odroid-h4/data.vbt and b/src/mainboard/hardkernel/odroid-h4/data.vbt differ diff --git a/src/mainboard/hardkernel/odroid-h4/devicetree.cb b/src/mainboard/hardkernel/odroid-h4/devicetree.cb index 48f35fd421f..d18a20749b0 100644 --- a/src/mainboard/hardkernel/odroid-h4/devicetree.cb +++ b/src/mainboard/hardkernel/odroid-h4/devicetree.cb @@ -5,22 +5,34 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "PMC_GPP_R" register "pmc_gpe0_dw2" = "PMC_GPD" - register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" + # FSP configuration + register "eist_enable" = "true" + # Sagv Configuration + register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" + register "RMT" = "0" register "enable_c6dram" = "true" register "tcc_offset" = "10" # TCC of 90C + register "ibecc" = "{ + .enable = false, + .mode = IBECC_MODE_ALL + }" + device domain 0 on + subsystemid 0x8086 0x7270 inherit device ref igpu on - register "ddi_portA_config" = "1" - register "ddi_portB_config" = "1" + register "ddi_portA_config" = "1" # HDMI on port A + register "ddi_portB_config" = "1" # DP on port B + # Fixed DP in TCP0 register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end + device ref xhci on ## Yes, the numbering of the three USB2 ports routed to the EXT_HEAD1 ## pin header does not correlate with the numbering of the USB2 ports @@ -61,12 +73,18 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A (Bottom Right)"" register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" device ref usb2_port1 on end device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A (Top Right)"" register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" device ref usb2_port2 on end device ref usb3_port2 on end end @@ -83,6 +101,9 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A (Top Left)"" register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" device ref usb2_port5 on end end chip drivers/usb/acpi @@ -93,11 +114,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A (Bottom Left)"" register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" device ref usb2_port7 on end end end end end + device ref i2c0 on register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" register "common_soc_config.i2c[0]" = "{ @@ -114,69 +139,60 @@ chip soc/intel/alderlake .fall_time_ns = 110, }" end + device ref heci1 on end + device ref sata on + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 0, + [1] = 1, + }" + + register "sata_ports_hotplug" = "{ + [0] = 0, + [1] = 1, + }" + end + device ref emmc on register "emmc_enable_hs400_mode" = "true" end - device ref pcie_rp3 on # LAN1 + + device ref pcie_rp3 on # LAN1 Intel i226 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref pcie_rp4 on # LAN2 + device ref pcie_rp4 on # LAN2 Intel i226 register "pch_pcie_rp[PCH_RP(4)]" = "{ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref pcie_rp7 on # ASM1064B SATA + device ref pcie_rp7 on # ASM1064B SATA (ASMedia PCie to 4xSATA) register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 3, .clk_req = 3, // Use hardwired CLKREQ# to allow clock gating .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref pcie_rp9 on # M.2 M (x4) - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 0, - .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, - }" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" - "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X" - end + device ref pch_espi on + # LPC generic I/O ranges register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x007c0a01" register "gen3_dec" = "0x000c03e1" register "gen4_dec" = "0x001c02e1" chip superio/ite/it8613e - register "ec.vin_mask" = "VIN0 | VIN1 | VIN2 | VIN4 | VIN5" - # TODO: figure out how to make PECI work - register "TMPIN1.mode" = "THERMAL_DIODE" - #register "TMPIN1.mode" = "THERMAL_PECI" - #register "TMPIN1.offset" = "0x56" - register "FAN2" = "{ - .mode = FAN_SMART_AUTOMATIC, - .smart = { - .tmpin = 1, - .tmp_off = 20, - .tmp_start = 35, - .tmp_full = 70, - .tmp_delta = 1, - .pwm_start = 20, - .slope = 3, - .smoothing = 0, - }, - }" - device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 irq 0x70 = 4 irq 0xf0 = 0x01 + irq 0xf1 = 0x52 # IRQ low level end device pnp 2e.4 on # Environment Controller io 0x60 = 0xa30 @@ -194,8 +210,8 @@ chip soc/intel/alderlake device pnp 2e.a off end # CIR end end + device ref p2sb hidden end device ref hda on - register "pch_hda_dsp_enable" = "true" register "pch_hda_sdi_enable[0]" = "true" register "pch_hda_audio_link_hda_enable" = "true" register "pch_hda_idisp_codec_enable" = "true" diff --git a/src/mainboard/hardkernel/odroid-h4/die.c b/src/mainboard/hardkernel/odroid-h4/die.c new file mode 100644 index 00000000000..85fe2299c79 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/die.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void die_notify(void) +{ + static uint8_t blink = 0; + + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink */ + gpio_output(GPP_B14, 0); + + while (1) { + gpio_set(GPP_B14, blink); + blink ^= 1; + mdelay(500); + } +} diff --git a/src/mainboard/hardkernel/odroid-h4/dsdt.asl b/src/mainboard/hardkernel/odroid-h4/dsdt.asl index 584f330cbb1..a6e97c4ceb9 100644 --- a/src/mainboard/hardkernel/odroid-h4/dsdt.asl +++ b/src/mainboard/hardkernel/odroid-h4/dsdt.asl @@ -22,5 +22,10 @@ DefinitionBlock( #include } + Scope (\_SB.PCI0.LPCB) + { + #include "acpi/superio.asl" + } + #include } diff --git a/src/mainboard/hardkernel/odroid-h4/gpio.c b/src/mainboard/hardkernel/odroid-h4/gpio.c new file mode 100644 index 00000000000..38b8568f098 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/gpio.c @@ -0,0 +1,620 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "gpio.h" + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* GPP_B3 - GPIO */ + PAD_NC(GPP_B3, NONE), + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO EMMC_DET# */ + PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SATA_LED# */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4), + /* GPP_B15 - GPIO */ + PAD_NC(GPP_B15, NONE), + /* GPP_B16 - GPIO */ + PAD_NC(GPP_B16, NONE), + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_NC(GPP_B18, NONE), + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + /* GPP_B23 - GPIO */ + PAD_NC(GPP_B23, NONE), + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + /* GPP_T0 - GPIO */ + PAD_NC(GPP_T0, NONE), + /* GPP_T1 - GPIO */ + PAD_NC(GPP_T1, NONE), + /* GPP_T2 - GPIO */ + PAD_NC(GPP_T2, NONE), + /* GPP_T3 - GPIO */ + PAD_NC(GPP_T3, NONE), + /* GPP_T4 - GPIO */ + PAD_NC(GPP_T4, NONE), + /* GPP_T5 - GPIO */ + PAD_NC(GPP_T5, NONE), + /* GPP_T6 - GPIO */ + PAD_NC(GPP_T6, NONE), + /* GPP_T7 - GPIO */ + PAD_NC(GPP_T7, NONE), + /* GPP_T8 - GPIO */ + PAD_NC(GPP_T8, NONE), + /* GPP_T9 - GPIO */ + PAD_NC(GPP_T9, NONE), + /* GPP_T10 - GPIO */ + PAD_NC(GPP_T10, NONE), + /* GPP_T11 - GPIO */ + PAD_NC(GPP_T11, NONE), + /* GPP_T12 - GPIO */ + PAD_NC(GPP_T12, NONE), + /* GPP_T13 - GPIO */ + PAD_NC(GPP_T13, NONE), + /* GPP_T14 - GPIO */ + PAD_NC(GPP_T14, NONE), + /* GPP_T15 - GPIO */ + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + /* GPP_A6 - GPIO */ + PAD_NC(GPP_A6, NONE), + /* GPP_A7 - GPIO */ + PAD_NC(GPP_A7, NONE), + /* GPP_A8 - LAN_DISABLE# */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), +#if CONFIG(ODROID_H4_NETCARD_SUPPORT) + /* GPP_A12 - GPIO - unused with netcard support */ + PAD_NC(GPP_A12, NONE), +#else + /* GPP_A12 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), +#endif + /* GPP_A13 - GPIO */ + PAD_NC(GPP_A13, NONE), + /* GPP_A14 - GPIO */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15 - GPIO */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16 - GPIO */ + PAD_NC(GPP_A16, NONE), + /* GPP_A17 - GPIO */ + PAD_NC(GPP_A17, NONE), + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* GPP_A20 - GPIO */ + PAD_NC(GPP_A20, NONE), + /* GPP_A21 - GPIO */ + PAD_NC(GPP_A21, NONE), + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NONE), + /* GPP_A23 - GPIO */ + PAD_NC(GPP_A23, NONE), + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + + /* GPP_I5 - GPIO */ + PAD_NC(GPP_I5, NONE), + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_NC(GPP_H0, NONE), + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + /* GPP_H2 - GPIO */ + PAD_NC(GPP_H2, NONE), + /* GPP_H3 - GPIO */ + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* GPP_H6 - I2C1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* GPP_H7 - I2C1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* GPP_H8 - GPIO */ + PAD_NC(GPP_H8, NONE), + /* GPP_H9 - GPIO */ + PAD_NC(GPP_H9, NONE), + /* GPP_H10 - GPIO */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11, NONE), + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12, NONE), + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16, NONE), + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19, NONE), + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_NC(GPP_D0, NONE), + /* GPP_D1 - GPIO */ + PAD_NC(GPP_D1, NONE), + /* GPP_D2 - GPIO */ + PAD_NC(GPP_D2, NONE), + /* GPP_D3 - GPIO */ + PAD_NC(GPP_D3, NONE), + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), +#if CONFIG(ODROID_H4_NETCARD_SUPPORT) + /* GPP_D5 - GPIO */ + /* Do not use SRCCLKREQ0# to PCIE RP 9 (NVMe), as the clock becomes shared */ + PAD_NC(GPP_D5, NONE), +#else + /* GPP_D5 - SRCCLKREQ0# to PCIE RP 9 (NVMe) */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +#endif + /* GPP_D6 - SRCCLKREQ1# to PCIE RP 3 (LAN1) */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPP_D7 - SRCCLKREQ2# to PCIE RP 4 (LAN2) */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D8 - SRCCLKREQ3# presumably for PCIE RP7, but permanently grounded? */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NATIVE), + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NATIVE), + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NATIVE), + /* GPP_D12 - GPIO */ + PAD_NC(GPP_D12, NATIVE), + /* GPP_D13 - GPIO */ + PAD_NC(GPP_D13, NONE), + /* GPP_D14 - GPIO */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + /* GPP_VGPIO_THC0 - GPP_VGPIO_THC0 */ + PAD_CFG_NF(GPP_VGPIO_THC0, NONE, DEEP, NF1), + /* GPP_VGPIO_THC1 - GPP_VGPIO_THC1 */ + PAD_CFG_NF(GPP_VGPIO_THC1, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + /* GPD2 - GPIO */ + PAD_NC(GPD2, NONE), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + /* GPD7 - GPIO */ + PAD_NC(GPD7, NONE), + /* GPD8 - SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + /* GPD11 - GPIO */ + PAD_NC(GPD11, NONE), + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* GPP_C2 - GPIO */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - GPIO */ + PAD_NC(GPP_C3, NONE), + /* GPP_C4 - GPIO */ + PAD_NC(GPP_C4, NONE), + /* GPP_C5 - GPIO */ + PAD_NC(GPP_C5, NONE), + /* GPP_C6 - GPIO */ + PAD_NC(GPP_C6, NONE), + /* GPP_C7 - GPIO */ + PAD_NC(GPP_C7, NONE), + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - GPIO */ + PAD_NC(GPP_F0, NONE), + /* GPP_F1 - GPIO */ + PAD_NC(GPP_F1, NONE), + /* GPP_F2 - GPIO */ + PAD_NC(GPP_F2, NONE), + /* GPP_F3 - GPIO */ + PAD_NC(GPP_F3, NONE), + /* GPP_F4 - GPIO# */ + PAD_NC(GPP_F4, NONE), + /* GPP_F5 - GPIO */ + PAD_NC(GPP_F5, NONE), + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + /* GPP_F7 - GPIO */ + PAD_NC(GPP_F7, NONE), + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + /* GPP_F9 - GPIO */ + PAD_NC(GPP_F9, NONE), + /* GPP_F10 - GPIO */ + PAD_NC(GPP_F10, NONE), + /* GPP_F11 - GPIO */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12 - GPIO */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13 - GPIO */ + PAD_NC(GPP_F13, NONE), + /* GPP_F14 - GPIO */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15 - GPIO */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16 - GPIO */ + PAD_NC(GPP_F16, NONE), + /* GPP_F17 - GPIO */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20 - Reserved */ + PAD_NC(GPP_F20, NONE), + /* GPP_F21 - Reserved */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + PAD_NC(GPP_L_BKLTEN, NONE), + /* GPP_L_BKLTCTL - n/a */ + PAD_NC(GPP_L_BKLTCTL, NONE), + /* GPP_L_VDDEN - n/a */ + PAD_NC(GPP_L_VDDEN, NONE), + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + /* GPP_E1 - GPIO */ + PAD_NC(GPP_E1, NONE), + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + /* GPP_E3 - GPIO */ + PAD_NC(GPP_E3, NONE), + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + /* GPP_E5 - GPIO */ + PAD_NC(GPP_E5, NONE), + /* GPP_E6 - GPIO */ + PAD_NC(GPP_E6, NONE), + /* GPP_E7 - GPIO */ + PAD_NC(GPP_E7, NONE), + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 - GPIO */ + PAD_NC(GPP_E13, NONE), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 - Reserved */ + PAD_NC(GPP_E15, NONE ), + /* GPP_E16 - Connetced to pad 67 in M.2 NVMe slot */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* GPP_E17 - GPIO */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18 - DDP1_CTRLCLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* GPP_E19 - DDP1_CTRLDATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NATIVE), + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NATIVE), + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE) +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/hardkernel/odroid-h4/gpio.h b/src/mainboard/hardkernel/odroid-h4/gpio.h new file mode 100644 index 00000000000..c6f88485c59 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef HARDKERNEL_ODROID_H4_GPIO_H +#define HARDKERNEL_ODROID_H4_GPIO_H + +const struct pad_config *board_gpio_table(size_t *num); + +#endif /* HARDKERNEL_ODROID_H4_GPIO_H */ diff --git a/src/mainboard/hardkernel/odroid-h4/mainboard.c b/src/mainboard/hardkernel/odroid-h4/mainboard.c index d8cfc8814d7..37cad4c57e9 100644 --- a/src/mainboard/hardkernel/odroid-h4/mainboard.c +++ b/src/mainboard/hardkernel/odroid-h4/mainboard.c @@ -1,219 +1,31 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include +#include #include +#include +#include +#include -/* - * Pad configuration was derived from schematics, revision 0.1 - * - https://wiki.odroid.com/odroid-h4/hardware#odroid-h4_schematics - */ -static const struct pad_config gpio_table[] = { - - /* ------- GPIO Group GPP_A ------- */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* ESPI_IO0 */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* ESPI_IO1 */ - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* ESPI_IO2 */ - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* ESPI_IO3 */ - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* ESPI_CS# */ - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* ESPI_ALERT# */ - PAD_NC(GPP_A6, NONE), - PAD_NC(GPP_A7, NONE), - PAD_CFG_GPO(GPP_A8, 1, PLTRST), /* LAN_DISABLE# */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* ESPI_CLK */ - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ - PAD_NC(GPP_A11, NONE), - PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* M.2_SSD_PEDET_R */ - PAD_NC(GPP_A13, NONE), - PAD_NC(GPP_A14, NONE), - PAD_NC(GPP_A15, NONE), - PAD_NC(GPP_A16, NONE), - PAD_NC(GPP_A17, NONE), - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDI1_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* TCP0_HPD */ - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_NC(GPP_A23, NONE), - - /* ------- GPIO Group GPP_B ------- */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ - PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* VRALERT# */ - PAD_NC(GPP_B3, NONE), - PAD_NC(GPP_B4, NONE), - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_CFG_GPI(GPP_B8, NONE, DEEP), /* EMMC_DET#_L */ - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PMCALERT# */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PM_PLTRST_N */ - PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF4), /* PCH_SATA_LED# */ - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_NC(GPP_B17, NONE), - PAD_NC(GPP_B18, NONE), - PAD_NC(GPP_B23, NONE), - - /* ------- GPIO Group GPP_C ------- */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ - PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* SMB_ALERT# */ - PAD_NC(GPP_C3, NONE), - PAD_NC(GPP_C4, NONE), - PAD_NC(GPP_C5, NONE), - PAD_NC(GPP_C6, NONE), - PAD_NC(GPP_C7, NONE), - - /* ------- GPIO Group GPP_D ------- */ - PAD_NC(GPP_D0, NONE), - PAD_NC(GPP_D1, NONE), - PAD_NC(GPP_D2, NONE), - PAD_NC(GPP_D3, NONE), - PAD_NC(GPP_D4, NONE), - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCIE_CLKREQ0_N */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCIE_CLKREQ1_N */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* PCIE_CLKREQ2_N */ - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* CLKREQ3# but always asserted */ - PAD_NC(GPP_D9, NONE), - PAD_NC(GPP_D10, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_NC(GPP_D16, NONE), - PAD_NC(GPP_D17, NONE), - PAD_NC(GPP_D18, NONE), - PAD_NC(GPP_D19, NONE), - - /* ------- GPIO Group GPP_E ------- */ - PAD_NC(GPP_E0, NONE), - PAD_NC(GPP_E1, NONE), - PAD_NC(GPP_E2, NONE), - PAD_NC(GPP_E3, NONE), - PAD_NC(GPP_E4, NONE), - PAD_NC(GPP_E5, NONE), - PAD_NC(GPP_E6, NONE), - PAD_NC(GPP_E7, NONE), - PAD_NC(GPP_E8, NONE), - PAD_NC(GPP_E9, NONE), - PAD_NC(GPP_E10, NONE), - PAD_NC(GPP_E11, NONE), - PAD_NC(GPP_E12, NONE), - PAD_NC(GPP_E13, NONE), - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */ - PAD_NC(GPP_E15, NONE), - PAD_NC(GPP_E16, NONE), /* Unknown, goes to M.2 pin 67 (NC) */ - PAD_NC(GPP_E17, NONE), - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* TCP0_DDCCLK */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* TCP0_DDCDATA */ - PAD_NC(GPP_E20, NONE), - PAD_NC(GPP_E21, NONE), - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), /* DDI0_DDCCLK */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDI0_DDCDATA */ - - /* ------- GPIO Group GPP_F ------- */ - PAD_NC(GPP_F0, NONE), - PAD_NC(GPP_F1, NONE), - PAD_NC(GPP_F2, NONE), - PAD_NC(GPP_F3, NONE), - PAD_NC(GPP_F4, NONE), - PAD_NC(GPP_F5, NONE), - PAD_NC(GPP_F6, NONE), - PAD_NC(GPP_F7, NONE), - PAD_NC(GPP_F10, NONE), - PAD_NC(GPP_F11, NONE), - PAD_NC(GPP_F12, NONE), - PAD_NC(GPP_F13, NONE), - PAD_NC(GPP_F14, NONE), - PAD_NC(GPP_F15, NONE), - PAD_NC(GPP_F16, NONE), - PAD_NC(GPP_F17, NONE), - PAD_NC(GPP_F18, NONE), - PAD_NC(GPP_F22, NONE), - PAD_NC(GPP_F23, NONE), - - /* ------- GPIO Group GPP_H ------- */ - PAD_NC(GPP_H0, NONE), - PAD_NC(GPP_H1, NONE), - PAD_NC(GPP_H2, NONE), - PAD_NC(GPP_H3, NONE), - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* I2C_0_SDA */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* I2C_0_SCL */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C_1_SDA */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C_1_SCL */ - PAD_NC(GPP_H8, NONE), - PAD_NC(GPP_H9, NONE), - PAD_NC(GPP_H10, NONE), - PAD_NC(GPP_H11, NONE), - PAD_NC(GPP_H12, NONE), - PAD_NC(GPP_H13, NONE), - PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDI1_DDCCLK */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDI1_DDCDATA */ - PAD_NC(GPP_H18, NONE), - PAD_NC(GPP_H19, NONE), - PAD_NC(GPP_H20, NONE), - PAD_NC(GPP_H21, NONE), - PAD_NC(GPP_H22, NONE), - PAD_NC(GPP_H23, NONE), - - /* ------- GPIO Group GPP_I ------- */ - PAD_NC(GPP_I5, NONE), - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */ - PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA_0 */ - PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA_1 */ - PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA_2 */ - PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA_3 */ - PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA_4 */ - PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA_5 */ - PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA_6 */ - PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA_7 */ - PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */ - PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */ - - /* ------- GPIO Group GPP_R ------- */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK_R */ - PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC_R */ - PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), /* HDA_SDO_R */ - PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI_R */ - PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* HDA_RST_N */ - PAD_NC(GPP_R5, NONE), - PAD_NC(GPP_R6, NONE), - PAD_NC(GPP_R7, NONE), - - /* ------- GPIO Group GPP_S ------- */ - PAD_NC(GPP_S0, NONE), - PAD_NC(GPP_S1, NONE), - PAD_NC(GPP_S2, NONE), - PAD_NC(GPP_S3, NONE), - PAD_NC(GPP_S4, NONE), - PAD_NC(GPP_S5, NONE), - PAD_NC(GPP_S6, NONE), - PAD_NC(GPP_S7, NONE), - - /* ------- GPIO Group GPP_GPD ------- */ - PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* BATLOW# */ - PAD_CFG_NF(GPD1, NONE, PWROK, NF1), /* ACPRESENT */ - PAD_NC(GPD2, NONE), - PAD_CFG_NF(GPD3, NONE, PWROK, NF1), /* PM_PWRBTN# */ - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ - PAD_NC(GPD7, NONE), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ - PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ - PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ - PAD_NC(GPD11, NONE), -}; - -static void mainboard_init(void *chip_info) +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + params->PcieRpEnableCpm[2] = 1; // LAN1 + params->PcieRpEnableCpm[3] = 1; // LAN2 + params->PcieRpEnableCpm[6] = 1; // ASMedia PCIe to SATA + if (!CONFIG(ODROID_H4_NETCARD_SUPPORT)) + params->PcieRpEnableCpm[8] = 1; // NVMe + + // Max payload 256B + memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload)); + + // I2C + params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6 + params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7 + + params->CnviRfResetPinMux = 0; + params->CnviClkreqPinMux = 0; } - -struct chip_operations mainboard_ops = { - .init = mainboard_init, -}; diff --git a/src/mainboard/hardkernel/odroid-h4/overridetree_netcard.cb b/src/mainboard/hardkernel/odroid-h4/overridetree_netcard.cb new file mode 100644 index 00000000000..c77a6613e29 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/overridetree_netcard.cb @@ -0,0 +1,39 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + device domain 0 on + register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" + # M.2 M NVMe (x4) bifurcated as 4x1 for netcard + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_CLK_SRC_UNUSED, + .pcie_rp_aspm = ASPM_DISABLE, + .PcieRpL1Substates = L1_SS_DISABLED, + }" + + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X" + end + device ref pcie_rp10 on + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_CLK_SRC_UNUSED, + .pcie_rp_aspm = ASPM_DISABLE, + .PcieRpL1Substates = L1_SS_DISABLED, + }" + end + device ref pcie_rp11 on + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_CLK_SRC_UNUSED, + .pcie_rp_aspm = ASPM_DISABLE, + .PcieRpL1Substates = L1_SS_DISABLED, + }" + end + device ref pcie_rp12 on + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_CLK_SRC_UNUSED, + .pcie_rp_aspm = ASPM_DISABLE, + .PcieRpL1Substates = L1_SS_DISABLED, + }" + end + end +end diff --git a/src/mainboard/hardkernel/odroid-h4/overridetree_nvme.cb b/src/mainboard/hardkernel/odroid-h4/overridetree_nvme.cb new file mode 100644 index 00000000000..f59a2fc5c4d --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/overridetree_nvme.cb @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + device domain 0 on + device ref pcie_rp9 on # M.2 M NVMe (x4) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X" + end + end +end diff --git a/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c b/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c index 549a4bdc347..683f31911f7 100644 --- a/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c +++ b/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c @@ -3,6 +3,9 @@ #include #include #include +#include + +#include "gpio.h" static const struct mb_cfg ddr5_mem_config = { .type = MEM_TYPE_DDR5, @@ -20,6 +23,14 @@ static const struct mem_spd dimm_module_spd_info = { void mainboard_memory_init_params(FSPM_UPD *memupd) { - const bool half_populated = true; + const struct pad_config *pads; + size_t num; + + const bool half_populated = false; memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); + + pads = board_gpio_table(&num); + gpio_configure_pads(pads, num); + + memupd->FspmConfig.DmiMaxLinkSpeed = 4; } diff --git a/src/mainboard/hardkernel/odroid-h4/vboot-rwa.fmd b/src/mainboard/hardkernel/odroid-h4/vboot-rwa.fmd new file mode 100644 index 00000000000..bfe0e6d73b6 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/vboot-rwa.fmd @@ -0,0 +1,36 @@ +FLASH@0xff000000 16M { + SI_ALL 6M { + SI_DESC 4K + SI_ME 0x413000 + SI_DEVICEEXT2 + } + SI_BIOS 10M { + SMMSTORE(PRESERVE) 256K + + RW_MISC 260K { + UNIFIED_MRC_CACHE(PRESERVE) { + RECOVERY_MRC_CACHE 128K + RW_MRC_CACHE 128K + } + RW_NVRAM(PRESERVE) 4K + } + + BOOTSPLASH(CBFS) 252K + + RW_SECTION_A { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + WP_RO 5M { + RO_SECTION { + FMAP 2K + RO_FRID 0x100 + RO_FRID_PAD 0x700 + GBB 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig new file mode 100644 index 00000000000..a6286a46dd3 --- /dev/null +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -0,0 +1,43 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_MINNOWMAX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_COM1 + select HAVE_SPD_IN_CBFS + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + string + default "intel/minnowmax" + +config MAINBOARD_PART_NUMBER + string + default "Minnow Max" + +config MAX_CPUS + int + default 16 + +config DIMM_SPD_SIZE + int + default 256 + +config CBFS_SIZE + hex + default 0x00600000 + +config POST_DEVICE + bool + default n + +config VGA_BIOS + bool + default y + +endif # BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/minnowmax/Kconfig.name b/src/mainboard/intel/minnowmax/Kconfig.name new file mode 100644 index 00000000000..a8606fccc8c --- /dev/null +++ b/src/mainboard/intel/minnowmax/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_INTEL_MINNOWMAX + bool "Minnow Max" diff --git a/src/mainboard/intel/minnowmax/Makefile.mk b/src/mainboard/intel/minnowmax/Makefile.mk new file mode 100644 index 00000000000..b7e5ce29c5f --- /dev/null +++ b/src/mainboard/intel/minnowmax/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +ramstage-y += irqroute.c + +#SPD_SOURCES = micron_1GiB_1066MHz_dimm_MT41K256M16HA-125 # 0b0000 +#SPD_SOURCES += micron_2GiB_1066MHz_dimm_MT41K256M16HA-125 # 0b0001 +#SPD_SOURCES += micron_1GiB_1333MHz_dimm_MT41K256M16HA-125 # 0b0010 +#SPD_SOURCES += micron_2GiB_1333MHz_dimm_MT41K256M16HA-125 # 0b0011 + +SPD_SOURCES = micron_1GiB_dimm_MT41K256M16HA-125 # 0b0000 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 # 0b0001 diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl new file mode 100644 index 00000000000..853b0877b33 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 00000000000..7d1b0a91168 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + }) + Method (_DIS, 0x0, NotSerialized) + { + //Add a dummy disable function + } +} + +Scope (\_SB) { + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl new file mode 100644 index 00000000000..853b0877b33 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c new file mode 100644 index 00000000000..d3b6582ddf9 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* No TPM Present */ + gnvs->tpmp = 0; + + /* Enable DPTF */ + gnvs->dpte = 0; +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/intel/minnowmax/board_info.txt b/src/mainboard/intel/minnowmax/board_info.txt new file mode 100644 index 00000000000..5af79f8de4b --- /dev/null +++ b/src/mainboard/intel/minnowmax/board_info.txt @@ -0,0 +1,4 @@ +Category: sbc +ROM protocol: SPI +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout new file mode 100644 index 00000000000..b3cea3cd0fc --- /dev/null +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -0,0 +1,95 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 2 e 8 use_xhci_over_ehci +#413 3 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +#save timestamps in pre-ram boot areas +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 EHCI +8 1 XHCI +8 2 Default +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/intel/minnowmax/data.vbt b/src/mainboard/intel/minnowmax/data.vbt new file mode 100644 index 00000000000..6b88c70142d Binary files /dev/null and b/src/mainboard/intel/minnowmax/data.vbt differ diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb new file mode 100644 index 00000000000..7c4caf45efa --- /dev/null +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -0,0 +1,80 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/baytrail + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for MinnowMax board + register "usb2_comp_bg" = "0x4680" + register "usb2_per_port_lane0" = "0x0004C209" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x0004B209" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on end + + device domain 0 on + device pci 00.0 on end # 8086 0F00 - SoC router + device pci 02.0 on end # 8086 0F31 - GFX micro HDMI + device pci 03.0 off end # 8086 0F38 - MIPI + device pci 10.0 off end # 8086 0F14 - EMMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 + device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC + device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime + device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC + device pci 17.0 off end # 8086 0F50 - MMC Port + device pci 18.0 on end # 8086 0F40 - SIO - DMA + device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) + device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints) + device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) + device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) + device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) + device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC + device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC + device pci 1a.0 on end # 8086 0F18 - TXE + device pci 1b.0 off end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on + device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models) + device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE + device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC + device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime + device pci 1e.0 on end # 8086 0F06 - SIO - DMA + device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC + device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC + device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC + device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC + device pci 1e.5 on end # 8086 0F0E - SPI LSEC + device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector + device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC + end +end diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl new file mode 100644 index 00000000000..09db35910de --- /dev/null +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + // Some generic macros + #include + + // global NVS and variables + #include + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + } + } + + /* Chipset specific sleep states */ + #include + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c new file mode 100644 index 00000000000..15c114129c8 --- /dev/null +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * The pads list is in the BWG_VOL2 Rev1p2: + * Note that Pad # is not the same as GPIO# + * 37 GPIO Handling: + * Table 37-1. SCORE Pads List + * Table 37-2. SSUSORE Pads List + */ + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, // GPIO_S0_NC[00] - HDMI_HPD + GPIO_FUNC2, // GPIO_S0_NC[01] - HDMI_DDCDAT + GPIO_FUNC2, // GPIO_S0_NC[02] - HDMI_DDCCLK + GPIO_NC, // GPIO_S0_NC[03] - No Connect + GPIO_NC, // GPIO_S0_NC[04] - No Connect + GPIO_NC, // GPIO_S0_NC[05] - No Connect + GPIO_NC, // GPIO_S0_NC[06] - No Connect + GPIO_FUNC2, // GPIO_S0_NC[07] - DDI1_DDCDAT + GPIO_NC, // GPIO_S0_NC[08] - No Connect + GPIO_NC, // GPIO_S0_NC[09] - No Connect + GPIO_NC, // GPIO_S0_NC[10] - No Connect + GPIO_NC, // GPIO_S0_NC[11] - No Connect + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_NC[12] - TP15 + GPIO_NC, // GPIO_S0_NC[13] - No Connect + GPIO_NC, // GPIO_S0_NC[14] - No Connect + GPIO_NC, // GPIO_S0_NC[15] - No Connect + GPIO_NC, // GPIO_S0_NC[16] - No Connect + GPIO_NC, // GPIO_S0_NC[17] - No Connect + GPIO_NC, // GPIO_S0_NC[18] - No Connect + GPIO_NC, // GPIO_S0_NC[19] - No Connect + GPIO_NC, // GPIO_S0_NC[20] - No Connect + GPIO_NC, // GPIO_S0_NC[21] - No Connect + GPIO_NC, // GPIO_S0_NC[22] - No Connect + GPIO_NC, // GPIO_S0_NC[23] - No Connect + GPIO_NC, // GPIO_S0_NC[24] - No Connect + GPIO_NC, // GPIO_S0_NC[25] - No Connect + GPIO_NC, // GPIO_S0_NC[26] - No Connect + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX) */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, // GPIO_S0_SC[000] - SATA_GP0 + GPIO_FUNC1, // GPIO_S0_SC[001] - SATA_GP1 + GPIO_FUNC1, // GPIO_S0_SC[002] - SATA_LED_B + GPIO_FUNC1, // GPIO_S0_SC[003] - PCIE_CLKREQ_0 + GPIO_FUNC1, // GPIO_S0_SC[004] - PCIE_CLKREQ_1 + GPIO_FUNC1, // GPIO_S0_SC[005] - PCIE_CLKREQ_2 + GPIO_FUNC1, // GPIO_S0_SC[006] - PCIE_CLKREQ_3 + GPIO_FUNC2, // GPIO_S0_SC[007] - SD3_WP + GPIO_NC, // GPIO_S0_SC[008] - No Connect + GPIO_NC, // GPIO_S0_SC[009] - No Connect + GPIO_NC, // GPIO_S0_SC[010] - No Connect + GPIO_NC, // GPIO_S0_SC[011] - No Connect + GPIO_NC, // GPIO_S0_SC[012] - No Connect + GPIO_NC, // GPIO_S0_SC[013] - No Connect + GPIO_NC, // GPIO_S0_SC[014] - No Connect + GPIO_NC, // GPIO_S0_SC[015] - No Connect + GPIO_NC, // GPIO_S0_SC[016] - No Connect + GPIO_NC, // GPIO_S0_SC[017] - No Connect + GPIO_NC, // GPIO_S0_SC[018] - No Connect + GPIO_NC, // GPIO_S0_SC[019] - No Connect + GPIO_NC, // GPIO_S0_SC[020] - No Connect + GPIO_NC, // GPIO_S0_SC[021] - No Connect + GPIO_NC, // GPIO_S0_SC[022] - No Connect + GPIO_NC, // GPIO_S0_SC[023] - No Connect + GPIO_NC, // GPIO_S0_SC[024] - No Connect + GPIO_NC, // GPIO_S0_SC[025] - No Connect + GPIO_NC, // GPIO_S0_SC[026] - No Connect + GPIO_NC, // GPIO_S0_SC[027] - No Connect + GPIO_NC, // GPIO_S0_SC[028] - No Connect + GPIO_NC, // GPIO_S0_SC[029] - No Connect + GPIO_NC, // GPIO_S0_SC[030] - No Connect + GPIO_NC, // GPIO_S0_SC[031] - No Connect + GPIO_NC, // GPIO_S0_SC[032] - No Connect + GPIO_FUNC1, // GPIO_S0_SC[033] - SD3_CLK + GPIO_FUNC1, // GPIO_S0_SC[034] - SD3_D0 + GPIO_FUNC1, // GPIO_S0_SC[035] - SD3_D1 + GPIO_FUNC1, // GPIO_S0_SC[036] - SD3_D2 + GPIO_FUNC1, // GPIO_S0_SC[037] - SD3_D3 + GPIO_FUNC1, // GPIO_S0_SC[038] - SD3_CD# + GPIO_FUNC1, // GPIO_S0_SC[039] - SD3_CMD + GPIO_FUNC1, // GPIO_S0_SC[040] - TP12 (SD3_1P8EN) + GPIO_FUNC1, // GPIO_S0_SC[041] - TP11 (/SD3_PWREN) + GPIO_NC, // GPIO_S0_SC[042] - No Connect + GPIO_NC, // GPIO_S0_SC[043] - No Connect + GPIO_NC, // GPIO_S0_SC[044] - No Connect + GPIO_NC, // GPIO_S0_SC[045] - No Connect + GPIO_NC, // GPIO_S0_SC[046] - No Connect + GPIO_NC, // GPIO_S0_SC[047] - No Connect + GPIO_NC, // GPIO_S0_SC[048] - No Connect + GPIO_NC, // GPIO_S0_SC[049] - No Connect + GPIO_NC, // GPIO_S0_SC[050] - No Connect + GPIO_FUNC1, // GPIO_S0_SC[051] - PCU_SMB_DATA + GPIO_FUNC1, // GPIO_S0_SC[052] - PCU_SMB_CLK + GPIO_FUNC1, // GPIO_S0_SC[053] - PCU_SMB_ALERT + GPIO_FUNC1, // GPIO_S0_SC[054] - ILB_8254_SPKR + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55) + GPIO_FUNC0, // GPIO_S0_SC[056] - GPIO_S0_SC_56 + GPIO_FUNC1, // GPIO_S0_SC[057] - PCU_UART3_TXD + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58) + GPIO_FUNC0, // GPIO_S0_SC[059] - HDMI_DCDC_ENB + GPIO_FUNC0, // GPIO_S0_SC[060] - HDMI_LDSW_ENB + GPIO_FUNC1, // GPIO_S0_SC[061] - PCU_UART3_RXD + GPIO_FUNC1, // GPIO_S0_SC[062] - LPE_I2S_CLK + GPIO_FUNC1, // GPIO_S0_SC[063] - LPE_I2S_FRM + GPIO_FUNC1, // GPIO_S0_SC[064] - LPE_I2S_DATIN + GPIO_FUNC1, // GPIO_S0_SC[065] - LPE_I2S_DATOUT + GPIO_FUNC1, // GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 + GPIO_FUNC1, // GPIO_S0_SC[067] - SOC_SIO_SPI_MISO + GPIO_FUNC1, // GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI + GPIO_FUNC1, // GPIO_S0_SC[069] - SOC_SIO_SPI_CLK + GPIO_FUNC1, // GPIO_S0_SC[070] - SIO_UART1_RXD + GPIO_FUNC1, // GPIO_S0_SC[071] - SIO_UART1_TXD + GPIO_FUNC1, // GPIO_S0_SC[072] - SIO_UART1_RTSB + GPIO_FUNC1, // GPIO_S0_SC[073] - SIO_UART1_CTSB + GPIO_FUNC1, // GPIO_S0_SC[074] - SIO_UART2_RXD + GPIO_FUNC1, // GPIO_S0_SC[075] - SIO_UART2_TXD + GPIO_NC, // GPIO_S0_SC[076] - No Connect + GPIO_NC, // GPIO_S0_SC[077] - No Connect + GPIO_NC, // GPIO_S0_SC[078] - No Connect + GPIO_NC, // GPIO_S0_SC[079] - No Connect + GPIO_FUNC1, // GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA) + GPIO_FUNC1, // GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL) + GPIO_NC, // GPIO_S0_SC[082] - No Connect + GPIO_NC, // GPIO_S0_SC[083] - No Connect + GPIO_NC, // GPIO_S0_SC[084] - No Connect + GPIO_NC, // GPIO_S0_SC[085] - No Connect + GPIO_NC, // GPIO_S0_SC[086] - No Connect + GPIO_NC, // GPIO_S0_SC[087] - No Connect + GPIO_FUNC1, // GPIO_S0_SC[088] - LSS_I2C_SDA + GPIO_FUNC1, // GPIO_S0_SC[089] - LSS_I2C_SCL + GPIO_FUNC1, // GPIO_S0_SC[090] - EXP_I2C_SDA + GPIO_FUNC1, // GPIO_S0_SC[091] - EXP_I2C_SCL + GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[092] - TP13 + GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[093] - TP16 + GPIO_FUNC1, // GPIO_S0_SC[094] - SOC_PWM0 + GPIO_FUNC1, // GPIO_S0_SC[095] - SOC_PWM1 + GPIO_NC, // GPIO_S0_SC[096] - No Connect + GPIO_NC, // GPIO_S0_SC[097] - No Connect + GPIO_NC, // GPIO_S0_SC[098] - No Connect + GPIO_NC, // GPIO_S0_SC[099] - No Connect + GPIO_NC, // GPIO_S0_SC[100] - No Connect + GPIO_NC, // GPIO_S0_SC[101] - No Connect + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[00] - SOC_GPIO_S5_0 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[01] - SOC_GPIO_S5_1 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[02] - SOC_GPIO_S5_2 + GPIO_FUNC6, // GPIO_S5[03] - mPCIE_WAKEB + GPIO_NC, // GPIO_S5[04] - No Connect + GPIO_INPUT, // GPIO_S5[05] - BOM_OP1 + // Memory: 0=1GB 1=2GB or 4GB + GPIO_INPUT, // GPIO_S5[06] - BOM_OP2 + GPIO_INPUT, // GPIO_S5[07] - BOM_OP3 + GPIO_OUT_HIGH_LEGACY, // GPIO_S5[08] - SOC_USB_HOST_EN0 + GPIO_OUT_HIGH_LEGACY, // GPIO_S5[09] - SOC_USB_HOST_EN1 + GPIO_OUT_HIGH_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK + GPIO_FUNC0, // GPIO_S5[11] - SUSPWRDNACK (TP14) + GPIO_FUNC0, // GPIO_S5[12] - PMC_SUSCLK0 + GPIO_FUNC1, // GPIO_S5[13] - PMC_SLP_S0IX (TP10) + GPIO_FUNC1, // GPIO_S5[14] - GPIO_S514_J20 + GPIO_FUNC0, // GPIO_S5[15] - PMC_PCIE_WAKE_R + GPIO_FUNC0, // GPIO_S5[16] - PMC_PWRBTN + GPIO_NC, // GPIO_S5[17] - No Connect + GPIO_FUNC1, // GPIO_S5[18] - LPCPD_L (TP7) + GPIO_FUNC0, // GPIO_S5[19] - SOC_USB_HOST_OC0 + GPIO_FUNC0, // GPIO_S5[20] - SOC_USB_HOST_OC1 + GPIO_FUNC0, // GPIO_S5[21] - SOC_SPI_CS1B + GPIO_INPUT_PD, // GPIO_S5[22] - NC or LED D2 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[23] - XDP_H_OBSDATA_A0 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[24] - XDP_H_OBSDATA_A1 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[25] - XDP_H_OBSDATA_A2 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[26] - XDP_H_OBSDATA_A3 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[27] - EXP_GPIO1 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[28] - EXP_GPIO2 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[29] - EXP_GPIO3 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[30] - EXP_GPIO4 + GPIO_NC, // GPIO_S5[31] - No Connect + GPIO_NC, // GPIO_S5[32] - No Connect + GPIO_NC, // GPIO_S5[33] - No Connect + GPIO_NC, // GPIO_S5[34] - No Connect + GPIO_NC, // GPIO_S5[35] - No Connect + GPIO_NC, // GPIO_S5[36] - No Connect + GPIO_NC, // GPIO_S5[37] - No Connect + GPIO_NC, // GPIO_S5[38] - No Connect + GPIO_NC, // GPIO_S5[39] - No Connect + GPIO_NC, // GPIO_S5[40] - No Connect + GPIO_NC, // GPIO_S5[41] - No Connect + GPIO_NC, // GPIO_S5[42] - No Connect + GPIO_NC, // GPIO_S5[43] - No Connect + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c new file mode 100644 index 00000000000..6fa036672e6 --- /dev/null +++ b/src/mainboard/intel/minnowmax/irqroute.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h new file mode 100644 index 00000000000..9739f6f620c --- /dev/null +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ + +/* Devices set as A, A, A, A evaluate as 0, and don't get set */ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 3), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c new file mode 100644 index 00000000000..e87b3bba78f --- /dev/null +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(struct device *dev) +{ +} + +/* + * mainboard_final is executed as one of the last items before loading the + * payload. + * + * This is the latest point to add customization. + */ +static void mainboard_final(void *chip_info) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c new file mode 100644 index 00000000000..fd82d6f21ea --- /dev/null +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +void mainboard_fill_mrc_params(struct mrc_params *mp) +{ + uint8_t *spd_file; + void *spd_content; + size_t spd_fsize; + u8 gpio34 = 0; + u8 is_1333_sku; + + /* + * The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. There's + * no good way of knowing the SKU'ing so frequency is used as a proxy. + * The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the + * E3827 and E3845 are 1750MHz and 1910MHz, respectively. + */ + is_1333_sku = !!(tsc_freq_mhz() >= 1700); + + printk(BIOS_INFO, "Using %d MHz DDR3 settings.\n", + is_1333_sku ? 1333 : 1066); + + /* + * Minnow Max Board + * Read SSUS gpio 5 (34) to determine memory type + * 0 : 1GB SKU uses 2Gb density memory + * 1 : 2GB SKU uses 4Gb density memory + * + * devicetree.cb assumes 1GB SKU board + */ + setup_ssus_gpio(34, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + + gpio34 = ssus_get_gpio(34); + if (gpio34) + printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n", + gpio34 ? "2 / 4" : "1"); + + spd_file = (uint8_t *)cbfs_map("spd.bin", &spd_fsize); + if (!spd_file) + die("SPD data not found."); + + spd_content = &spd_file[CONFIG_DIMM_SPD_SIZE * gpio34]; + + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM, + mp->txe_size_mb = 16; + + mp->mainboard.dram_data[0] = spd_content; + mp->mainboard.dram_data[1] = NULL; +} diff --git a/src/mainboard/intel/minnowmax/spd/micron_1GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/intel/minnowmax/spd/micron_1GiB_dimm_MT41K256M16HA-125.spd.hex new file mode 100644 index 00000000000..59e5c5635de --- /dev/null +++ b/src/mainboard/intel/minnowmax/spd/micron_1GiB_dimm_MT41K256M16HA-125.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 02 19 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 86 +20 08 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 aa 49 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex new file mode 100644 index 00000000000..f3bcb56245c --- /dev/null +++ b/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 04 19 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 86 +20 08 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 19 d2 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c index 25ff2d62266..2ce90088c5a 100644 --- a/src/mainboard/inventec/transformers/romstage.c +++ b/src/mainboard/inventec/transformers/romstage.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "ipmi.h" diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig index 25350426f73..b229a9fc05e 100644 --- a/src/mainboard/msi/Kconfig +++ b/src/mainboard/msi/Kconfig @@ -14,4 +14,23 @@ source "src/mainboard/msi/*/Kconfig" config MAINBOARD_VENDOR default "MSI" +config BOARD_HAS_MSI_ROMHOLE + bool + default n + +config MSI_ROMHOLE_IN_CBFS + bool "Put the MSI ROMHOLE as CBFS file" + depends on BOARD_HAS_MSI_ROMHOLE && !VBOOT + default n + +config MSI_ROMHOLE_ADDRESS_IN_CBFS + hex "MSI ROMHOLE address in CBFS" + depends on MSI_ROMHOLE_IN_CBFS + default 0xff7c0000 if BOARD_ROMSIZE_KB_32768 + +config MSI_ROMHOLE_SIZE_IN_CBFS + hex "MSI ROMHOLE size in CBFS" + depends on MSI_ROMHOLE_IN_CBFS + default 0x20000 + endif # VENDOR_MSI diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig index 1b23f0354a8..1b6e1445f11 100644 --- a/src/mainboard/msi/ms7d25/Kconfig +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -9,6 +9,7 @@ config BOARD_MSI_Z690_A_PRO_WIFI_DDR5 config BOARD_MSI_MS7D25 def_bool n select SOC_INTEL_ALDERLAKE_PCH_S + select SOC_INTEL_RAPTORLAKE select BOARD_ROMSIZE_KB_32768 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SUPERIO_NUVOTON_NCT6687D @@ -19,7 +20,7 @@ config BOARD_MSI_MS7D25 select MEMORY_MAPPED_TPM select CRB_TPM select HAVE_INTEL_PTT - select USE_LEGACY_8254_TIMER + select BOARD_HAS_MSI_ROMHOLE if BOARD_MSI_MS7D25 @@ -31,27 +32,24 @@ config MAINBOARD_PART_NUMBER default "PRO Z690-A WIFI (MS-7D25)" if BOARD_MSI_Z690_A_PRO_WIFI_DDR5 config MAINBOARD_VENDOR - string default "Micro-Star International Co., Ltd." config MAINBOARD_FAMILY - string default "Default string" config MAINBOARD_VERSION - string default "2.0" if BOARD_MSI_Z690_A_PRO_WIFI_DDR5 config UART_FOR_CONSOLE - int default 0 config USE_PM_ACPI_TIMER - bool default n +config USE_LEGACY_8254_TIMER + default y + config CBFS_SIZE - hex default 0x1000000 config TPM_PIRQ @@ -65,18 +63,35 @@ config VBOOT select VBOOT_ALWAYS_ENABLE_DISPLAY select VBOOT_NO_BOARD_SUPPORT select HAS_RECOVERY_MRC_CACHE + select VBOOT_NO_TPM + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE config VBOOT_SLOTS_RW_AB default y if VBOOT +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + config FMDFILE - string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB # gen_test_hwid.sh script doesn't like parentheses in the MAINBOARD_PART_NUMBER # Override the GBB_HWID config GBB_HWID - string default "MSI_MS7D25" +if !VBOOT && MSI_ROMHOLE_IN_CBFS + +# FIXME: Make coreboot build system automatically fixup the ucode and FIT location +# so that creating FIT does not fail. +config CPU_MICROCODE_CBFS_LOC + hex + default 0xff800000 + +config INTEL_FIT_LOC + hex + default 0xfffc0000 + +endif + endif diff --git a/src/mainboard/msi/ms7d25/Makefile.mk b/src/mainboard/msi/ms7d25/Makefile.mk index deb5ff625a6..6b9791768ac 100644 --- a/src/mainboard/msi/ms7d25/Makefile.mk +++ b/src/mainboard/msi/ms7d25/Makefile.mk @@ -1,10 +1,32 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c +$(call src-to-obj,bootblock,$(dir)/msi_id.S): $(obj)/fmap_config.h +bootblock-y += msi_id.S romstage-y += romstage_fsp_params.c ramstage-y += mainboard.c +ramstage-y += smbios.c all-y += die.c smm-y += die.c + +ifeq ($(CONFIG_MSI_ROMHOLE_IN_CBFS),y) + +$(obj)/mainboard/$(MAINBOARDDIR)/bpa.bin: + dd if=/dev/zero of=$@ bs=64K count=1 + +cbfs-files-y += bpa.bin + +bpa.bin-file := $(obj)/mainboard/$(MAINBOARDDIR)/bpa.bin +bpa.bin-type := raw +bpa.bin-compression := none +bpa.bin-position := 0xff080000 # Fixed position from original MSI firmware + +# Workaround: place build_info exactly at the EXT_BIOS_WINDOW boundary (plus +# the metadata size) to avoid files getting fragmented between +# FIXED_BIOS_WINDOW and EXT_BIOS_WINDOW. +build_info-COREBOOT-position := 0xff000040 + +endif diff --git a/src/mainboard/msi/ms7d25/acpi/mainboard.asl b/src/mainboard/msi/ms7d25/acpi/mainboard.asl new file mode 100644 index 00000000000..dd64d794bc5 --- /dev/null +++ b/src/mainboard/msi/ms7d25/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Scope (_GPE) { + /* Empty PCI_EXP_STS handler */ + Method (_L69, 0, Serialized) { } +} + +Scope (\_SB.PCI0) { + /* This device triggers automatic drivers and MSI utilities installation on Windows */ + Device (MSIV) { + Name (_HID, "MBID0001") + Name (_UID, One) + Method (_STA, 0, NotSerialized){ + Return (One) + } + } +} diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c index 110d6828a61..1b192eb8d10 100644 --- a/src/mainboard/msi/ms7d25/bootblock.c +++ b/src/mainboard/msi/ms7d25/bootblock.c @@ -4,42 +4,75 @@ #include #include #include +#include +#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7) #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) +#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART) +#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC) + +#define EC_IO_BASE 0xa20 void bootblock_mainboard_early_init(void) { /* Replicate vendor settings for multi-function pins in global config LDN */ - nuvoton_pnp_enter_conf_state(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low - pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + nuvoton_pnp_enter_conf_state(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low + pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low /* Below are multi-pin function */ - pnp_write_config(SERIAL_DEV, 0x15, 0xaa); - pnp_write_config(SERIAL_DEV, 0x1a, 0x02); - pnp_write_config(SERIAL_DEV, 0x1b, 0x02); - pnp_write_config(SERIAL_DEV, 0x1d, 0x00); - pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); - pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); - pnp_write_config(SERIAL_DEV, 0x22, 0xbd); - pnp_write_config(SERIAL_DEV, 0x23, 0xdf); - pnp_write_config(SERIAL_DEV, 0x24, 0x39); - pnp_write_config(SERIAL_DEV, 0x25, 0xfe); - pnp_write_config(SERIAL_DEV, 0x26, 0x40); - pnp_write_config(SERIAL_DEV, 0x27, 0x77); - pnp_write_config(SERIAL_DEV, 0x28, 0x00); - pnp_write_config(SERIAL_DEV, 0x29, 0xfb); - pnp_write_config(SERIAL_DEV, 0x2a, 0x80); - pnp_write_config(SERIAL_DEV, 0x2b, 0x20); - pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); - pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); + pnp_write_config(GPIO_DEV, 0x15, 0xaa); + pnp_write_config(GPIO_DEV, 0x1a, 0x02); + pnp_write_config(GPIO_DEV, 0x1b, 0x02); + pnp_write_config(GPIO_DEV, 0x1d, 0x00); + pnp_write_config(GPIO_DEV, 0x1e, 0xaa); + pnp_write_config(GPIO_DEV, 0x1f, 0xb2); + pnp_write_config(GPIO_DEV, 0x22, 0xbd); + pnp_write_config(GPIO_DEV, 0x23, 0xdf); + pnp_write_config(GPIO_DEV, 0x24, 0x39); + pnp_write_config(GPIO_DEV, 0x25, 0xfe); + pnp_write_config(GPIO_DEV, 0x26, 0x40); + pnp_write_config(GPIO_DEV, 0x27, 0x77); + pnp_write_config(GPIO_DEV, 0x28, 0x00); + pnp_write_config(GPIO_DEV, 0x29, 0xfb); + pnp_write_config(GPIO_DEV, 0x2a, 0x80); + pnp_write_config(GPIO_DEV, 0x2b, 0x20); + pnp_write_config(GPIO_DEV, 0x2c, 0x8a); + pnp_write_config(GPIO_DEV, 0x2d, 0xaa); + + /* Set GPIO 06 as high output */ + pnp_write_config(GPIO_DEV, 0xF0, 0x00); + pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40); + pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00); pnp_set_logical_device(POWER_DEV); /* Configure pin for PECI */ pnp_write_config(POWER_DEV, 0xf3, 0x80); - nuvoton_pnp_exit_conf_state(POWER_DEV); + /* Configure power fault detection */ + pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30); + pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01); + + /* Configure yellow and green LED */ + pnp_write_config(POWER_DEV, 0xe7, 0x88); + pnp_write_config(POWER_DEV, 0xe8, 0x07); + pnp_set_logical_device(P80_UART_DEV); + pnp_write_config(P80_UART_DEV, 0xe5, 0x0f); + + /* Configure EC */ + pnp_set_logical_device(EC_DEV); + pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE); + pnp_set_enable(EC_DEV, 1); + + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0); + nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03); + nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04); + + nuvoton_pnp_exit_conf_state(EC_DEV); if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms7d25/data.vbt b/src/mainboard/msi/ms7d25/data.vbt index b9085691568..ee8e76953dd 100644 Binary files a/src/mainboard/msi/ms7d25/data.vbt and b/src/mainboard/msi/ms7d25/data.vbt differ diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 73d871d3462..8d87ccafce7 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -2,6 +2,7 @@ chip soc/intel/alderlake # FSP configuration register "eist_enable" = "true" + register "enable_hwp_scalability_tracking" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" @@ -12,76 +13,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_VPGIO" register "pmc_gpe0_dw2" = "GPD" - # USB Configuration - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 - register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5 - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0 - register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty? - register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4 - register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4 - register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3 - register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3 - register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 - register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 - register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers - register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT - register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 - register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 - register "usb3_ports[9]" = "USB3_PORT_EMPTY" - - # LPC generic I/O ranges - register "gen1_dec" = "0x00fc0201" - register "gen2_dec" = "0x003c0a01" - register "gen3_dec" = "0x000c03f1" - register "gen4_dec" = "0x000c0081" - - register "sata_salp_support" = "1" - - register "sata_ports_enable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" - - register "sata_ports_dev_slp" = "{ - [0] = 0, - [1] = 0, - [2] = 0, - [3] = 0, - [4] = 0, - [5] = 0, - [6] = 1, - [7] = 1, - }" - - # HDMI on port B - register "ddi_portB_config" = "1" - register "ddi_ports_config" = "{ - [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_2] = DDI_ENABLE_HPD, - [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_4] = DDI_ENABLE_HPD, - }" - register "hybrid_storage_mode" = "true" register "dmi_power_optimize_disable" = "true" @@ -104,7 +35,18 @@ chip soc/intel/alderlake "PCI_E1" "SlotDataBusWidth16X" end device ref pcie5_1 off end - device ref igpu on end + device ref igpu on + # HDMI on port B + register "ddi_portB_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_2] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_4] = DDI_ENABLE_HPD, + }" + end device ref pcie4_0 on register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 9, @@ -114,8 +56,35 @@ chip soc/intel/alderlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end - device ref crashlog off end - device ref xhci on end + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # USB-C LAN_USB1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # MSI MYSTIC LIGHT + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # USB-A LAN_USB1 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # JUSB5 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # HUB to rear USB 2.0 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" # JUSB4 + register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" # JUSB4 + register "usb2_ports[8]" = "USB2_PORT_LONG(OC4)" # JUSB3 + register "usb2_ports[9]" = "USB2_PORT_LONG(OC4)" # JUSB3 + register "usb2_ports[10]" = "USB2_PORT_LONG(OC5)" # PS2_USB1 + register "usb2_ports[11]" = "USB2_PORT_LONG(OC5)" # PS2_USB1 + register "usb2_ports[12]" = "USB2_PORT_MID(OC6)" # HUB to USB 2.0 headers + register "usb2_ports[13]" = "USB2_PORT_LONG(OC6)" # CNVi BT + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB-C Gen2x2 LAN_USB1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB-C Gen2x2 LAN_USB1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB-A LAN_USB1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # JUSB5 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # USB-A USB2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # USB-A USB2 + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC3)" # JUSB4 + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC3)" # JUSB4 + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC4)" # JUSB3 + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC4)" # JUSB3 + end device ref cnvi_wifi on # Enable CNVi BT register "cnvi_bt_core" = "true" @@ -127,12 +96,42 @@ chip soc/intel/alderlake end end device ref heci1 on end - device ref heci2 off end - device ref ide_r off end - device ref kt off end - device ref heci3 off end - device ref heci4 off end - device ref sata on end + device ref sata on + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + + register "sata_ports_dev_slp" = "{ + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0, + [4] = 0, + [5] = 0, + [6] = 1, + [7] = 1, + }" + + register "sata_ports_hotplug" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref pcie_rp1 on register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 10, @@ -158,7 +157,6 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, }" end - device ref pcie_rp4 off end device ref pcie_rp5 on register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -212,7 +210,170 @@ chip soc/intel/alderlake "M2_2" "SlotDataBusWidth4X" end device ref pch_espi on + # LPC generic I/O ranges + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c03f1" + register "gen4_dec" = "0x000c0081" + chip superio/nuvoton/nct6687d + register "sensors[0]" = "PECI_AGENT0_DOMAIN0" + register "sensors[1]" = "TD0P_CURRENT_MODE" + register "sensors[2]" = "THERMISTOR15" + register "sensors[3]" = "PCH_CHIP" + register "sensors[4]" = "THERMISTOR16" + register "sensors[5]" = "THERMISTOR0" + register "sensors[6]" = "THERMISTOR1" + register "sensors[16]" = "VIN0" + register "sensors[17]" = "VIN1" + register "sensors[18]" = "VIN2" + register "sensors[19]" = "VIN3" + register "sensors[20]" = "VIN4" + register "sensors[21]" = "VIN5" + register "sensors[22]" = "VIN6" + register "sensors[23]" = "VIN7" + register "sensors[24]" = "VCC" + + register "smbus_sensor.sensor_idx" = "3" + register "smbus_sensor.sensor_en" = "true" + register "smbus_sensor.sensor_cmd" = "0x40" + register "smbus_sensor.sensor_addr" = "0x96" + register "smbus_sensor.baud_rate" = "BAUD_100K" + register "smbus_sensor.report_one_byte" = "true" + register "smbus_sensor.port_sel" = "1" + + register "peci_speed" = "PECI_1200KHZ" + + register "fan_default_val" = "60" + + register "smart_tracking.speed_boundary_low" = "1500" + register "smart_tracking.speed_boundary_high" = "2500" + register "smart_tracking.rpm_tolerance_low" = "100" + register "smart_tracking.rpm_tolerance_mid" = "100" + register "smart_tracking.rpm_tolerance_high" = "100" + register "smart_tracking.step_up" = "1" + register "smart_tracking.step_down" = "1" + + # CPU_FAN + register "FAN1.mode" = "FAN_SMART_FAN_IV" + register "FAN1.unit_sel" = "FAN_PWM" + register "FAN1.fanin_sel" = "TACH_PWM1" + register "FAN1.fanout_sel" = "TACH_PWM0" + register "FAN1.fan_alg_weight" = "10" + register "FAN1.smart_tracking_en" = "true" + register "FAN1.crit_temp" = "101" + register "FAN1.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN1.smart_fan.temp_levels" = "{ 40, 55, 70, 85, 90, 95, 100 }" + register "FAN1.smart_fan.speed_levels" = "{ 13, 38, 63, 85, 90, 95, 100 }" + register "FAN1.smart_fan.cut_off_delay" = "5" + register "FAN1.smart_fan.step_up_time" = "1" + register "FAN1.smart_fan.step_down_time" = "1" + + # PUMP_FAN + register "FAN2.mode" = "FAN_SMART_FAN_IV" + register "FAN2.unit_sel" = "FAN_PWM" + register "FAN2.fanin_sel" = "TACH_PWM3" + register "FAN2.fanout_sel" = "TACH_PWM2" + register "FAN2.fan_alg_weight" = "10" + register "FAN2.smart_tracking_en" = "true" + register "FAN2.crit_temp" = "101" + register "FAN2.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN2.smart_fan.temp_levels" = "{ 32, 32, 32, 32, 32, 32, 32 }" + register "FAN2.smart_fan.speed_levels" = "{ 100, 100, 100, 100, 100, 100, 100 }" + register "FAN2.smart_fan.cut_off_delay" = "5" + register "FAN2.smart_fan.step_up_time" = "1" + register "FAN2.smart_fan.step_down_time" = "1" + + # SYS_FAN1 + register "FAN3.mode" = "FAN_SMART_FAN_IV" + register "FAN3.unit_sel" = "FAN_PWM" + register "FAN3.fanin_sel" = "TACH_PWM11" + register "FAN3.fanout_sel" = "TACH_PWM10" + register "FAN3.fan_alg_weight" = "10" + register "FAN3.smart_tracking_en" = "true" + register "FAN3.crit_temp" = "101" + register "FAN3.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN3.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN3.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN3.smart_fan.cut_off_delay" = "5" + register "FAN3.smart_fan.step_up_time" = "1" + register "FAN3.smart_fan.step_down_time" = "1" + + # SYS_FAN2 + register "FAN4.mode" = "FAN_SMART_FAN_IV" + register "FAN4.unit_sel" = "FAN_PWM" + register "FAN4.fanin_sel" = "TACH_PWM13" + register "FAN4.fanout_sel" = "TACH_PWM12" + register "FAN4.fan_alg_weight" = "10" + register "FAN4.smart_tracking_en" = "true" + register "FAN4.crit_temp" = "101" + register "FAN4.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN4.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN4.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN4.smart_fan.cut_off_delay" = "5" + register "FAN4.smart_fan.step_up_time" = "1" + register "FAN4.smart_fan.step_down_time" = "1" + + # SYS_FAN3 + register "FAN5.mode" = "FAN_SMART_FAN_IV" + register "FAN5.unit_sel" = "FAN_PWM" + register "FAN5.fanin_sel" = "TACH_PWM15" + register "FAN5.fanout_sel" = "TACH_PWM14" + register "FAN5.fan_alg_weight" = "10" + register "FAN5.smart_tracking_en" = "true" + register "FAN5.crit_temp" = "101" + register "FAN5.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN5.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN5.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN5.smart_fan.cut_off_delay" = "5" + register "FAN5.smart_fan.step_up_time" = "1" + register "FAN5.smart_fan.step_down_time" = "1" + + # SYS_FAN4 + register "FAN6.mode" = "FAN_SMART_FAN_IV" + register "FAN6.unit_sel" = "FAN_PWM" + register "FAN6.fanin_sel" = "TACH_PWM17" + register "FAN6.fanout_sel" = "TACH_PWM16" + register "FAN6.fan_alg_weight" = "10" + register "FAN6.smart_tracking_en" = "true" + register "FAN6.crit_temp" = "101" + register "FAN6.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN6.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN6.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN6.smart_fan.cut_off_delay" = "5" + register "FAN6.smart_fan.step_up_time" = "1" + register "FAN6.smart_fan.step_down_time" = "1" + + # SYS_FAN5 + register "FAN7.mode" = "FAN_SMART_FAN_IV" + register "FAN7.unit_sel" = "FAN_PWM" + register "FAN7.fanin_sel" = "TACH_PWM19" + register "FAN7.fanout_sel" = "TACH_PWM18" + register "FAN7.fan_alg_weight" = "10" + register "FAN7.smart_tracking_en" = "true" + register "FAN7.crit_temp" = "101" + register "FAN7.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN7.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN7.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN7.smart_fan.cut_off_delay" = "5" + register "FAN7.smart_fan.step_up_time" = "1" + register "FAN7.smart_fan.step_down_time" = "1" + + # SYS_FAN6 + register "FAN8.mode" = "FAN_SMART_FAN_IV" + register "FAN8.unit_sel" = "FAN_PWM" + register "FAN8.fanin_sel" = "TACH_PWM6" + register "FAN8.fanout_sel" = "TACH_PWM4" + register "FAN8.fan_alg_weight" = "10" + register "FAN8.smart_tracking_en" = "true" + register "FAN8.crit_temp" = "101" + register "FAN8.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN8.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN8.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN8.smart_fan.cut_off_delay" = "5" + register "FAN8.smart_fan.step_up_time" = "1" + register "FAN8.smart_fan.step_down_time" = "1" + device pnp 4e.1 off end # Parallel port device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 @@ -245,7 +406,7 @@ chip soc/intel/alderlake device pnp 0.0 on end # TPM end end - device ref p2sb on end + device ref p2sb hidden end device ref hda on subsystemid 0x1462 0x9d25 register "pch_hda_audio_link_hda_enable" = "1" diff --git a/src/mainboard/msi/ms7d25/dsdt.asl b/src/mainboard/msi/ms7d25/dsdt.asl index 8e512dbc853..11fd5e65280 100644 --- a/src/mainboard/msi/ms7d25/dsdt.asl +++ b/src/mainboard/msi/ms7d25/dsdt.asl @@ -26,5 +26,7 @@ DefinitionBlock( #include "acpi/superio.asl" } + #include "acpi/mainboard.asl" + #include } diff --git a/src/mainboard/msi/ms7d25/hda_verb.c b/src/mainboard/msi/ms7d25/hda_verb.c index 3906a84eb57..c7c06c49372 100644 --- a/src/mainboard/msi/ms7d25/hda_verb.c +++ b/src/mainboard/msi/ms7d25/hda_verb.c @@ -6,7 +6,8 @@ const u32 cim_verb_data[] = { /* Realtek ALC897 */ 0x10ec0897, /* Vendor ID */ 0x14629d25, /* Subsystem ID */ - 15, /* Number of entries */ + 28, /* Number of entries */ + AZALIA_RESET(0x1), AZALIA_SUBVENDOR(0, 0x14629d25), AZALIA_PIN_CFG(0, 0x11, 0x4037d540), AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), @@ -23,12 +24,83 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + 0x0205003B, + 0x02040080, + 0x02050039, + 0x02044031, + + 0x02050013, + 0x02040053, + 0x02050030, + 0x020492D1, + + 0x02050021, + 0x02040000, + 0x02050023, + 0x02040000, + + 0x02050025, + 0x02040000, + 0x02050027, + 0x02040000, + + 0x02050029, + 0x02040000, + 0x0205002A, + 0x02041640, + + 0x0205002B, + 0x02041640, + 0x02050021, + 0x02040C00, + + 0x02050023, + 0x02040C00, + 0x02050025, + 0x02040C00, + + 0x02050027, + 0x02040C00, + 0x02050029, + 0x02040C00, + + 0x0205002A, + 0x02041641, + 0x0205002B, + 0x02041641, + + 0x02050030, + 0x02049251, + 0x0205002A, + 0x02041649, + + 0x0205002B, + 0x02041649, + 0x0205000C, + 0x02043F06, + + 0x02050007, + 0x0204F808, + 0x02050007, + 0x0204F808, + /* Alderlake HDMI */ 0x80862815, /* Vendor ID */ 0x80860101, /* Subsystem ID */ - 2, /* Number of entries */ + 7, /* Number of entries */ AZALIA_SUBVENDOR(2, 0x80860101), - AZALIA_PIN_CFG(2, 0x04, 0x18560010), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 }; diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index b346ac7df06..527e0865bce 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -1,12 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include -#include #include #include #include #include +#include + +#define MSR_ATOM_TURBO_RATIO_LIMIT 0x650 +#define MSR_ATOM_TURBO_RATIO_LIMIT_CORES 0x651 +#define MSR_BIGCORE_TURBO_RATIO_LIMIT 0x1ad +#define MSR_BIGCORE_TURBO_RATIO_LIMIT_CORES 0x1ae + void mainboard_fill_fadt(acpi_fadt_t *fadt) { @@ -14,53 +22,35 @@ void mainboard_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch |= ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; } -static void mainboard_init(void *chip_info) -{ -} - -u8 smbios_mainboard_feature_flags(void) -{ - return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; -} -smbios_wakeup_type smbios_system_wakeup_type(void) +static void mainboard_init(void *chip_info) { - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} + struct device *ps2_dev = dev_find_slot_pnp(0x4e, NCT6687D_KBC); + bool ps2_en = get_ps2_option(); -const char *smbios_system_product_name(void) -{ - return "MS-7D25"; + ps2_dev->enabled = ps2_en & 1; + printk(BIOS_DEBUG, "PS2 Controller state: %d\n", ps2_en); } -const char *smbios_mainboard_product_name(void) +static void fill_turbo_ratio_limits(FSP_S_CONFIG *params) { - if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) { - if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) - return "PRO Z690-A WIFI DDR4(MS-7D25)"; - else - return "PRO Z690-A DDR4(MS-7D25)"; - } + msr_t msr; - if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5)) { - if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) - return "PRO Z690-A WIFI (MS-7D25)"; - else - return "PRO Z690-A (MS-7D25)"; - } + msr = rdmsr(MSR_BIGCORE_TURBO_RATIO_LIMIT); + memcpy(¶ms->TurboRatioLimitRatio[0], &msr.lo, 4); + memcpy(¶ms->TurboRatioLimitRatio[4], &msr.hi, 4); - return mainboard_part_number; -} + msr = rdmsr(MSR_BIGCORE_TURBO_RATIO_LIMIT_CORES); + memcpy(¶ms->TurboRatioLimitNumCore[0], &msr.lo, 4); + memcpy(¶ms->TurboRatioLimitNumCore[4], &msr.hi, 4); -/* Only baseboard serial number is populated */ -const char *smbios_system_serial_number(void) -{ - return "Default string"; -} + msr = rdmsr(MSR_ATOM_TURBO_RATIO_LIMIT); + memcpy(¶ms->AtomTurboRatioLimitRatio[0], &msr.lo, 4); + memcpy(¶ms->AtomTurboRatioLimitRatio[4], &msr.hi, 4); -const char *smbios_system_sku(void) -{ - return "Default string"; + msr = rdmsr(MSR_ATOM_TURBO_RATIO_LIMIT_CORES); + memcpy(¶ms->AtomTurboRatioLimitNumCore[0], &msr.lo, 4); + memcpy(¶ms->AtomTurboRatioLimitNumCore[4], &msr.hi, 4); } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -86,24 +76,21 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating)); params->UsbPdoProgramming = 1; - params->CpuPcieFiaProgramming = 1; - params->PcieRpFunctionSwap = 0; params->CpuPcieRpFunctionSwap = 0; - params->PchLegacyIoLowLatency = 1; params->PchDmiAspmCtrl = 0; - params->CpuPcieRpPmSci[0] = 1; // M2_1 - params->CpuPcieRpPmSci[1] = 1; // PCI_E1 - params->PcieRpPmSci[0] = 1; // PCI_E2 - params->PcieRpPmSci[1] = 1; // PCI_E4 - params->PcieRpPmSci[2] = 1; // Ethernet - params->PcieRpPmSci[4] = 1; // PCI_E3 - params->PcieRpPmSci[8] = 1; // M2_3 - params->PcieRpPmSci[20] = 1; // M2_4 - params->PcieRpPmSci[24] = 1; // M2_2 + params->CpuPcieRpPmSci[0] = 0; // M2_1 + params->CpuPcieRpPmSci[1] = 0; // PCI_E1 + params->PcieRpPmSci[0] = 0; // PCI_E2 + params->PcieRpPmSci[1] = 0; // PCI_E4 + params->PcieRpPmSci[2] = 0; // Ethernet + params->PcieRpPmSci[4] = 0; // PCI_E3 + params->PcieRpPmSci[8] = 0; // M2_3 + params->PcieRpPmSci[20] = 0; // M2_4 + params->PcieRpPmSci[24] = 0; // M2_2 params->PcieRpMaxPayload[0] = 1; // PCI_E2 params->PcieRpMaxPayload[1] = 1; // PCI_E4 @@ -174,6 +161,12 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->SataPortsSolidStateDrive[6] = 1; // M2_3 params->SataPortsSolidStateDrive[7] = 1; // M2_4 params->SataLedEnable = 1; + + /* + * If OcLock is not set in FSP-M UPD, FSP-S UPD will take and program + * zeroed turbo ratio limits. Avoid this by populating defautl values here. + */ + fill_turbo_ratio_limits(params); } #if CONFIG(GENERATE_SMBIOS_TABLES) @@ -531,7 +524,12 @@ static void mainboard_enable(struct device *dev) #endif } +static void mainboard_final(void *chip_info) +{ +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, + .final = mainboard_final, }; diff --git a/src/mainboard/msi/ms7d25/msi_id.S b/src/mainboard/msi/ms7d25/msi_id.S new file mode 100644 index 00000000000..8be2e971651 --- /dev/null +++ b/src/mainboard/msi/ms7d25/msi_id.S @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +.section .init, "a", @progbits + +/* The following structures must reside in the last 64KiB of flash */ + +.align 16 + +build_date: + .ascii "$MSESGN$" + .ascii "E7D25IMS." +#if CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5) + .byte 'A' +#endif +#if CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4) + .byte '1' +#endif + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte ' ' + .asciz COREBOOT_DMI_DATE + +.align 8 + +msi_sign_on: + .ascii "$MS1E7D25IMS" +#if CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5) + .byte 'A' +#endif +#if CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4) + .byte '1' +#endif + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte 2 + +.align 8 + +bpa: + .ascii "$BPA" + .byte bpa_end - bpa + .byte 1 + .long 0x1000 + .long 6 + .byte 2 + .long 0x17c0000 + .long 0x20000 + .byte 3 + .long 0x1080000 + .long 64 + .byte 4 + .long 2 +bpa_end: + .byte 0, 0, 0, 0, 0 + + .asciz "@FC@" + .byte 2 + .byte 0 + .byte '1' + .asciz "/P /B /N" + .byte '2' + .byte 0 + .ascii "NULL" + .ascii "@@" + .fill 10, 1, 0 diff --git a/src/mainboard/msi/ms7d25/romhole.h b/src/mainboard/msi/ms7d25/romhole.h new file mode 100644 index 00000000000..f9ae37de919 --- /dev/null +++ b/src/mainboard/msi/ms7d25/romhole.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ROMHOLE_H_ +#define _ROMHOLE_H_ + +#define ROMHOLE_MAGIC 0x10012501 +#define NUM_PWD_ENTRIES 2 +#define PWD_SIZE 40 +#define NUM_GD_ENTRIES 8 +#define GD_SIZE 48 +#define NUM_US_ENTRIES 8 +#define US_SIZE 0x3851 +#define TYPE2_SIZE 256 +#define FTB_SIZE 105 +#define FIB_SIZE 512 +#define FDP_SIZE 1024 +#define BUV_SIZE 1024 +#define NUM_VOLUMES 7 + +struct uuid_structure { + uint8_t magic0[4]; // always sSiD + uint16_t length; // structure length, always 0x1a + uint8_t magic1[3]; // awlays $uD + uint8_t space; // always 0x1 + uint8_t uuid[16]; // SMBIOS type 1 UUID +} __packed; + +struct pwd_entry { + uint8_t magic[3]; // always $s$ + uint8_t number; // ordinal number + uint8_t length; // length of pwd + uint8_t pwd[PWD_SIZE]; // password? +} __packed; + +struct pwd_structure { + uint8_t magic[4]; // always spWd + uint16_t length; // structure length + struct pwd_entry entries[NUM_PWD_ENTRIES]; +} __packed; + +struct gd_entry { + uint8_t magic[3]; // always $gD + uint8_t number; // ordinal number + uint16_t length; // length of gd + uint8_t gd[GD_SIZE]; // global data? +} __packed; + +struct gpdt_structure { + uint8_t magic[4]; // always gPdT + uint16_t length; // structure length + uint8_t num_entries; // number of entries + uint8_t space; // awlays zero + struct gd_entry entries[NUM_GD_ENTRIES]; +} __packed; + +struct us_entry { + uint8_t magic[3]; // always $uS + uint8_t number; // ordinal number + uint16_t length; // length of us + uint8_t us[US_SIZE]; // user data? +} __packed; + +struct ucsc_structure { + uint8_t magic[4]; // always uCsC + uint16_t length; // structure length + struct us_entry entries[NUM_US_ENTRIES]; +} __packed; + +struct type2_rw { + uint8_t magic0[4]; // always t2Rw + uint16_t length; // structure length + uint8_t magic1[3]; // always $tW + uint8_t space; // always 0x1 + uint8_t smbios_type2[TYPE2_SIZE]; // SMBIOS type2 table +} __packed; + +struct ftb_structure { + uint8_t magic0[4]; // always $FTB + uint16_t length; // structure length + uint8_t magic1[4]; // always $DIB + uint16_t space0; // always 0x2 + uint16_t size; // size of data field, always 105 + uint16_t space1; // always 0x0 + uint8_t magic2[4]; // always MFTD + uint8_t data[FTB_SIZE]; // default 0xfe +} __packed; + +struct fib_structure { + uint8_t magic0[4]; // always $FIB + uint16_t length; // structure length + uint16_t size; // size of data field, always 512 + uint8_t magic1[4]; // always $MFX + uint8_t data[FIB_SIZE]; // default 0xfa +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P since A.40/1.40 */ +struct fdp_structure { + uint8_t magic0[4]; // always $FDP + uint16_t length; // structure length + uint8_t magic1[3]; // always $Fd + uint8_t number; // always 0x1 + uint8_t data[FDP_SIZE]; // default 0xff +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P A.40/1.40 */ +struct buv_structure { + uint8_t magic0[4]; // always $BuV + uint16_t length; // structure length + uint8_t magic1[3]; // always $Bv + uint8_t number; // always 0x1 + uint8_t data[BUV_SIZE]; // default 0xff +} __packed; + +struct volume_entry { + uint8_t number; // ordinal number in ascii + uint32_t address; // volume base address + uint32_t size; // volume size + uint8_t space; // always 0xff +} __packed; + +struct ris_structure { + uint8_t magic0[4]; // always $RiS + uint16_t length; // structure length + uint8_t magic1[4]; // always $RiT + /* Array below keep the addresses and sizes of UEFI Firmware Volumes */ + struct volume_entry volumes[NUM_VOLUMES]; +} __packed; + +/* Place the following struct in the ROMHOLE flash region with 64K/128K alignment */ +struct msi_romhole { + uint32_t magic0; // 0x10012501 + uint16_t length; // length of the structure + char magic1[4]; // always SYSD + uint32_t address; // romhole address in flash + uint32_t size; // romhole total size + uint8_t pad0[48]; // always 0xff + struct uuid_structure uuid; + struct pwd_structure pwd; + struct gpdt_structure gpdt; + struct ucsc_structure ucsc; + struct type2_rw t2rw; + struct ftb_structure ftb; + struct fib_structure fib; + struct fdp_structure fdp; + struct buv_structure buv; + struct ris_structure ris; + // the rest is padded with 0xff by cbfstool +} __packed; + +#endif diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 1494deec8ba..f152de76b5f 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -80,8 +81,15 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.DmiAspmCtrl = 0; memupd->FspmConfig.SkipExtGfxScan = 0; + memupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; memupd->FspmConfig.PchHdaSdiEnable[0] = 1; + memupd->FspmConfig.MmioSize = 0xb00; /* 2.75GB in MB */ + + memupd->FspmConfig.OcLock = 0; + + memupd->FspmConfig.SpdProfileSelected = dasharo_get_memory_profile(); + if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5)) diff --git a/src/mainboard/msi/ms7d25/smbios.c b/src/mainboard/msi/ms7d25/smbios.c new file mode 100644 index 00000000000..6a543521963 --- /dev/null +++ b/src/mainboard/msi/ms7d25/smbios.c @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "romhole.h" + +struct smbios_type2_v3_4 { + struct smbios_header header; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 asset_tag; + u8 feature_flags; + u8 location_in_chassis; + u16 chassis_handle; + u8 board_type; + u8 contained_objects; + u8 eos[2]; +} __packed; + +static struct msi_romhole *romhole_addr = NULL; + +static struct msi_romhole *get_msi_romhole_address(void) +{ + struct region_device rdev; + + if (romhole_addr) + return romhole_addr; + + if (fmap_locate_area_as_rdev("ROMHOLE", &rdev)) + return NULL; + + romhole_addr = (struct msi_romhole *)rdev_mmap_full(&rdev); + + return romhole_addr; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +const char *smbios_system_product_name(void) +{ + return "MS-7D25"; +} +const char *smbios_mainboard_product_name(void) +{ + if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) { + if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) + return "PRO Z690-A WIFI DDR4(MS-7D25)"; + else + return "PRO Z690-A DDR4(MS-7D25)"; + } + + if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5)) { + if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) + return "PRO Z690-A WIFI (MS-7D25)"; + else + return "PRO Z690-A (MS-7D25)"; + } + + return CONFIG_MAINBOARD_PART_NUMBER; +} + +/* Only baseboard serial number is populated */ +const char *smbios_system_serial_number(void) +{ + return "Default string"; +} + +const char *smbios_system_sku(void) +{ + return "Default string"; +} + +void smbios_system_set_uuid(u8 *uuid) +{ + if (!get_msi_romhole_address()) + return; + + memcpy(uuid, romhole_addr->uuid.uuid, 16); +} + +static const char* get_smbios_string(u8 *str_table_start, u8 string_index, + const char *fallback) +{ + u8 i; + char *smbios_str = (char *)str_table_start; + + for (i = 1; i < string_index; i++) { + if (strlen(smbios_str)) + smbios_str += strlen(smbios_str) + 1; + else + return fallback; + } + + return strlen(smbios_str) ? (const char *)smbios_str : fallback; +} + +const char *smbios_mainboard_serial_number(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + return get_smbios_string(type2->eos, type2->serial_number, + CONFIG_MAINBOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_VERSION; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_VERSION; + + return get_smbios_string(type2->eos, type2->version, + CONFIG_MAINBOARD_VERSION); +} diff --git a/src/mainboard/msi/ms7d25/smihandler.c b/src/mainboard/msi/ms7d25/smihandler.c new file mode 100644 index 00000000000..3978d4fcef1 --- /dev/null +++ b/src/mainboard/msi/ms7d25/smihandler.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) +#define ACPI_DEV PNP_DEV(0x4e, NCT6687D_ACPI) + +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +static void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +static void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void disable_ps2_wake(void) +{ + uint8_t reg; + + pnp_set_logical_device(ACPI_DEV); + reg = pnp_read_config(ACPI_DEV, 0xe4); + reg &= ~0xc0; /* Disable keyboard and mouse wake via PSOUT# */ + reg &= ~0x08; /* Disable keyboard wake with any key */ + pnp_write_config(ACPI_DEV, 0xe4, reg); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + nuvoton_pnp_enter_conf_state(POWER_DEV); + pnp_set_logical_device(POWER_DEV); + + switch (slp_typ) { + case 3: + pnp_write_config(POWER_DEV, 0xe7, 0x20); /* Keep LED freq at S3-S5 */ + pnp_write_config(POWER_DEV, 0xe8, 0x05); /* Blink LED at 1Hz */ + break; + case 4: + pnp_write_config(POWER_DEV, 0xe7, 0x88); /* Set AUTO_EN */ + pnp_write_config(POWER_DEV, 0xe8, 0x07); /* LED to low */ + break; + case 5: + pnp_write_config(POWER_DEV, 0xe7, 0x88); /* Set AUTO_EN */ + pnp_write_config(POWER_DEV, 0xe8, 0x07); /* LED to low */ + disable_ps2_wake(); + break; + } + + nuvoton_pnp_exit_conf_state(POWER_DEV); +} diff --git a/src/mainboard/msi/ms7d25/vboot-rwab.fmd b/src/mainboard/msi/ms7d25/vboot-rwab.fmd index 665c8949bbe..7569cda7cc4 100644 --- a/src/mainboard/msi/ms7d25/vboot-rwab.fmd +++ b/src/mainboard/msi/ms7d25/vboot-rwab.fmd @@ -6,6 +6,10 @@ FLASH 32M { UNUSED 12M + SMMSTORE(PRESERVE) 256K + RESERVED(PRESERVE) 256K + BPA(PRESERVE) 128K + RW_MISC 320K { UNIFIED_MRC_CACHE(PRESERVE) { RECOVERY_MRC_CACHE 128K @@ -21,22 +25,25 @@ FLASH 32M { } CONSOLE 128K - SMMSTORE(PRESERVE) 256K HSPHY_FW(PRESERVE) 32K + BOOTSPLASH(CBFS) 2M - RW_SECTION_A 5264K { + RW_SECTION_A 4768K { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 0x100 } - RW_SECTION_B 5264K { + # ROMHOLE must be at flash offset 0x17c0000 + ROMHOLE(PRESERVE) 128K + + RW_SECTION_B 4224K { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 0x100 } - WP_RO 5M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K diff --git a/src/mainboard/msi/ms7e06/Kconfig b/src/mainboard/msi/ms7e06/Kconfig index b0ba2163568..727e41e472a 100644 --- a/src/mainboard/msi/ms7e06/Kconfig +++ b/src/mainboard/msi/ms7e06/Kconfig @@ -3,7 +3,7 @@ config BOARD_MSI_Z790_P_PRO_WIFI_DDR4 select BOARD_MSI_MS7E06 -config BOARD_MSI_Z790_P_PRO_WIFI +config BOARD_MSI_Z790_P_PRO_WIFI_DDR5 select BOARD_MSI_MS7E06 config BOARD_MSI_MS7E06 @@ -19,6 +19,7 @@ config BOARD_MSI_MS7E06 select MEMORY_MAPPED_TPM select CRB_TPM select HAVE_INTEL_PTT + select BOARD_HAS_MSI_ROMHOLE if BOARD_MSI_MS7E06 @@ -26,8 +27,8 @@ config MAINBOARD_DIR default "msi/ms7e06" config MAINBOARD_PART_NUMBER - default "PRO Z790-P WIFI DDR4(MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI_DDR4 - default "PRO Z790-P WIFI (MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI + default "PRO Z790-P WIFI DDR4 (MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI_DDR4 + default "PRO Z790-P WIFI (MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI_DDR5 config MAINBOARD_VENDOR default "Micro-Star International Co., Ltd." @@ -35,6 +36,9 @@ config MAINBOARD_VENDOR config MAINBOARD_FAMILY default "Default string" +config MAINBOARD_VERSION + default "2.0" if BOARD_MSI_Z790_P_PRO_WIFI_DDR5 + config UART_FOR_CONSOLE default 0 @@ -58,6 +62,8 @@ config VBOOT select VBOOT_ALWAYS_ENABLE_DISPLAY select VBOOT_NO_BOARD_SUPPORT select HAS_RECOVERY_MRC_CACHE + select VBOOT_NO_TPM + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE config VBOOT_SLOTS_RW_AB default y if VBOOT @@ -73,4 +79,19 @@ config FMDFILE config GBB_HWID default "MSI_MS7E06" +if !VBOOT && MSI_ROMHOLE_IN_CBFS + +# FIXME: Make coreboot build system automatically fixup the ucode and FIT location +# so that creating FIT does not fail. +config CPU_MICROCODE_CBFS_LOC + hex + default 0xff800000 + +config INTEL_FIT_LOC + hex + default 0xfffc0000 + +endif + + endif diff --git a/src/mainboard/msi/ms7e06/Kconfig.name b/src/mainboard/msi/ms7e06/Kconfig.name index 8154492d628..026018024b2 100644 --- a/src/mainboard/msi/ms7e06/Kconfig.name +++ b/src/mainboard/msi/ms7e06/Kconfig.name @@ -3,5 +3,5 @@ config BOARD_MSI_Z790_P_PRO_WIFI_DDR4 bool "PRO Z790-P (WIFI) DDR4" -config BOARD_MSI_Z790_P_PRO_WIFI +config BOARD_MSI_Z790_P_PRO_WIFI_DDR5 bool "PRO Z790-P (WIFI)" diff --git a/src/mainboard/msi/ms7e06/Makefile.mk b/src/mainboard/msi/ms7e06/Makefile.mk index deb5ff625a6..cc0df70e7bd 100644 --- a/src/mainboard/msi/ms7e06/Makefile.mk +++ b/src/mainboard/msi/ms7e06/Makefile.mk @@ -2,9 +2,32 @@ bootblock-y += bootblock.c +$(call src-to-obj,bootblock,$(dir)/msi_id.S): $(obj)/fmap_config.h +bootblock-y += msi_id.S + romstage-y += romstage_fsp_params.c ramstage-y += mainboard.c +ramstage-y += smbios.c all-y += die.c smm-y += die.c + +ifeq ($(CONFIG_MSI_ROMHOLE_IN_CBFS),y) + +$(obj)/mainboard/$(MAINBOARDDIR)/bpa.bin: + dd if=/dev/zero of=$@ bs=64K count=1 + +cbfs-files-y += bpa.bin + +bpa.bin-file := $(obj)/mainboard/$(MAINBOARDDIR)/bpa.bin +bpa.bin-type := raw +bpa.bin-compression := none +bpa.bin-position := 0xff080000 # Fixed position from original MSI firmware + +# Workaround: place build_info exactly at the EXT_BIOS_WINDOW boundary (plus +# the metadata size) to avoid files getting fragmented between +# FIXED_BIOS_WINDOW and EXT_BIOS_WINDOW. +build_info-COREBOOT-position := 0xff000040 + +endif diff --git a/src/mainboard/msi/ms7e06/acpi/mainboard.asl b/src/mainboard/msi/ms7e06/acpi/mainboard.asl index 8cc72ab68d7..6aca5b5e8f9 100644 --- a/src/mainboard/msi/ms7e06/acpi/mainboard.asl +++ b/src/mainboard/msi/ms7e06/acpi/mainboard.asl @@ -8,7 +8,7 @@ Scope (_GPE) { Scope (\_SB.PCI0) { /* This device triggers automatic drivers and MSI utilities installation on Windows */ Device (MSIV) { - Name (_HID, "MBID0001") + Name (_HID, "MBID0002") Name (_UID, 1) Method (_STA, 0, NotSerialized){ Return (1) diff --git a/src/mainboard/msi/ms7e06/bootblock.c b/src/mainboard/msi/ms7e06/bootblock.c index 110d6828a61..55c2a88dec0 100644 --- a/src/mainboard/msi/ms7e06/bootblock.c +++ b/src/mainboard/msi/ms7e06/bootblock.c @@ -4,42 +4,76 @@ #include #include #include +#include +#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7) #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) +#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART) +#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC) + +#define EC_IO_BASE 0xa20 void bootblock_mainboard_early_init(void) { /* Replicate vendor settings for multi-function pins in global config LDN */ - nuvoton_pnp_enter_conf_state(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low - pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + nuvoton_pnp_enter_conf_state(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low + pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low /* Below are multi-pin function */ - pnp_write_config(SERIAL_DEV, 0x15, 0xaa); - pnp_write_config(SERIAL_DEV, 0x1a, 0x02); - pnp_write_config(SERIAL_DEV, 0x1b, 0x02); - pnp_write_config(SERIAL_DEV, 0x1d, 0x00); - pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); - pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); - pnp_write_config(SERIAL_DEV, 0x22, 0xbd); - pnp_write_config(SERIAL_DEV, 0x23, 0xdf); - pnp_write_config(SERIAL_DEV, 0x24, 0x39); - pnp_write_config(SERIAL_DEV, 0x25, 0xfe); - pnp_write_config(SERIAL_DEV, 0x26, 0x40); - pnp_write_config(SERIAL_DEV, 0x27, 0x77); - pnp_write_config(SERIAL_DEV, 0x28, 0x00); - pnp_write_config(SERIAL_DEV, 0x29, 0xfb); - pnp_write_config(SERIAL_DEV, 0x2a, 0x80); - pnp_write_config(SERIAL_DEV, 0x2b, 0x20); - pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); - pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); + pnp_write_config(GPIO_DEV, 0x15, 0xaa); + pnp_write_config(GPIO_DEV, 0x1a, 0x02); + pnp_write_config(GPIO_DEV, 0x1b, 0x02); + pnp_write_config(GPIO_DEV, 0x1d, 0x00); + pnp_write_config(GPIO_DEV, 0x1e, 0xaa); + pnp_write_config(GPIO_DEV, 0x1f, 0xb2); + pnp_write_config(GPIO_DEV, 0x22, 0xbd); + pnp_write_config(GPIO_DEV, 0x23, 0xdf); + pnp_write_config(GPIO_DEV, 0x24, 0x39); + pnp_write_config(GPIO_DEV, 0x25, 0xfe); + pnp_write_config(GPIO_DEV, 0x26, 0x40); + pnp_write_config(GPIO_DEV, 0x27, 0x77); + pnp_write_config(GPIO_DEV, 0x28, 0x00); + pnp_write_config(GPIO_DEV, 0x29, 0xfb); + pnp_write_config(GPIO_DEV, 0x2a, 0x80); + pnp_write_config(GPIO_DEV, 0x2b, 0x20); + pnp_write_config(GPIO_DEV, 0x2c, 0x8a); + pnp_write_config(GPIO_DEV, 0x2d, 0xaa); + + /* Set GPIO 06 as high output */ + pnp_write_config(GPIO_DEV, 0xF0, 0x00); + pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40); + pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00); pnp_set_logical_device(POWER_DEV); /* Configure pin for PECI */ pnp_write_config(POWER_DEV, 0xf3, 0x80); - nuvoton_pnp_exit_conf_state(POWER_DEV); + /* Configure power fault detection */ + pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30); + pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01); + + /* Configure yellow and green LED */ + pnp_write_config(POWER_DEV, 0xe7, 0x88); + pnp_write_config(POWER_DEV, 0xe8, 0x07); + pnp_set_logical_device(P80_UART_DEV); + pnp_write_config(P80_UART_DEV, 0xe5, 0x0f); + + /* Configure EC */ + pnp_set_logical_device(EC_DEV); + pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE); + pnp_set_enable(EC_DEV, 1); + + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0); + nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03); + nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04); + + + nuvoton_pnp_exit_conf_state(EC_DEV); if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index eb179885c17..7d4d9973a96 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -7,6 +7,7 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" register "RMT" = "0" register "enable_c6dram" = "1" + register "enable_hwp_scalability_tracking" = "true" register "pmc_gpe0_dw0" = "GPP_J" register "pmc_gpe0_dw1" = "GPP_VPGIO" @@ -33,6 +34,7 @@ chip soc/intel/alderlake smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong" "PCI_E1" "SlotDataBusWidth16X" end + device ref pcie5_1 off end device ref igpu on # HDMI on port B register "ddi_portB_config" = "1" @@ -54,34 +56,35 @@ chip soc/intel/alderlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end + device ref crashlog off end device ref xhci on - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 - register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5 - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0 - register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty? - register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4 - register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4 - register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3 - register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3 - register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 - register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 - register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers - register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # USB-C LAN_USB1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # MSI MYSTIC LIGHT + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # USB-A LAN_USB1 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # JUSB5 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # HUB to rear USB 2.0 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" # JUSB4 + register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" # JUSB4 + register "usb2_ports[8]" = "USB2_PORT_LONG(OC4)" # JUSB3 + register "usb2_ports[9]" = "USB2_PORT_LONG(OC4)" # JUSB3 + register "usb2_ports[10]" = "USB2_PORT_LONG(OC5)" # PS2_USB1 + register "usb2_ports[11]" = "USB2_PORT_LONG(OC5)" # PS2_USB1 + register "usb2_ports[12]" = "USB2_PORT_MID(OC6)" # HUB to USB 2.0 headers + register "usb2_ports[13]" = "USB2_PORT_LONG(OC6)" # CNVi BT register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 - register "usb3_ports[9]" = "USB3_PORT_EMPTY" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB-C Gen2x2 LAN_USB1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB-C Gen2x2 LAN_USB1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB-A LAN_USB1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # JUSB5 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # USB-A USB2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # USB-A USB2 + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC3)" # JUSB4 + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC3)" # JUSB4 + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC4)" # JUSB3 + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC4)" # JUSB3 end device ref cnvi_wifi on # Enable CNVi BT @@ -118,6 +121,17 @@ chip soc/intel/alderlake [6] = 1, [7] = 1, }" + + register "sata_ports_hotplug" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" end device ref pcie_rp1 on register "pch_pcie_rp[PCH_RP(1)]" = "{ @@ -144,6 +158,7 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, }" end + device ref pcie_rp4 off end device ref pcie_rp5 on register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -197,12 +212,170 @@ chip soc/intel/alderlake "M2_2" "SlotDataBusWidth4X" end device ref pch_espi on + # LPC generic I/O ranges register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x003c0a01" register "gen3_dec" = "0x000c03f1" register "gen4_dec" = "0x000c0081" chip superio/nuvoton/nct6687d + register "sensors[0]" = "PECI_AGENT0_DOMAIN0" + register "sensors[1]" = "TD0P_CURRENT_MODE" + register "sensors[2]" = "THERMISTOR15" + register "sensors[3]" = "PCH_CHIP" + register "sensors[4]" = "THERMISTOR16" + register "sensors[5]" = "THERMISTOR0" + register "sensors[6]" = "THERMISTOR1" + register "sensors[16]" = "VIN0" + register "sensors[17]" = "VIN1" + register "sensors[18]" = "VIN2" + register "sensors[19]" = "VIN3" + register "sensors[20]" = "VIN4" + register "sensors[21]" = "VIN5" + register "sensors[22]" = "VIN6" + register "sensors[23]" = "VIN7" + register "sensors[24]" = "VCC" + + register "smbus_sensor.sensor_idx" = "3" + register "smbus_sensor.sensor_en" = "true" + register "smbus_sensor.sensor_cmd" = "0x40" + register "smbus_sensor.sensor_addr" = "0x96" + register "smbus_sensor.baud_rate" = "BAUD_100K" + register "smbus_sensor.report_one_byte" = "true" + register "smbus_sensor.port_sel" = "1" + + register "peci_speed" = "PECI_1200KHZ" + + register "fan_default_val" = "60" + + register "smart_tracking.speed_boundary_low" = "1500" + register "smart_tracking.speed_boundary_high" = "2500" + register "smart_tracking.rpm_tolerance_low" = "100" + register "smart_tracking.rpm_tolerance_mid" = "100" + register "smart_tracking.rpm_tolerance_high" = "100" + register "smart_tracking.step_up" = "1" + register "smart_tracking.step_down" = "1" + + # CPU_FAN + register "FAN1.mode" = "FAN_SMART_FAN_IV" + register "FAN1.unit_sel" = "FAN_PWM" + register "FAN1.fanin_sel" = "TACH_PWM1" + register "FAN1.fanout_sel" = "TACH_PWM0" + register "FAN1.fan_alg_weight" = "10" + register "FAN1.smart_tracking_en" = "true" + register "FAN1.crit_temp" = "101" + register "FAN1.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN1.smart_fan.temp_levels" = "{ 40, 55, 70, 85, 90, 95, 100 }" + register "FAN1.smart_fan.speed_levels" = "{ 13, 38, 63, 85, 90, 95, 100 }" + register "FAN1.smart_fan.cut_off_delay" = "5" + register "FAN1.smart_fan.step_up_time" = "1" + register "FAN1.smart_fan.step_down_time" = "1" + + # PUMP_FAN + register "FAN2.mode" = "FAN_SMART_FAN_IV" + register "FAN2.unit_sel" = "FAN_PWM" + register "FAN2.fanin_sel" = "TACH_PWM3" + register "FAN2.fanout_sel" = "TACH_PWM2" + register "FAN2.fan_alg_weight" = "10" + register "FAN2.smart_tracking_en" = "true" + register "FAN2.crit_temp" = "101" + register "FAN2.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN2.smart_fan.temp_levels" = "{ 32, 32, 32, 32, 32, 32, 32 }" + register "FAN2.smart_fan.speed_levels" = "{ 100, 100, 100, 100, 100, 100, 100 }" + register "FAN2.smart_fan.cut_off_delay" = "5" + register "FAN2.smart_fan.step_up_time" = "1" + register "FAN2.smart_fan.step_down_time" = "1" + + # SYS_FAN1 + register "FAN3.mode" = "FAN_SMART_FAN_IV" + register "FAN3.unit_sel" = "FAN_PWM" + register "FAN3.fanin_sel" = "TACH_PWM11" + register "FAN3.fanout_sel" = "TACH_PWM10" + register "FAN3.fan_alg_weight" = "10" + register "FAN3.smart_tracking_en" = "true" + register "FAN3.crit_temp" = "101" + register "FAN3.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN3.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN3.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN3.smart_fan.cut_off_delay" = "5" + register "FAN3.smart_fan.step_up_time" = "1" + register "FAN3.smart_fan.step_down_time" = "1" + + # SYS_FAN2 + register "FAN4.mode" = "FAN_SMART_FAN_IV" + register "FAN4.unit_sel" = "FAN_PWM" + register "FAN4.fanin_sel" = "TACH_PWM13" + register "FAN4.fanout_sel" = "TACH_PWM12" + register "FAN4.fan_alg_weight" = "10" + register "FAN4.smart_tracking_en" = "true" + register "FAN4.crit_temp" = "101" + register "FAN4.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN4.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN4.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN4.smart_fan.cut_off_delay" = "5" + register "FAN4.smart_fan.step_up_time" = "1" + register "FAN4.smart_fan.step_down_time" = "1" + + # SYS_FAN3 + register "FAN5.mode" = "FAN_SMART_FAN_IV" + register "FAN5.unit_sel" = "FAN_PWM" + register "FAN5.fanin_sel" = "TACH_PWM15" + register "FAN5.fanout_sel" = "TACH_PWM14" + register "FAN5.fan_alg_weight" = "10" + register "FAN5.smart_tracking_en" = "true" + register "FAN5.crit_temp" = "101" + register "FAN5.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN5.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN5.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN5.smart_fan.cut_off_delay" = "5" + register "FAN5.smart_fan.step_up_time" = "1" + register "FAN5.smart_fan.step_down_time" = "1" + + # SYS_FAN4 + register "FAN6.mode" = "FAN_SMART_FAN_IV" + register "FAN6.unit_sel" = "FAN_PWM" + register "FAN6.fanin_sel" = "TACH_PWM17" + register "FAN6.fanout_sel" = "TACH_PWM16" + register "FAN6.fan_alg_weight" = "10" + register "FAN6.smart_tracking_en" = "true" + register "FAN6.crit_temp" = "101" + register "FAN6.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN6.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN6.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN6.smart_fan.cut_off_delay" = "5" + register "FAN6.smart_fan.step_up_time" = "1" + register "FAN6.smart_fan.step_down_time" = "1" + + # SYS_FAN5 + register "FAN7.mode" = "FAN_SMART_FAN_IV" + register "FAN7.unit_sel" = "FAN_PWM" + register "FAN7.fanin_sel" = "TACH_PWM19" + register "FAN7.fanout_sel" = "TACH_PWM18" + register "FAN7.fan_alg_weight" = "10" + register "FAN7.smart_tracking_en" = "true" + register "FAN7.crit_temp" = "101" + register "FAN7.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN7.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN7.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN7.smart_fan.cut_off_delay" = "5" + register "FAN7.smart_fan.step_up_time" = "1" + register "FAN7.smart_fan.step_down_time" = "1" + + # SYS_FAN6 + register "FAN8.mode" = "FAN_SMART_FAN_IV" + register "FAN8.unit_sel" = "FAN_PWM" + register "FAN8.fanin_sel" = "TACH_PWM6" + register "FAN8.fanout_sel" = "TACH_PWM4" + register "FAN8.fan_alg_weight" = "10" + register "FAN8.smart_tracking_en" = "true" + register "FAN8.crit_temp" = "101" + register "FAN8.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN8.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN8.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN8.smart_fan.cut_off_delay" = "5" + register "FAN8.smart_fan.step_up_time" = "1" + register "FAN8.smart_fan.step_down_time" = "1" + device pnp 4e.1 off end # Parallel port device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 @@ -235,8 +408,11 @@ chip soc/intel/alderlake device pnp 0.0 on end # TPM end end + device ref p2sb hidden end device ref hda on subsystemid 0x1462 0x9e06 + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_dsp_enable" = "0" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "true" diff --git a/src/mainboard/msi/ms7e06/gpio.h b/src/mainboard/msi/ms7e06/gpio.h index 71b30e0c8c8..2014fa8ef80 100644 --- a/src/mainboard/msi/ms7e06/gpio.h +++ b/src/mainboard/msi/ms7e06/gpio.h @@ -165,14 +165,14 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group vGPIO_0 ------- */ /* These are Virtual USB OC pins */ - _PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_0 */ - _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_1 */ - _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_2 */ - _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_3 */ - _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_8 */ - _PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_9 */ - _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_10 */ - _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_11 */ + _PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_0 */ + _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_1 */ + _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_2 */ + _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_3 */ + _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_8 */ + _PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_9 */ + _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_10 */ + _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_11 */ /* ------- GPIO Community 1 ------- */ diff --git a/src/mainboard/msi/ms7e06/hda_verb.c b/src/mainboard/msi/ms7e06/hda_verb.c index 96578fa9ab6..89def1bbb31 100644 --- a/src/mainboard/msi/ms7e06/hda_verb.c +++ b/src/mainboard/msi/ms7e06/hda_verb.c @@ -6,7 +6,8 @@ const u32 cim_verb_data[] = { /* Realtek ALC897 */ 0x10ec0897, /* Vendor ID */ 0x14629e06, /* Subsystem ID */ - 15, /* Number of entries */ + 28, /* Number of entries */ + AZALIA_RESET(0x1), AZALIA_SUBVENDOR(0, 0x14629e06), AZALIA_PIN_CFG(0, 0x11, 0x4037d540), AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), @@ -23,22 +24,86 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), - /* Alderlake HDMI */ - 0x80862818, /* Vendor ID */ + 0x0205003B, + 0x02040080, + 0x02050039, + 0x02044031, + + 0x02050013, + 0x02040053, + 0x02050030, + 0x020492D1, + + 0x02050021, + 0x02040000, + 0x02050023, + 0x02040000, + + 0x02050025, + 0x02040000, + 0x02050027, + 0x02040000, + + 0x02050029, + 0x02040000, + 0x0205002A, + 0x02041640, + + 0x0205002B, + 0x02041640, + 0x02050021, + 0x02040C00, + + 0x02050023, + 0x02040C00, + 0x02050025, + 0x02040C00, + + 0x02050027, + 0x02040C00, + 0x02050029, + 0x02040C00, + + 0x0205002A, + 0x02041641, + 0x0205002B, + 0x02041641, + + 0x02050030, + 0x02049251, + 0x0205002A, + 0x02041649, + + 0x0205002B, + 0x02041649, + 0x0205000C, + 0x02043F06, + + 0x02050007, + 0x0204F808, + 0x02050007, + 0x0204F808, + + /* RaptorLake HDMI */ + 0x8086280f, /* Vendor ID */ 0x80860101, /* Subsystem ID */ 10, /* Number of entries */ AZALIA_SUBVENDOR(2, 0x80860101), - AZALIA_PIN_CFG(2, 0x04, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560010), - AZALIA_PIN_CFG(2, 0x08, 0x18560010), - AZALIA_PIN_CFG(2, 0x0a, 0x18560010), - AZALIA_PIN_CFG(2, 0x0b, 0x18560010), - AZALIA_PIN_CFG(2, 0x0c, 0x18560010), - AZALIA_PIN_CFG(2, 0x0d, 0x18560010), - AZALIA_PIN_CFG(2, 0x0e, 0x18560010), - AZALIA_PIN_CFG(2, 0x0f, 0x18560010), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 }; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/ms7e06/mainboard.c b/src/mainboard/msi/ms7e06/mainboard.c index 2645f075d1f..be30b6fbabf 100644 --- a/src/mainboard/msi/ms7e06/mainboard.c +++ b/src/mainboard/msi/ms7e06/mainboard.c @@ -1,12 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include -#include #include #include #include #include +#include + + +#define MSR_ATOM_TURBO_RATIO_LIMIT 0x650 +#define MSR_ATOM_TURBO_RATIO_LIMIT_CORES 0x651 +#define MSR_BIGCORE_TURBO_RATIO_LIMIT 0x1ad +#define MSR_BIGCORE_TURBO_RATIO_LIMIT_CORES 0x1ae void mainboard_fill_fadt(acpi_fadt_t *fadt) @@ -17,51 +25,32 @@ void mainboard_fill_fadt(acpi_fadt_t *fadt) static void mainboard_init(void *chip_info) { -} - -u8 smbios_mainboard_feature_flags(void) -{ - return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; -} + struct device *ps2_dev = dev_find_slot_pnp(0x4e, NCT6687D_KBC); + bool ps2_en = get_ps2_option(); -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} - -const char *smbios_system_product_name(void) -{ - return "MS-7E06"; + ps2_dev->enabled = ps2_en & 1; + printk(BIOS_DEBUG, "PS2 Controller state: %d\n", ps2_en); } -const char *smbios_mainboard_product_name(void) +static void fill_turbo_ratio_limits(FSP_S_CONFIG *params) { - if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4)) { - if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) - return "PRO Z790-P WIFI DDR4(MS-7E06)"; - else - return "PRO Z790-P DDR4(MS-7E06)"; - } + msr_t msr; - if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI)) { - if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) - return "PRO Z790-P WIFI (MS-7E06)"; - else - return "PRO Z790-P (MS-7E06)"; - } + msr = rdmsr(MSR_BIGCORE_TURBO_RATIO_LIMIT); + memcpy(¶ms->TurboRatioLimitRatio[0], &msr.lo, 4); + memcpy(¶ms->TurboRatioLimitRatio[4], &msr.hi, 4); - return CONFIG_MAINBOARD_PART_NUMBER; -} + msr = rdmsr(MSR_BIGCORE_TURBO_RATIO_LIMIT_CORES); + memcpy(¶ms->TurboRatioLimitNumCore[0], &msr.lo, 4); + memcpy(¶ms->TurboRatioLimitNumCore[4], &msr.hi, 4); -/* Only baseboard serial number is populated */ -const char *smbios_system_serial_number(void) -{ - return "Default string"; -} + msr = rdmsr(MSR_ATOM_TURBO_RATIO_LIMIT); + memcpy(¶ms->AtomTurboRatioLimitRatio[0], &msr.lo, 4); + memcpy(¶ms->AtomTurboRatioLimitRatio[4], &msr.hi, 4); -const char *smbios_system_sku(void) -{ - return "Default string"; + msr = rdmsr(MSR_ATOM_TURBO_RATIO_LIMIT_CORES); + memcpy(¶ms->AtomTurboRatioLimitNumCore[0], &msr.lo, 4); + memcpy(¶ms->AtomTurboRatioLimitNumCore[4], &msr.hi, 4); } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -171,6 +160,12 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->SataPortsSolidStateDrive[6] = 1; // M2_3 params->SataPortsSolidStateDrive[7] = 1; // M2_4 params->SataLedEnable = 1; + + /* + * If OcLock is not set in FSP-M UPD, FSP-S UPD will take and program + * zeroed turbo ratio limits. Avoid this by populating defautl values here. + */ + fill_turbo_ratio_limits(params); } #if CONFIG(GENERATE_SMBIOS_TABLES) @@ -528,7 +523,12 @@ static void mainboard_enable(struct device *dev) #endif } +static void mainboard_final(void *chip_info) +{ +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, + .final = mainboard_final, }; diff --git a/src/mainboard/msi/ms7e06/msi_id.S b/src/mainboard/msi/ms7e06/msi_id.S new file mode 100644 index 00000000000..2633ada4b74 --- /dev/null +++ b/src/mainboard/msi/ms7e06/msi_id.S @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +.section .init, "a", @progbits + +/* The following structures must reside in the last 64KiB of flash */ + +.align 16 + +build_date: + .ascii "$MSESGN$" + .ascii "E7E06IMS." +#if CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR5) + .byte 'A' +#endif +#if CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4) + .byte '1' +#endif + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte ' ' + .asciz COREBOOT_DMI_DATE + +.align 8 + +msi_sign_on: + .ascii "$MS1E7E06IMS" +#if CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR5) + .byte 'A' +#endif +#if CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4) + .byte '1' +#endif + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte 2 + +.align 8 + +bpa: + .ascii "$BPA" + .byte bpa_end - bpa + .byte 1 + .long 0x1000 + .long 6 + .byte 2 + .long 0x17c0000 + .long 0x20000 + .byte 3 + .long 0x1080000 + .long 64 + .byte 4 + .long 2 +bpa_end: + .byte 0, 0, 0, 0, 0 + + .asciz "@FC@" + .byte 2 + .byte 0 + .byte '1' + .asciz "/P /B /N" + .byte '2' + .byte 0 + .ascii "NULL" + .ascii "@@" + .fill 10, 1, 0 diff --git a/src/mainboard/msi/ms7e06/romhole.h b/src/mainboard/msi/ms7e06/romhole.h new file mode 100644 index 00000000000..f9ae37de919 --- /dev/null +++ b/src/mainboard/msi/ms7e06/romhole.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ROMHOLE_H_ +#define _ROMHOLE_H_ + +#define ROMHOLE_MAGIC 0x10012501 +#define NUM_PWD_ENTRIES 2 +#define PWD_SIZE 40 +#define NUM_GD_ENTRIES 8 +#define GD_SIZE 48 +#define NUM_US_ENTRIES 8 +#define US_SIZE 0x3851 +#define TYPE2_SIZE 256 +#define FTB_SIZE 105 +#define FIB_SIZE 512 +#define FDP_SIZE 1024 +#define BUV_SIZE 1024 +#define NUM_VOLUMES 7 + +struct uuid_structure { + uint8_t magic0[4]; // always sSiD + uint16_t length; // structure length, always 0x1a + uint8_t magic1[3]; // awlays $uD + uint8_t space; // always 0x1 + uint8_t uuid[16]; // SMBIOS type 1 UUID +} __packed; + +struct pwd_entry { + uint8_t magic[3]; // always $s$ + uint8_t number; // ordinal number + uint8_t length; // length of pwd + uint8_t pwd[PWD_SIZE]; // password? +} __packed; + +struct pwd_structure { + uint8_t magic[4]; // always spWd + uint16_t length; // structure length + struct pwd_entry entries[NUM_PWD_ENTRIES]; +} __packed; + +struct gd_entry { + uint8_t magic[3]; // always $gD + uint8_t number; // ordinal number + uint16_t length; // length of gd + uint8_t gd[GD_SIZE]; // global data? +} __packed; + +struct gpdt_structure { + uint8_t magic[4]; // always gPdT + uint16_t length; // structure length + uint8_t num_entries; // number of entries + uint8_t space; // awlays zero + struct gd_entry entries[NUM_GD_ENTRIES]; +} __packed; + +struct us_entry { + uint8_t magic[3]; // always $uS + uint8_t number; // ordinal number + uint16_t length; // length of us + uint8_t us[US_SIZE]; // user data? +} __packed; + +struct ucsc_structure { + uint8_t magic[4]; // always uCsC + uint16_t length; // structure length + struct us_entry entries[NUM_US_ENTRIES]; +} __packed; + +struct type2_rw { + uint8_t magic0[4]; // always t2Rw + uint16_t length; // structure length + uint8_t magic1[3]; // always $tW + uint8_t space; // always 0x1 + uint8_t smbios_type2[TYPE2_SIZE]; // SMBIOS type2 table +} __packed; + +struct ftb_structure { + uint8_t magic0[4]; // always $FTB + uint16_t length; // structure length + uint8_t magic1[4]; // always $DIB + uint16_t space0; // always 0x2 + uint16_t size; // size of data field, always 105 + uint16_t space1; // always 0x0 + uint8_t magic2[4]; // always MFTD + uint8_t data[FTB_SIZE]; // default 0xfe +} __packed; + +struct fib_structure { + uint8_t magic0[4]; // always $FIB + uint16_t length; // structure length + uint16_t size; // size of data field, always 512 + uint8_t magic1[4]; // always $MFX + uint8_t data[FIB_SIZE]; // default 0xfa +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P since A.40/1.40 */ +struct fdp_structure { + uint8_t magic0[4]; // always $FDP + uint16_t length; // structure length + uint8_t magic1[3]; // always $Fd + uint8_t number; // always 0x1 + uint8_t data[FDP_SIZE]; // default 0xff +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P A.40/1.40 */ +struct buv_structure { + uint8_t magic0[4]; // always $BuV + uint16_t length; // structure length + uint8_t magic1[3]; // always $Bv + uint8_t number; // always 0x1 + uint8_t data[BUV_SIZE]; // default 0xff +} __packed; + +struct volume_entry { + uint8_t number; // ordinal number in ascii + uint32_t address; // volume base address + uint32_t size; // volume size + uint8_t space; // always 0xff +} __packed; + +struct ris_structure { + uint8_t magic0[4]; // always $RiS + uint16_t length; // structure length + uint8_t magic1[4]; // always $RiT + /* Array below keep the addresses and sizes of UEFI Firmware Volumes */ + struct volume_entry volumes[NUM_VOLUMES]; +} __packed; + +/* Place the following struct in the ROMHOLE flash region with 64K/128K alignment */ +struct msi_romhole { + uint32_t magic0; // 0x10012501 + uint16_t length; // length of the structure + char magic1[4]; // always SYSD + uint32_t address; // romhole address in flash + uint32_t size; // romhole total size + uint8_t pad0[48]; // always 0xff + struct uuid_structure uuid; + struct pwd_structure pwd; + struct gpdt_structure gpdt; + struct ucsc_structure ucsc; + struct type2_rw t2rw; + struct ftb_structure ftb; + struct fib_structure fib; + struct fdp_structure fdp; + struct buv_structure buv; + struct ris_structure ris; + // the rest is padded with 0xff by cbfstool +} __packed; + +#endif diff --git a/src/mainboard/msi/ms7e06/romstage_fsp_params.c b/src/mainboard/msi/ms7e06/romstage_fsp_params.c index c8955f7247a..ff4e04abe3d 100644 --- a/src/mainboard/msi/ms7e06/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7e06/romstage_fsp_params.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -84,9 +85,13 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.MmioSize = 0xb00; /* 2.75GB in MB */ + memupd->FspmConfig.OcLock = 0; + + memupd->FspmConfig.SpdProfileSelected = dasharo_get_memory_profile(); + if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4)) memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); - if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI)) + if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR5)) memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/msi/ms7e06/smbios.c b/src/mainboard/msi/ms7e06/smbios.c new file mode 100644 index 00000000000..4d8397db926 --- /dev/null +++ b/src/mainboard/msi/ms7e06/smbios.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "romhole.h" + +struct smbios_type2_v3_4 { + struct smbios_header header; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 asset_tag; + u8 feature_flags; + u8 location_in_chassis; + u16 chassis_handle; + u8 board_type; + u8 contained_objects; + u8 eos[2]; +} __packed; + +static struct msi_romhole *romhole_addr = NULL; + +static struct msi_romhole *get_msi_romhole_address(void) +{ + struct region_device rdev; + + if (romhole_addr) + return romhole_addr; + + if (fmap_locate_area_as_rdev("ROMHOLE", &rdev)) + return NULL; + + romhole_addr = (struct msi_romhole *)rdev_mmap_full(&rdev); + + return romhole_addr; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +const char *smbios_system_product_name(void) +{ + return "MS-7E06"; +} + +const char *smbios_mainboard_product_name(void) +{ + if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4)) { + if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) + return "PRO Z790-P WIFI DDR4 (MS-7E06)"; + else + return "PRO Z790-P DDR4 (MS-7E06)"; + } + + if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR5)) { + if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) + return "PRO Z790-P WIFI (MS-7E06)"; + else + return "PRO Z790-P (MS-7E06)"; + } + + return CONFIG_MAINBOARD_PART_NUMBER; +} + +/* Only baseboard serial number is populated */ +const char *smbios_system_serial_number(void) +{ + return "Default string"; +} + +const char *smbios_system_sku(void) +{ + return "Default string"; +} + +void smbios_system_set_uuid(u8 *uuid) +{ + if (!get_msi_romhole_address()) + return; + + memcpy(uuid, romhole_addr->uuid.uuid, 16); +} + +static const char* get_smbios_string(u8 *str_table_start, u8 string_index, + const char *fallback) +{ + u8 i; + char *smbios_str = (char *)str_table_start; + + for (i = 1; i < string_index; i++) { + if (strlen(smbios_str)) + smbios_str += strlen(smbios_str) + 1; + else + return fallback; + } + + return strlen(smbios_str) ? (const char *)smbios_str : fallback; +} + +const char *smbios_mainboard_serial_number(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + return get_smbios_string(type2->eos, type2->serial_number, + CONFIG_MAINBOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_VERSION; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_VERSION; + + return get_smbios_string(type2->eos, type2->version, + CONFIG_MAINBOARD_VERSION); +} diff --git a/src/mainboard/msi/ms7e06/smihandler.c b/src/mainboard/msi/ms7e06/smihandler.c new file mode 100644 index 00000000000..3978d4fcef1 --- /dev/null +++ b/src/mainboard/msi/ms7e06/smihandler.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) +#define ACPI_DEV PNP_DEV(0x4e, NCT6687D_ACPI) + +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +static void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +static void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void disable_ps2_wake(void) +{ + uint8_t reg; + + pnp_set_logical_device(ACPI_DEV); + reg = pnp_read_config(ACPI_DEV, 0xe4); + reg &= ~0xc0; /* Disable keyboard and mouse wake via PSOUT# */ + reg &= ~0x08; /* Disable keyboard wake with any key */ + pnp_write_config(ACPI_DEV, 0xe4, reg); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + nuvoton_pnp_enter_conf_state(POWER_DEV); + pnp_set_logical_device(POWER_DEV); + + switch (slp_typ) { + case 3: + pnp_write_config(POWER_DEV, 0xe7, 0x20); /* Keep LED freq at S3-S5 */ + pnp_write_config(POWER_DEV, 0xe8, 0x05); /* Blink LED at 1Hz */ + break; + case 4: + pnp_write_config(POWER_DEV, 0xe7, 0x88); /* Set AUTO_EN */ + pnp_write_config(POWER_DEV, 0xe8, 0x07); /* LED to low */ + break; + case 5: + pnp_write_config(POWER_DEV, 0xe7, 0x88); /* Set AUTO_EN */ + pnp_write_config(POWER_DEV, 0xe8, 0x07); /* LED to low */ + disable_ps2_wake(); + break; + } + + nuvoton_pnp_exit_conf_state(POWER_DEV); +} diff --git a/src/mainboard/msi/ms7e06/vboot-rwab.fmd b/src/mainboard/msi/ms7e06/vboot-rwab.fmd index 665c8949bbe..7569cda7cc4 100644 --- a/src/mainboard/msi/ms7e06/vboot-rwab.fmd +++ b/src/mainboard/msi/ms7e06/vboot-rwab.fmd @@ -6,6 +6,10 @@ FLASH 32M { UNUSED 12M + SMMSTORE(PRESERVE) 256K + RESERVED(PRESERVE) 256K + BPA(PRESERVE) 128K + RW_MISC 320K { UNIFIED_MRC_CACHE(PRESERVE) { RECOVERY_MRC_CACHE 128K @@ -21,22 +25,25 @@ FLASH 32M { } CONSOLE 128K - SMMSTORE(PRESERVE) 256K HSPHY_FW(PRESERVE) 32K + BOOTSPLASH(CBFS) 2M - RW_SECTION_A 5264K { + RW_SECTION_A 4768K { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 0x100 } - RW_SECTION_B 5264K { + # ROMHOLE must be at flash offset 0x17c0000 + ROMHOLE(PRESERVE) 128K + + RW_SECTION_B 4224K { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 0x100 } - WP_RO 5M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K diff --git a/src/mainboard/novacustom/Kconfig b/src/mainboard/novacustom/Kconfig new file mode 100644 index 00000000000..34019efc07b --- /dev/null +++ b/src/mainboard/novacustom/Kconfig @@ -0,0 +1,21 @@ +if VENDOR_NOVACUSTOM + +choice + prompt "Mainboard model" + +source "src/mainboard/novacustom/*/Kconfig.name" + +endchoice + +source "src/mainboard/novacustom/*/Kconfig" +source "src/mainboard/clevo/*/Kconfig" + +config MAINBOARD_VENDOR + default "Notebook" + +config DGPU_ONLY_AVAILABLE + bool "dGPU Only mux pin is available" + default n + depends on EDK2_DGPU_POWER_OPTION + +endif # VENDOR_NOVACUSTOM diff --git a/src/mainboard/novacustom/Kconfig.name b/src/mainboard/novacustom/Kconfig.name new file mode 100644 index 00000000000..e135a635d52 --- /dev/null +++ b/src/mainboard/novacustom/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_NOVACUSTOM + bool "NovaCustom" diff --git a/src/mainboard/novacustom/adl-p/Kconfig b/src/mainboard/novacustom/adl-p/Kconfig new file mode 100644 index 00000000000..39d893af199 --- /dev/null +++ b/src/mainboard/novacustom/adl-p/Kconfig @@ -0,0 +1,9 @@ +config BOARD_NOVACUSTOM_NS5X_ADLP + select BOARD_CLEVO_NS50PU_BASE + +config BOARD_NOVACUSTOM_NV4X_ADLP + select BOARD_CLEVO_NV40PZ_BASE + +config MAINBOARD_PART_NUMBER + default "nv40pz" if BOARD_NOVACUSTOM_NV4X_ADLP + default "ns50pu" if BOARD_NOVACUSTOM_NS5X_ADLP diff --git a/src/mainboard/novacustom/adl-p/Kconfig.name b/src/mainboard/novacustom/adl-p/Kconfig.name new file mode 100644 index 00000000000..5b2fe3b89b4 --- /dev/null +++ b/src/mainboard/novacustom/adl-p/Kconfig.name @@ -0,0 +1,7 @@ +comment "Alder Lake P (2022)" + +config BOARD_NOVACUSTOM_NS5X_ADLP + bool "NS5x ADL" + +config BOARD_NOVACUSTOM_NV4X_ADLP + bool "NV4x ADL" diff --git a/src/mainboard/novacustom/adl-p/board_info.txt b/src/mainboard/novacustom/adl-p/board_info.txt new file mode 100644 index 00000000000..2820c1d1e74 --- /dev/null +++ b/src/mainboard/novacustom/adl-p/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: NovaCustom +Board name: adl-p +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig new file mode 100644 index 00000000000..ce52dd60683 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig @@ -0,0 +1,165 @@ +config BOARD_NOVACUSTOM_MTLH_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_WIFI_GENERIC + select EC_ACPI + select EC_DASHARO_EC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_NOVACUSTOM_V5X0TNX_BASE + bool + select EC_DASHARO_EC_DGPU + select INCLUDE_NVIDIA_GPU_ASL + select BOARD_NOVACUSTOM_MTLH_COMMON + select DRIVERS_I2C_TAS5825M + select DGPU_ONLY_AVAILABLE + +config BOARD_NOVACUSTOM_V540TNX + bool + select BOARD_NOVACUSTOM_V5X0TNX_BASE + +config BOARD_NOVACUSTOM_V560TNX + bool + select BOARD_NOVACUSTOM_V5X0TNX_BASE + +config BOARD_NOVACUSTOM_V5X0TU_BASE + bool + select MAINBOARD_USES_IFD_GBE_REGION + select BOARD_NOVACUSTOM_MTLH_COMMON + +config BOARD_NOVACUSTOM_V540TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +config BOARD_NOVACUSTOM_V560TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +if BOARD_NOVACUSTOM_MTLH_COMMON + +config MAINBOARD_DIR + default "novacustom/mtl-h" + +config VARIANT_DIR + default "igpu" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "dgpu" if BOARD_NOVACUSTOM_V5X0TNX_BASE + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" + +config MAINBOARD_VERSION + default "V540TU" if BOARD_NOVACUSTOM_V540TU + default "V560TU" if BOARD_NOVACUSTOM_V560TU + default "V540TNx" if BOARD_NOVACUSTOM_V540TNX + default "V560TNx" if BOARD_NOVACUSTOM_V560TNX + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match Insyde firmware + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_SPD_SIZE + default 1024 + +config ONBOARD_VGA_IS_PRIMARY + default y + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_ENABLE_CBFS_FALLBACK + +config VBOOT_SLOTS_RW_AB + default y if VBOOT + +config VBOOT_VBNV_OFFSET + default 0x28 + +config TPM_PIRQ + default 0x61 # GPP_E01 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config VBOOT_FWID_VERSION + default "\$(CONFIG_LOCALVERSION)" + +config EC_DASHARO_EC_FLASH_SIZE + default 0x40000 + +config EC_DASHARO_EC_CPU_FAN_COUNT + default 2 if BOARD_NOVACUSTOM_V5X0TU_BASE + +config INCLUDE_NVIDIA_GPU_ASL + def_bool n + help + Select this if the variant has an Nvidia GPU attached to RP12 + +config PXE_ROM_ID + string + default "8086,550a" if BOARD_NOVACUSTOM_V5X0TU_BASE + +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 30 + +endif + +endif diff --git a/src/mainboard/novacustom/mtl-h/Kconfig.name b/src/mainboard/novacustom/mtl-h/Kconfig.name new file mode 100644 index 00000000000..f224cedd647 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig.name @@ -0,0 +1,13 @@ +comment "Meteor Lake H" + +config BOARD_NOVACUSTOM_V540TNX + bool "V540TU (14\", discrete graphics)" + +config BOARD_NOVACUSTOM_V560TNX + bool "V560TU (16\", discrete graphics)" + +config BOARD_NOVACUSTOM_V540TU + bool "V540TU (14\", integrated graphics)" + +config BOARD_NOVACUSTOM_V560TU + bool "V560TU (16\", integrated graphics)" diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk new file mode 100644 index 00000000000..5b66f6c2176 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Makefile.mk @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c + +romstage-y += romstage.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-y += ramstage.c +ramstage-y += variants/${VARIANT_DIR}/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c diff --git a/src/mainboard/novacustom/mtl-h/acpi/backlight.asl b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl new file mode 100644 index 00000000000..01fa83ea610 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl new file mode 100644 index 00000000000..8bf8954b82b --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define GPS_FUNC_SUPPORT 0 +#define GPS_FUNC_GETCALLBACKS 0x13 +#define GPS_FUNC_PSHARESTATUS 0x20 +#define GPS_FUNC_PSHAREPARAMS 0x2a +#define GPS_FUNC_REQUESTDXSTATE 0x12 + +#define QUERY_GET_STATUS 0 +#define QUERY_GET_SUPPORTED_FIELDS 1 +#define QUERY_GET_CURRENT_LIMITS 2 + +/* GPS return Package */ +Name (GPSP, Buffer (0x24) {0x0}) +CreateDWordField (GPSP, 0, RETN) +CreateDWordField (GPSP, 4, VRV1) +CreateDWordField (GPSP, 8, TGPU) + +/* GETCALLBACKS return value + [0]: Callback for post-mode set + [1]: Callback for pre-mode set + [2]: Callback for post power state transition */ +Name (GPSR, Buffer (4) { 0x4, 0x0, 0x0, 0x0 }) + +Method (GPS, 2, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (GPS_FUNC_SUPPORT) + { + Return (LTOB( + (1 << GPS_FUNC_SUPPORT) | + (1 << GPS_FUNC_GETCALLBACKS) | + (1 << GPS_FUNC_PSHARESTATUS) | + (1 << GPS_FUNC_PSHAREPARAMS) | + (1 << GPS_FUNC_REQUESTDXSTATE))) + } + Case (GPS_FUNC_GETCALLBACKS) + { + CreateDWordField (Arg1, 0, QURY) + + /* Driver querying for which callbacks the ACPI code + wants callbacks for. */ + If (QURY == 0) + { + Return (GPSR) + } + + If (QURY & 0x4) + { + Printf("GPS: Kernel driver callback post power state transition") + Return (GPSR) + } + } + Case (GPS_FUNC_PSHARESTATUS) + { + Return (ITOB(0)) + } + Case (GPS_FUNC_PSHAREPARAMS) + { + CreateField (Arg1, 0, 4, QUTY) /* Query type */ + + /* Version of return value */ + VRV1 = 0x10000 + RETN = QUTY + + Switch (ToInteger (QUTY)) + { + Case (QUERY_GET_STATUS) + { + Return (GPSP) + } + Case (QUERY_GET_SUPPORTED_FIELDS) + { + RETN = 0x300 | ToInteger (QUTY) + CreateDWordField (GPSP, 0x0C, PDTS) + PDTS = 0x03e8 + Return (GPSP) + } + Case (QUERY_GET_CURRENT_LIMITS) + { + /* No limits */ + Return (GPSP) + } + } + } + Case (GPS_FUNC_REQUESTDXSTATE) + { + Local0 = ToInteger(\_SB.PCI0.LPCB.EC0.GPUD) + \_SB.PCI0.RP12.PXSX.DNOT (Local0, 1) + Return (NV_ERROR_SUCCESS) + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h new file mode 100644 index 00000000000..1cb03145b09 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define NV_ERROR_SUCCESS 0x0 +#define NV_ERROR_UNSPECIFIED 0x80000001 +#define NV_ERROR_UNSUPPORTED 0x80000002 + +#define PCI_OWNER_SBIOS 0x0 +#define PCI_OWNER_DRIVER 0x1 + +#define OPTIMUS_POWER_CONTROL_DISABLE 0x2 +#define OPTIMUS_POWER_CONTROL_ENABLE 0x3 + +#define OPTIMUS_CONTROL_NO_RUN_PS0 0x0 +#define OPTIMUS_CONTROL_RUN_PS0 0x1 + +#define GC6_STATE_EXITED 0x0 +#define GC6_STATE_ENTERED 0x1 +#define GC6_STATE_TRANSITION 0x2 + +#define GC6_DEFER_DISABLE 0x0 +#define GC6_DEFER_ENABLE 0x1 + +#define NOTIFY_GPS_EVENT_STATUS_CHANGE 0xc0 +#define NOTIFY_GPS_NVPCF_STATUS_CHANGE 0xc5 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_0 0xd1 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_1 0xd2 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_2 0xd3 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_3 0xd4 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_4 0xd5 + +/* Defines for NVJT subfunction */ +#define NVJT_GPC_GSS 0 +#define NVJT_GPC_EGNS 1 +#define NVJT_GPC_EGIS 2 +#define NVJT_GPS_XGXS 3 +#define NVJT_GPS_XGIS 4 + +#define UUID_NVOP "a486d8f8-0bda-471b-a72b-6042a6b5bee0" +#define UUID_NVJT "cbeca351-067b-4924-9cbd-b46b00b86f34" +#define UUID_NBCI "d4a50b75-65c7-46f7-bfb7-41514cea0244" +#define UUID_NVPCF "36b49710-2483-11e7-9598-0800200c9a66" +#define UUID_GPS "a3132d01-8cda-49ba-a52e-bc9d46df6b81" + +#define REVISION_MIN_NVOP 0x100 +#define REVISION_MIN_NVJT 0x100 +#define REVISION_MIN_NBCI 0x102 +#define REVISION_MIN_NVPCF 0x200 +#define REVISION_MIN_GPS 0x200 + +#define D1_EC 0 +#define D2_EC 1 +#define D3_EC 2 +#define D4_EC 3 +#define D5_EC 4 + +#define D1_GPU 0xD1 +#define D2_GPU 0xD2 +#define D3_GPU 0xD3 +#define D4_GPU 0xD4 +#define D5_GPU 0xD5 diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl new file mode 100644 index 00000000000..13b04294b69 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPCB.EC0) +{ + /* EC has data for GPU in memmap */ + Method (_QA0, 0, Serialized) + { + Local0 = ToInteger(GPUD) + \_SB.PCI0.RP12.PXSX.DNOT (Local0, 0) + } +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl new file mode 100644 index 00000000000..676d93c4a59 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "gpu_defines.h" + +Scope (\_SB.PCI0.RP12) +{ + #include "peg.asl" + + Device (PXSX) + { + Name (_ADR, 0x0) + OperationRegion (PCIC, PCI_Config, 0x00, 0x100) + Field (PCIC, DWordAcc, NoLock, Preserve) + { + NVID, 16, + NDID, 16, + Offset (0x40), + NVSS, 32 + } + + #include "utility.asl" + #include "power.asl" + #include "nvop.asl" + #include "nvjt.asl" + #include "nbci.asl" + #include "gps.asl" + #include "gpu_ec.asl" + + /* Convert D Notify from EC to GPU */ + Method (CNVD, 1, NotSerialized) + { + Switch (ToInteger(Arg0)) { + Case (D1_EC) { Return (D1_GPU) } + Case (D2_EC) { Return (D2_GPU) } + Case (D3_EC) { Return (D3_GPU) } + Case (D4_EC) { Return (D4_GPU) } + Case (D5_EC) { Return (D5_GPU) } + Default { Return (D5_GPU) } + } + } + + /* Current D Notify Value, defaults to D1 + * Arg0 == Shared value + * Arg1 == force notification if no change (0 or 1) + */ + Name (CDNV, D1_EC) + Method (DNOT, 2, Serialized) + { + Printf ("EC: GPU D-Notify, %o", Arg0) + If ((Arg0 != CDNV) || (Arg1 == 1)) + { + CDNV = Arg0 + Local0 = CNVD (Arg0) + Notify (\_SB.PCI0.RP12.PXSX, Local0) + } + } + + Method (_DSM, 4, Serialized) + { + If (Arg0 == ToUUID (UUID_NVOP)) + { + If (ToInteger(Arg1) >= REVISION_MIN_NVOP) + { + Return (NVOP (Arg2, Arg3)) + } + } + ElseIf (Arg0 == ToUUID (UUID_NVJT)) + { + If (ToInteger (Arg1) >= REVISION_MIN_NVJT) + { + Return (NVJT (Arg2, Arg3)) + } + } + ElseIf (Arg0 == ToUUID (UUID_NBCI)) + { + If (ToInteger (Arg1) >= REVISION_MIN_NBCI) + { + Return (NBCI (Arg2, Arg3)) + } + } + ElseIf (Arg0 == ToUUID (UUID_GPS)) + { + If (ToInteger (Arg1) >= REVISION_MIN_GPS) + { + Return (GPS (Arg2, Arg3)) + } + } + + Return (NV_ERROR_UNSUPPORTED) + } + } +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl new file mode 100644 index 00000000000..1546928aef3 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define NBCI_FUNC_SUPPORT 0 +#define NBCI_FUNC_GETOBJBYTYPE 16 +#define NBCI_FUNC_GETCALLBACKS 19 + +#define GPS_FUNC_GETCALLBACKS 0x13 + +Method (NBCI, 2, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (NBCI_FUNC_SUPPORT) + { + Return (ITOB( + (1 << NBCI_FUNC_SUPPORT) | + (1 << NBCI_FUNC_GETCALLBACKS))) + } + Case (NBCI_FUNC_GETCALLBACKS) + { + /* Re-use the GPS subfunction's GETCALLBACKS Method */ + Return (GPS (GPS_FUNC_GETCALLBACKS, Arg1)) + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl new file mode 100644 index 00000000000..2a0790167f6 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define JT_FUNC_SUPPORT 0 +#define JT_FUNC_CAPS 1 +#define JT_FUNC_POWERCONTROL 3 +#define JT_FUNC_PLATPOLICY 4 + +Method (NVJT, 2, Serialized) +{ + Switch (ToInteger(Arg0)) + { + Case (JT_FUNC_SUPPORT) + { + Return (ITOB( + (1 << JT_FUNC_SUPPORT) | + (1 << JT_FUNC_CAPS) | + (1 << JT_FUNC_POWERCONTROL))) + } + Case (JT_FUNC_CAPS) + { + Return (ITOB( + (1 << 0) | /* JTE: G-Sync NVSR Power Features Enabled */ + (1 << 0) | /* NVSE: NVSR Disabled */ + (2 << 3) | /* PPR: Panel Power Rail */ + (0 << 5) | /* SRPR: Self-Refresh Controller Power Rail */ + (0 << 6) | /* FBPR: FB Power Rail */ + (0 << 8) | /* GPR: GPU Power Rail */ + (0 << 10) | /* GCR: GC6 ROM */ + (1 << 11) | /* PTH: No SMI Handler */ + (0 << 12) | /* NOT: Supports Notify on GC6 State done */ + (1 << 13) | /* MHYB: MS Hybrid Support (deferred GC6) */ + (1 << 14) | /* RPC: Root Port Control */ + (2 << 15) | /* GC6 Version (GC6-R) */ + (0 << 17) | /* GEI: GC6 Exit ISR Support */ + (0 << 18) | /* GSW: GC6 Self Wakeup */ + (0x200 << 20))) /* MXRV: Highest Revision */ + } + Case (JT_FUNC_POWERCONTROL) + { + CreateField (Arg1, 0, 3, GPC) /* GPU Power Control */ + CreateField (Arg1, 4, 1, PPC) /* Panel Power Control */ + CreateField (Arg1, 14, 2, DFGC) /* Defer GC6 enter/exit */ + CreateField (Arg1, 16, 3, GPCX) /* Deferred GC6 exit */ + + /* Deferred GC6 entry/exit is requested */ + If (ToInteger(GPC) != 0 || ToInteger(DFGC) != 0) + { + DFEN = ToInteger(DFGC) + DFCI = ToInteger(GPC) + DFCO = ToInteger(GPCX) + } + + Local0 = Buffer (4) { 0x0 } + CreateField (Local0, 0, 3, CGCS) /* Current GC State */ + CreateField (Local0, 3, 1, CGPS) /* Current GPU power status */ + CreateField (Local0, 7, 1, CPSS) /* Current panel and SRC state */ + + /* Leave early if deferred GC6 is requested */ + If (DFEN != 0) + { + CGCS = 1 + CGPS = 1 + Return (Local0) + } + + Switch (ToInteger(GPC)) + { + /* Get GCU GCx Sleep Status */ + Case (NVJT_GPC_GSS) + { + If (PSTA () != 0) + { + CGPS = 1 + CGCS = 1 + } + Else + { + CGPS = 0 + CGCS = 3 + } + } + Case (NVJT_GPC_EGNS) + { + /* Enter GC6; no self-refresh */ + GC6I () + CPSS = 1 + CGCS = 0 + } + Case (NVJT_GPC_EGIS) + { + /* Enter GC6; enable self-refresh */ + GC6I () + If (ToInteger (PPC) == 0) + { + CPSS = 0 + } + CGCS = 0 + } + Case (NVJT_GPS_XGXS) + { + /* Exit GC6; stop self-refresh */ + GC6O () + CGCS = 1 + CGPS = 1 + If (ToInteger (PPC) != 0) + { + CPSS = 0 + } + } + Case (NVJT_GPS_XGIS) + { + /* Exit GC6 for self-refresh */ + GC6O () + CGCS = 1 + CGPS = 1 + If (ToInteger (PPC) != 0) + { + CPSS = 0 + } + } + } + + Return (Local0) + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl new file mode 100644 index 00000000000..1f534be5496 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define NVOP_FUNC_SUPPORT 0x00 +#define NVOP_FUNC_OPTIMUS_CAPS 0x1a +#define NVOP_FUNC_OPTIMUS_STATUS 0x1b + +Method (NVOP, 2, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (NVOP_FUNC_SUPPORT) + { + Return (ITOB ( + (1 << NVOP_FUNC_SUPPORT) | + (1 << NVOP_FUNC_OPTIMUS_CAPS) | + (1 << NVOP_FUNC_OPTIMUS_STATUS))) + } + Case (NVOP_FUNC_OPTIMUS_CAPS) + { + CreateField(Arg1, 0, 1, FLUP) /* Flag Update */ + CreateField(Arg1, 1, 1, CSOT) /* Change configuration Space Owner Target */ + CreateField(Arg1, 2, 1, CSOW) /* Change configuration Space Owner Write */ + CreateField(Arg1, 24, 2, NPCE) /* New Power Control Enable setting */ + + /* Change Optimus power control capabilities */ + If (ToInteger (FLUP) != 0 && ToInteger (NPCE) != 0) + { + OPCS = NPCE + } + + /* Change PCI configuration space save/restore owner */ + If (ToInteger (CSOW) == 1) + { + PCIO = CSOT + } + + /* Current GPU Control Status */ + If (PSTA () == 1) + { + Local0 = 3 + } + Else + { + Local0 = 0 + } + + Return (ITOB ( + (1 << 0) | /* Optimus Enabled */ + (Local0 << 3) | /* Current GPU Control Status */ + (1 << 6) | /* Shared Discrete GPU Hotplug Capabilities */ + (0 << 7) | /* MUXed DDC/Aux Capabilities */ + (PCIO << 8) | /* PCIe Configuration Space Owner */ + (1 << 24) | /* Platform Optimus Power Capabilities */ + (3 << 27))) /* Optimus HD Audio Codec Capabilities */ + } + Case (NVOP_FUNC_OPTIMUS_STATUS) + { + Return (ITOB ( + (1 << 0) | /* Optimus Audio Codec Control */ + (0 << 2) | /* Request GPU Power State */ + (0 << 4) | /* Evaluate Requested GPU Power State */ + (0 << 5) | /* Request Optimus Adapter Policy */ + (0 << 7))) /* Evaluate Requested Optimus Adapter Selection */ + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl new file mode 100644 index 00000000000..ac0c17cbb2e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +External (\_SB.PCI0.RP12.PXSX.NPON, MethodObj) +External (\_SB.PCI0.RP12.PXSX.NPOF, MethodObj) + +OperationRegion (PCIC, PCI_Config, 0x00, 0x100) +Field (PCIC, AnyAcc, NoLock, Preserve) +{ + Offset (0x4a), + CEDR, 1, /* Correctable Error Detected, RW/1C/V */ + Offset (0x52), + , 13, + LASX, 1, /* Link Active Status */ + Offset (0x69), + , 2, + LREN, 1, /* LTR Enabled */ + Offset (0xe0), + , 7, + NCB7, 1, /* Scratch bit to save L2/3 state */ + Offset (0xe2), + , 2, + L23E, 1, /* L23_Rdy Entry request */ + L23R, 1 /* L23_Rdy Detect Transition */ +} + +/* L2/3 Entry sequence */ +Method (DL23, 0, Serialized) +{ + L23E = 1 + Local0 = 8 + While (Local0 > 0) + { + If (!L23E) + { + Break + } + + Sleep (2) + Local0-- + } + NCB7 = 1 +} + +/* L2/3 exit seqeuence */ +Method (LD23, 0, Serialized) +{ + If (!NCB7) + { + Return + } + + L23R = 1 + Local0 = 20 + While (Local0 > 0) + { + If (!L23R) + { + Break + } + + Sleep (2) + Local0-- + } + + NCB7 = 0 + Local0 = 8 + While (Local0 > 0) + { + If (LASX == 1) + { + Break + } + + Sleep (2) + Local0-- + } +} + +/* PEG Power Resource */ +PowerResource (PGPR, 0, 0) +{ + Method (_ON, 0, Serialized) + { + /* Power up GPU from GCOFF (or GC6 exit if deferred) */ + \_SB.PCI0.RP12.PXSX.NPON () + _STA = 1 + } + Method (_OFF, 0, Serialized) + { + /* Power down GPU to GCOFF (or GC6 entry if deferred) */ + _STA = 0 + \_SB.PCI0.RP12.PXSX.NPOF () + } + Name (_STA, 0) +} + +Name (_PR0, Package() { PGPR }) +Name (_PR2, Package() { PGPR }) +Name (_PR3, Package() { PGPR }) diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl new file mode 100644 index 00000000000..496fd2c1476 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +External (\_SB.PCI0.SPCO, MethodObj) + + +/* Board specific defines */ + +/* PCI Subsystem ID to restore after wake */ +#define GPU_SSID 0xa7611558 + +/* Power control signals */ +#define GPIO_GPU_PERST_L GPP_B09 +#define GPIO_GPU_PWR_EN GPP_D03 +#define GPIO_GPU_PWR_GD GPP_C15 +#define GPIO_GPU_NVVDD_EN GPP_F16 + +/* GPU clock pin */ +#define GPU_SRCCLK_PIN 0x6 + +#define GC6_DEFER_TYPE_EXIT_GC6 3 + +/* 250ms in "Timer" units (i.e. 100ns increments) */ +#define MIN_OFF_TIME_TIMERS 2500000 + +#define SRCCLK_DISABLE 0 +#define SRCCLK_ENABLE 1 + +#define GPU_POWER_STATE_OFF 0 +#define GPU_POWER_STATE_ON 1 + +/* Optimus Power Control State */ +Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE) + +/* PCI configuration space Owner */ +Name (PCIO, PCI_OWNER_SBIOS) + +/* Deferred GPU State */ +Name (OPS0, OPTIMUS_CONTROL_NO_RUN_PS0) + +/* GC6 Entry/Exit state */ +Name (GC6E, GC6_STATE_EXITED) + +/* Power State, GCOFF, GCON */ +Name (GPPS, GPU_POWER_STATE_ON) + +/* Defer GC6 entry / exit until D3-cold request */ +Name (DFEN, 0) +/* Deferred GC6 Enter control */ +Name (DFCI, 0) +/* Deferred GC6 Exit control */ +Name (DFCO, 0) +/* GCOFF Timer */ +Name (GCOT, 0) + +/* Copy of LTR enable bit from PEG port */ +Name (SLTR, 0) + +/* Control the PCIe SRCCLK# for dGPU */ +Method (SRCC, 1, Serialized) +{ + /* Control clock via P2SB interface */ + \_SB.PCI0.SPCO (GPU_SRCCLK_PIN, Arg0) +} + +/* "GC6 In", i.e. GC6 Entry Sequence */ +Method (GC6I, 0, Serialized) +{ + GC6E = GC6_STATE_TRANSITION + + /* Save the PEG port's LTR setting */ + SLTR = LREN + + /* Put PCIe link into L2/3 */ + \_SB.PCI0.RP12.DL23 () + + /* Wait for GPU to deassert its GPIO4, i.e. GPU_NVVDD_EN */ + GPPL (GPIO_GPU_NVVDD_EN, 0, 20) + + /* Assert GPU_PERST_L */ + CTXS (GPIO_GPU_PERST_L) + + /* Disable PCIe SRCCLK# */ + SRCC (SRCCLK_DISABLE) + + GC6E = GC6_STATE_ENTERED +} + +/* "GC6 Out", i.e. GC6 Exit Sequence */ +Method (GC6O, 0, Serialized) +{ + GC6E = GC6_STATE_TRANSITION + + /* Re-enable PCIe SRCCLK# */ + SRCC (SRCCLK_ENABLE) + + /* Deassert GPU_PERST_L */ + STXS (GPIO_GPU_PERST_L) + + /* Wait for GPU to assert GPU_NVVDD_EN */ + GPPL (GPIO_GPU_NVVDD_EN, 1, 20) + + /* Restore PCIe link back to L0 state */ + \_SB.PCI0.RP12.LD23 () + + /* Wait for dGPU to reappear on the bus */ + Local0 = 50 + While (NVID != PCI_VID_NVIDIA) + { + Stall (100) + Local0-- + If (Local0 == 0) + { + Break + } + } + + /* Restore the PEG LTR enable bit */ + LREN = SLTR + + /* Clear recoverable errors detected bit */ + CEDR = 1 + + GC6E = GC6_STATE_EXITED +} + +/* GCOFF exit sequence */ +Method (PGON, 0, Serialized) +{ + Local0 = Timer - GCOT + If (Local0 < MIN_OFF_TIME_TIMERS) + { + Local1 = (MIN_OFF_TIME_TIMERS - Local0) / 10000 + Printf("Sleeping %o to ensure min GCOFF time", Local1) + Sleep (Local1) + } + + /* Assert PERST# */ + CTXS (GPIO_GPU_PERST_L) + + /* Enable power rails */ + STXS (GPIO_GPU_PWR_EN) + + /* Wait 200ms for PWRGD */ + GPPL (GPIO_GPU_PWR_GD, 1, 200) + + /* Deassert PERST# */ + STXS (GPIO_GPU_PERST_L) + + GC6E = GC6_STATE_EXITED + GPPS = GPU_POWER_STATE_ON +} + +/* GCOFF entry sequence */ +Method (PGOF, 0, Serialized) +{ + /* Assert PERST# */ + CTXS (GPIO_GPU_PERST_L) + + /* Disable power rails */ + CTXS (GPIO_GPU_PWR_EN) + + GCOT = Timer + + GPPS = GPU_POWER_STATE_OFF +} + +/* GCOFF Out, i.e. full power-on sequence */ +Method (GCOO, 0, Serialized) +{ + If (GPPS == GPU_POWER_STATE_ON) + { + Printf ("PGON: GPU already on") + Return + } + + SRCC (SRCCLK_ENABLE) + PGON () + \_SB.PCI0.RP12.LD23 () + + /* Wait for dGPU to reappear on the bus */ + Local0 = 50 + While (NVID != PCI_VID_NVIDIA) + { + Stall (100) + Local0-- + If (Local0 == 0) + { + Break + } + } + + /* Restore the PEG LTR enable bit */ + LREN = SLTR + + /* Clear recoverable errors detected bit */ + CEDR = 1 + + /* Restore the PEG LTR enable bit */ + LREN = SLTR + + /* Clear recoverable errors detected bit */ + CEDR = 1 +} + +/* GCOFF In, i.e. full power-off sequence */ +Method (GCOI, 0, Serialized) +{ + If (GPPS == GPU_POWER_STATE_OFF) + { + Printf ("GPU already off") + Return + } + + /* Save the PEG port's LTR setting */ + SLTR = LREN + \_SB.PCI0.RP12.DL23 () + PGOF () + SRCC (SRCCLK_DISABLE) +} + +/* Handle deferred GC6 vs. poweron request */ +Method (NPON, 0, Serialized) +{ + If (DFEN == GC6_DEFER_ENABLE) + { + If (DFCO == GC6_DEFER_TYPE_EXIT_GC6) + { + GC6O () + } + + DFEN = GC6_DEFER_DISABLE + } + Else + { + GCOO () + } + NVSS = GPU_SSID +} + +/* Handle deferred GC6 vs. poweroff request */ +Method (NPOF, 0, Serialized) +{ + /* Don't touch the `DFEN` flag until the GC6 exit. */ + If (DFEN == GC6_DEFER_ENABLE) + { + /* Deferred GC6 entry */ + If (DFCI == NVJT_GPC_EGNS || DFCI == NVJT_GPC_EGIS) + { + GC6I () + } + } + Else + { + GCOI () + } +} + +Method (_ON, 0, Serialized) +{ + PGON () + NVSS = GPU_SSID +} + +Method (_OFF, 0, Serialized) +{ + PGOF () +} + +/* Put device into D0 */ +Method (_PS0, 0, NotSerialized) +{ + If (OPS0 == OPTIMUS_CONTROL_RUN_PS0) + { + /* Poweron or deferred GC6 exit */ + NPON () + + OPS0 = OPTIMUS_CONTROL_NO_RUN_PS0 + } +} + +/* Put device into D3 */ +Method (_PS3, 0, NotSerialized) +{ + If (OPCS == OPTIMUS_POWER_CONTROL_ENABLE) + { + /* Poweroff or deferred GC6 entry */ + NPOF () + + /* Because _PS3 ran NPOF, _PS0 must run NPON */ + OPS0 = OPTIMUS_CONTROL_RUN_PS0 + + /* OPCS is one-shot, so reset it */ + OPCS = OPTIMUS_POWER_CONTROL_DISABLE + } +} + +Method (PSTA, 0, Serialized) +{ + If (GC6E == GC6_STATE_EXITED && + \_SB.PCI0.GTXS(GPIO_GPU_PWR_GD) == 1) + { + Return (1) + } + Else + { + Return (0) + } +} + +Method (_STA, 0, Serialized) +{ + Return (0xF) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl new file mode 100644 index 00000000000..49f3dca8e93 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Poll a GPIO until it goes to the specified state + * Arg0 == GPIO # + * Arg1 == state (0 or 1) + * Arg2 == timeout in ms + */ +Method (GPPL, 3, Serialized) +{ + Local0 = 0 + Local1 = Arg2 * 10 + While (Local0 < Local1) + { + If (\_SB.PCI0.GRXS (Arg0) == Arg1) { + Return (0) + } Else { + Local0++ + } + Stall (100) + } + + If (Local0 == Arg2) { + Printf("[ERROR] GPPL for %o timed out", Arg0) + } + + Return (0xFF) +} + +/* Convert from 32-bit integer to 4-byte buffer (little-endian) */ +Method (ITOB, 1) +{ + Local0 = Buffer(4) { 0, 0, 0, 0 } + Local0[0] = Arg0 & 0xFF + Local0[1] = (Arg0 >> 8) & 0xFF + Local0[2] = (Arg0 >> 16) & 0xFF + Local0[3] = (Arg0 >> 24) & 0xFF + Return (Local0) +} + +/* Convert from 64-bit integer to 8-byte buffer (little-endian) */ +Method (LTOB, 1) +{ + Local0 = Buffer(8) { 0, 0, 0, 0, 0, 0, 0, 0 } + Local0[0] = Arg0 & 0xFF + Local0[1] = (Arg0 >> 8) & 0xFF + Local0[2] = (Arg0 >> 16) & 0xFF + Local0[3] = (Arg0 >> 24) & 0xFF + Local0[4] = (Arg0 >> 32) & 0xFF + Local0[5] = (Arg0 >> 40) & 0xFF + Local0[6] = (Arg0 >> 48) & 0xFF + Local0[7] = (Arg0 >> 56) & 0xFF + Return (Local0) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl new file mode 100644 index 00000000000..44943c1edaf --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#define CPU_CRIT_TEMP 100 +#define GPU_CRIT_TEMP 105 +#include + +Scope (\_SB) { + #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/sleep.asl b/src/mainboard/novacustom/mtl-h/acpi/sleep.asl new file mode 100644 index 00000000000..5d4bb78f368 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/sleep.asl @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + +#if CONFIG(D3COLD_SUPPORT) + /* Bring system out of TC cold before enter Sx */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () +#endif +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) + + If (CondRefOf (\_SB.PCI0.TXHC)) { + \_SB.TCWK (Arg0) + } +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) +#if CONFIG(D3COLD_SUPPORT) + /* Bring system out of TC cold */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () +#endif + } +} + +/* + * Display Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MSDX, 1, Serialized) +{ + If (CondRefOf (\_SB.PCI0.IMNG)) + { + \_SB.PCI0.IMNG (Arg0) + } +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/touchpad.asl b/src/mainboard/novacustom/mtl-h/acpi/touchpad.asl new file mode 100644 index 00000000000..0ac407185f4 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/touchpad.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External (\_SB.PCI0.I2C0.H038, DeviceObj) +External (\_SB.PCI0.I2C0.H038._STA, IntObj) + +External (\_SB.PCI0.I2C0.H015, DeviceObj) +External (\_SB.PCI0.I2C0.H015._STA, IntObj) + +Method (TPTG, 0, Serialized) +{ + If (CondRefOf (\_SB.PCI0.I2C0.H038)) { + If (\_SB.PCI0.I2C0.H038._STA == Zero) { + \_SB.PCI0.I2C0.H038._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H038._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H038, One) + } + + If (CondRefOf (\_SB.PCI0.I2C0.H015)) { + If (\_SB.PCI0.I2C0.H015._STA == Zero) { + \_SB.PCI0.I2C0.H015._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H015._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H015, One) + } +} diff --git a/src/mainboard/novacustom/mtl-h/board_info.txt b/src/mainboard/novacustom/mtl-h/board_info.txt new file mode 100644 index 00000000000..5220e452c84 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Clevo +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/novacustom/mtl-h/bootblock.c b/src/mainboard/novacustom/mtl-h/bootblock.c new file mode 100644 index 00000000000..7bd8493df5c --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ +}; + +void bootblock_mainboard_early_init(void) +{ + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/cmos.default b/src/mainboard/novacustom/mtl-h/cmos.default new file mode 100644 index 00000000000..972deace70b --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable +kbl_brightness=0xff +kbl_color=0x00ffffff diff --git a/src/mainboard/novacustom/mtl-h/cmos.layout b/src/mainboard/novacustom/mtl-h/cmos.layout new file mode 100644 index 00000000000..fa2067eb9f0 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.layout @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 304 r 0 reserved_memory + +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# Vboot non-volatile data +432 128 r 0 vbnv + +984 16 h 0 check_sum + +# embedded controller settings +1024 8 h 0 kbl_brightness +1032 32 h 0 kbl_color + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 431 984 diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb new file mode 100644 index 00000000000..02741383556 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/devicetree.cb @@ -0,0 +1,271 @@ +chip soc/intel/meteorlake + # Common SoC configuration + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable S0ix / Modern Standby + register "s0ix_enable" = "1" + + # SaGv configuration + register "sagv" = "SAGV_ENABLED" + + # Enable Energy Reporting + register "pch_pm_energy_report_enable" = "1" + + # Thermal + register "tcc_offset" = "30" # TCC of 80C + + device cpu_cluster 0 on end + device domain 0 on + device ref system_agent on end + device ref igpu on + register "ddi_port_A_config" = "1" + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref dtt on end + device ref pcie_rp10 on # M.2 2280 #2 + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D01)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + register "srcclk_pin" = "8" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device ref pcie_rp11 on # M.2 2280 #1 + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D05)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "srcclk_pin" = "7" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref tbt_pcie_rp0 on end + device ref gna on end + device ref crashlog on end + device ref vpu on end + device ref tcss_xhci on + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # Bits (4,5) allocated for TCSS Port3 configuration and Bits (6,7)for TCSS Port4. + # Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0x00" + + register "tcss_ports" = "{ + [0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */ + [1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */ + }" + + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))" + register "usb_lpm_incapable" = "true" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + register "usb_lpm_incapable" = "true" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + end + device ref ioe_shared_sram on end + device ref xhci on + register "usb2_wake_enable_bitmap" = "0x27" + register "usb3_wake_enable_bitmap" = "0x3" + + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB Type-A Port 2 (Right) */ + [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */ + [6] = USB2_PORT_LONG(OC_SKIP), /* Integrated Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth on M.2 2230 */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */ + }" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Left"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Left"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port2 on end + end + end + end + end + device ref pmc_shared_sram on end + device ref cnvi_wifi on + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c1 on # USB-PD EEPROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c3 on # Pantone ROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + device ref pcie_rp6 on # SD Card Reader + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end + device ref pcie_rp8 on # M.2 2230 + register "pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_09" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref uart0 on # BIOS Debug Port + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci" + end + device ref soc_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0e01" # AP/EC command + register "gen3_dec" = "0x00fc0f01" # AP/EC debug + chip drivers/pc80/tpm # SLB 9672 TPM 2.0 + device pnp 0c31.0 on end + end + end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_V" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_S" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # USB Type-C Port 1 (TBT) + use usb2_port6 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + subsystemid 0x1558 0xa763 + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + + end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end + end +end diff --git a/src/mainboard/novacustom/mtl-h/dsdt.asl b/src/mainboard/novacustom/mtl-h/dsdt.asl new file mode 100644 index 00000000000..b12077ebc8d --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/dsdt.asl @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + #include + } + + /* Chipset specific sleep states */ + #include + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" + #include "acpi/touchpad.asl" + +#if CONFIG(INCLUDE_NVIDIA_GPU_ASL) + #include "acpi/dgpu/gpu_top.asl" +#endif +} diff --git a/src/mainboard/novacustom/mtl-h/fadt.c b/src/mainboard/novacustom/mtl-h/fadt.c new file mode 100644 index 00000000000..f983717e096 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/fadt.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h new file mode 100644 index 00000000000..db1dd7dfe5a --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h b/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h new file mode 100644 index 00000000000..50935c8b99c --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_VARIANTS_H +#define MAINBOARD_VARIANTS_H + +void variant_devtree_update(void); +void variant_final(void); + +#endif diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c new file mode 100644 index 00000000000..bb9d5625968 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -0,0 +1,285 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct smfi_cmd_set_fan_curve { + uint8_t fan; + struct fan_curve curve; +} __packed; + +struct fan_curve fan_curve_silent = { + { .temp = 0, .duty = 20 }, + { .temp = 65, .duty = 25 }, + { .temp = 75, .duty = 35 }, + { .temp = 85, .duty = 100 } +}; + +struct fan_curve fan_curve_performance = { + { .temp = 0, .duty = 25 }, + { .temp = 55, .duty = 35 }, + { .temp = 75, .duty = 60 }, + { .temp = 85, .duty = 100} +}; + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +static void set_fan_curve(void) +{ + int i; + uint8_t selection = get_fan_curve_option(); + struct smfi_cmd_set_fan_curve cmd; + + switch (selection) { + case FAN_CURVE_OPTION_PERFORMANCE: + cmd.curve = fan_curve_performance; + break; + case FAN_CURVE_OPTION_SILENT: + default: + cmd.curve = fan_curve_silent; + break; + } + + for (i = 0; i < (CONFIG(EC_DASHARO_EC_DGPU) ? 2 : 1); ++i) { + cmd.fan = i; + dasharo_ec_smfi_cmd(CMD_FAN_CURVE_SET, sizeof(cmd), (uint8_t *)&cmd); + } +} + +static void set_camera_enablement(void) +{ + bool enabled = get_camera_option(); + + dasharo_ec_smfi_cmd(CMD_CAMERA_ENABLEMENT_SET, sizeof(enabled), (uint8_t *)&enabled); +} + +static void set_battery_thresholds(void) +{ + struct battery_config bat_cfg; + + get_battery_config(&bat_cfg); + + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_START, bat_cfg.start_threshold); + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_STOP, bat_cfg.stop_threshold); +} + +static void set_power_on_ac(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_POWER_ON_AC, + 0 + }; + + cmd.value = dasharo_get_power_on_after_fail(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd), (uint8_t *)&cmd); +} + +static void set_usb_charge_port(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_ALWAYS_ON_USB, + 0 + }; + + cmd.value = dasharo_get_usb_port_power(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + +static void mainboard_init(void *chip_info) +{ + config_t *cfg = config_of_soc(); + struct device *wlan_dev = pcidev_on_root(0x1c, 7); + struct device *cnvi_dev = pcidev_on_root(0x14, 3); + bool radio_enable = get_wireless_option(); + + printk(BIOS_DEBUG, "Wireless is %sabled\n", radio_enable ? "en" : "dis"); + + wlan_dev->enabled = radio_enable; + cnvi_dev->enabled = radio_enable; + cfg->cnvi_bt_core = radio_enable; + cfg->cnvi_bt_audio_offload = radio_enable; + cfg->cnvi_wifi_core = radio_enable; + cfg->usb2_ports[9].enable = radio_enable; + + dasharo_ec_smfi_cmd(CMD_WIFI_BT_ENABLEMENT_SET, 1, (uint8_t *)&radio_enable); + + set_fan_curve(); + set_camera_enablement(); + set_battery_thresholds(); + set_power_on_ac(); + set_usb_charge_port(); + + variant_devtree_update(); +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static uint8_t read_proprietary_ec_version(uint8_t *data) +{ + int i, result; + char ec_version[16]; + + if (!data) + return -1; + + if (send_ec_command(0x93)) + return -1; + + for (i = 0; i < 16 - 1; i++) { + + result = recv_ec_data(); + if (result != -1) + ec_version[i] = result & 0xff; + + if (ec_version[i] == '$') { + ec_version[i] = '\0'; + break; + } + } + ec_version[15] = '\0'; + + data[0] = '1'; + data[1] = '.'; + + strcpy((char *)&data[2], ec_version); + + return 0; +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ec_version[256]; + uint8_t result; + + result = dasharo_ec_read_version((uint8_t *)ec_version); + + /* If the command fails it mean we are running proprietary EC most likely */ + if (result != 0) { + printk(BIOS_ERR, "Failed to read open EC firmware version\n"); + result = read_proprietary_ec_version((uint8_t *)ec_version); + if (result == 0) + t->count = smbios_add_string(t->eos, "EC: proprietary"); + else + t->count = smbios_add_string(t->eos, "EC: unknown"); + } else { + t->count = smbios_add_string(t->eos, "EC: open-source"); + } + + if (result == 0) { + printk(BIOS_DEBUG, "EC firmware version: %s\n", ec_version); + t->count = smbios_add_string(t->eos, strconcat("EC firmware version: ", + ec_version)); + } else { + printk(BIOS_ERR, "Unable to probe EC firmware version\n"); + t->count = smbios_add_string(t->eos, "EC firmware version: unknown"); + } + +} +#endif + + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_strings = mainboard_smbios_strings; +#endif +} + +void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3) + config->s0ix_enable = 0; + else + config->s0ix_enable = 1; +} + +void __weak variant_final(void) +{ + +} + +static void mainboard_final(void *chip_info) +{ + variant_final(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, + .final = mainboard_final, +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + // Pinmux configuration + params->PchSerialIoI2cSdaPinMux[3] = 0x1A45CA06; // GPP_H6 + params->PchSerialIoI2cSclPinMux[3] = 0x1A45AA07; // GPP_H7 + + params->PchSerialIoI2cSdaPinMux[4] = 0x8A44CC0C; // GPP_E12 + params->PchSerialIoI2cSclPinMux[4] = 0x8A44AC0D; // GPP_E13 + + params->PchSerialIoI2cSdaPinMux[5] = 0x8A46CE0D; // GPP_F13 + params->PchSerialIoI2cSclPinMux[5] = 0x8A46AE0C; // GPP_F12 + + params->CnviRfResetPinMux = 0x194CE404; // GPP_F4 + params->CnviClkreqPinMux = 0x394CE605; // GPP_F5 + + /* + * [3:0] MappingPchXhciUsbA (1-based USB2 port numbering) + * [5:4] Reserved + * [6] Orientation - TCSS port uses TX0/RX0 pairs or TX1/RX1 pairs + * [7] Enable + */ + params->EnableTcssCovTypeA[1] = 0x82; + + /* Disable S0i2.x due to wake issues */ + params->PmcLpmS0ixSubStateEnableMask = BIT(0); + + params->LidStatus = dasharo_ec_get_lid_state(); + + params->PortResetMessageEnable[1] = 1; + params->PortResetMessageEnable[5] = 1; + + params->PmcPdEnable = 1; + params->TcCstateLimit = 10; + params->TcNotifyIgd = 1; + params->PsOnEnable = 0; +} diff --git a/src/mainboard/novacustom/mtl-h/romstage.c b/src/mainboard/novacustom/mtl-h/romstage.c new file mode 100644 index 00000000000..45ee2e4ebbb --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/romstage.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const bool half_populated = false; + + static const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR5, + + .rcomp = { + /* Values for MTL-H DDR5 2R */ + .resistor = 100, + + .targets = {70, 30, 25, 25, 25}, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + + .ddr_config = { + .dq_pins_interleaved = false, + } + }; + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + mainboard_configure_gpios(); + mupd->FspmConfig.PrimaryDisplay = 4; + mupd->FspmConfig.RootPortIndex = 11; + + /* The values come from Clevo firmware. */ + mupd->FspmConfig.AcLoadline[0] = 190; + mupd->FspmConfig.AcLoadline[1] = 310; + mupd->FspmConfig.AcLoadline[2] = 490; + mupd->FspmConfig.DcLoadline[0] = 190; + mupd->FspmConfig.DcLoadline[1] = 310; + mupd->FspmConfig.DcLoadline[2] = 490; + + mupd->FspmConfig.MmioSize = 2560; /* 2.5 GiB */ + + memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated); +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt b/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt new file mode 100644 index 00000000000..add19e3e7ff Binary files /dev/null and b/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt differ diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c new file mode 100644 index 00000000000..82d6bd89f18 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c @@ -0,0 +1,284 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group CPU ------- */ + + /* ------- GPIO Group V ------- */ + PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), /* BATLOW# */ + PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), /* ACPRESENT */ + PAD_CFG_GPI_TRIG_OWN(GPP_V02, NATIVE, DEEP, OFF, ACPI), /* GPIO - CPU_LAN_WAKEUP# */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPP_V07, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), /* SUSCLK */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPP_V11, 1, DEEP), /* GPIO - GPIO_LAN_EN */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), /* SLP_LAN# */ + PAD_CFG_GPO(GPP_V13, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* WAKE# */ + PAD_CFG_GPO(GPP_V15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V18, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_C02, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C09, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_DGPU_PWRGD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TBT_LSX0_RXD */ + PAD_CFG_GPO(GPP_C18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_CFG_GPO(GPP_A07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A09, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), /* GPIO - ADDS_CODE */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), /* GPIO - WLAN_WAKEUP# */ + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), /* GPIO - M2_SSD2_RST# */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, UP_20K, DEEP, OFF, ACPI), /* GPIO - NVVDD_ALERT# */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), /* GPIO - CPU_SWI# */ + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), /* RSVD - ESPI_ALERT0# */ + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), /* GPIO - TP_ATTN# */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), /* GPIO - TEST_R (ANX7411) */ + PAD_CFG_GPI_APIC(GPP_A19, NONE, DEEP, LEVEL, NONE), /* GPIO - INTP_OUT (ANX7411) */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), /* GPIO - LAN_PLT_RST# */ + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), /* PMCALERT# */ + PAD_NC(GPP_A22, NATIVE), /* GPIO */ + PAD_NC(GPP_A23, NATIVE), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E00, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID7 */ + PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), /* GPIO - TPM_PIRQ# */ + PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID4 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_CNVI_WAKE# */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E05, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), /* GPIO - CPU_SMI# */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E09, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID6 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), /* I2C4_SDA - ANX7411 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), /* I2C4_SCL - ANX7411 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), /* GPIO - CPU_SCI# */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), /* VRALERT# */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID5 */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), /* GPIO */ + PAD_NC(GPP_E23, NONE), /* GPIO */ + PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H03, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), /* CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H18, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* I2C0_SCL */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* I2C1_SDA */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* I2C1_SCL */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), /* GPIO */ + PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), /* n/a */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), /* MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), /* CNVI_GNSS_PA_BLANKING */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F08, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), /* GPIO - TPM_DET */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID3 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* I2C5_SCL - Smart AMP */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* I2C5_SDA - Smart AMP */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), /* GPIO - GPIO4_GC6_NVVDD_EN */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), /* GPIO - CPU_GC6_FB_EN */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO -CCD_WP# */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), /* GPIO */ + PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), /* GPIO */ + PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_CFG_GPO(GPP_S00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S03, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S05, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S06, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S07, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B03, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B05, 0, DEEP), /* GPIO - CPU_KBCRST# */ + PAD_CFG_GPO(GPP_B06, 1, DEEP), /* GPIO - ROM_I2C_EN */ + PAD_CFG_GPO(GPP_B07, 0, DEEP), /* GPIO - PANTONE_WP# */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPIO - PS8461_SW (DDS for eDP) */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), /* GPIO - DGPU_RST#_PCH */ + PAD_CFG_GPI_SCI(GPP_B10, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV Type-C DP HPD */ + PAD_CFG_GPI_SCI(GPP_B11, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV HDMI HPD */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_GPO(GPP_B14, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPIO - CPU_GPIO_LANRTD3 */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), /* GPIO - PCH_BT_EN */ + PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPIO - WIFI_RF_EN */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* GPIO - TBT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPIO */ + PAD_CFG_TERM_GPO(GPP_B23, 0, DN_20K, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), /* n/a */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D00, 1, DEEP), /* GPIO - SB_BLON */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPIO - SSD2_PWR_EN */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), /* GPIO - M2_SSD1_RST# */ + PAD_CFG_GPO(GPP_D03, 0, DEEP), /* GPIO - CPU_DGPU_PWR_EN */ + PAD_CFG_GPO(GPP_D04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D05, 1, DEEP), /* GPIO - SSD1_PWR_EN */ + PAD_CFG_GPO(GPP_D06, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D09, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO - GPIO_SPK_MUTE */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* SRCCLKREQ6# */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* SRCCLKREQ7# */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SRCCLKREQ8# */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* SRCCLKREQ5# */ + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), /* GPP_BOOTHALT_B */ +}; + +#define DGPU_RST_N GPP_B09 +#define DGPU_PWR_EN GPP_D03 +#define DGPU_PWRGD GPP_C15 +#define DGPU_NVVDD_EN GPP_F16 + +/* Pad configuration was generated automatically using intelp2m utility */ +void mainboard_configure_gpios(void) +{ + bool result; + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + mdelay(50); + if (dasharo_dgpu_state() != 0 && !gpio_get(DGPU_PWRGD)) { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + result = wait_ms(200, gpio_get(DGPU_PWRGD) == 1); + if (result) + gpio_set(DGPU_RST_N, 1); + else + gpio_set(DGPU_PWR_EN, 0); + } else { + gpio_set(DGPU_PWR_EN, 0); + } + printk(BIOS_DEBUG, "DGPU_PWRGD %d\n", gpio_get(DGPU_PWRGD)); + printk(BIOS_DEBUG, "DGPU_RST_N %d\n", gpio_get(DGPU_RST_N)); + printk(BIOS_DEBUG, "DGPU_PWR_EN %d\n", gpio_get(DGPU_PWR_EN)); + printk(BIOS_DEBUG, "DGPU_NVVDD_EN %d\n", gpio_get(DGPU_NVVDD_EN)); + printk(BIOS_DEBUG, "PEG_CLKREQ %d\n", gpio_get(GPP_D18)); + + mdelay(50); +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c new file mode 100644 index 00000000000..376ed9dc5b9 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a741, /* Subsystem ID */ + 30, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558a741), + AZALIA_RESET(1), + + 0x1271C30, 0x1271D01, 0x1271EA6, 0x1271F90, + 0x1371C00, 0x1371D00, 0x1371E00, 0x1371F40, + 0x1871CF0, 0x1871D11, 0x1871E11, 0x1871F41, + 0x1971CF0, 0x1971D11, 0x1971E11, 0x1971F41, + 0x1A71CF0, 0x1A71D11, 0x1A71E11, 0x1A71F41, + 0x1B71CF0, 0x1B71D11, 0x1B71E11, 0x1B71F41, + 0x1D71C2D, 0x1D71D9B, 0x1D71E68, 0x1D71F40, + 0x1E71CF0, 0x1E71D11, 0x1E71E11, 0x1E71F41, + 0x2171C20, 0x2171D10, 0x2171E21, 0x2171F04, + 0x5B50006, 0x5B40011, 0x205001A, 0x204810B, + 0x205004A, 0x2042010, 0x2050038, 0x2044909, + 0x5C50000, 0x5C43D82, 0x5C50000, 0x5C43D82, + 0x5350000, 0x534201A, 0x5350000, 0x534201A, + 0x535001D, 0x5340800, 0x535001E, 0x5340800, + 0x5350003, 0x5341EC4, 0x5350004, 0x5340000, + 0x5450000, 0x5442000, 0x545001D, 0x5440800, + 0x545001E, 0x5440800, 0x5450003, 0x5441EC4, + 0x5450004, 0x5440000, 0x5350000, 0x534A01A, + 0x205003C, 0x204F175, 0x205003C, 0x204F135, + 0x2050040, 0x2048800, 0x5A50001, 0x5A4001F, + 0x2050010, 0x2040020, 0x2050010, 0x2040020, + 0x170500, 0x170500, 0x5A50004, 0x5A40113, + 0x2050008, 0x2046A8C, 0x2050076, 0x204F000, + 0x205000E, 0x20465C0, 0x2050033, 0x2048580, + 0x2050069, 0x204FDA8, 0x2050068, 0x2040000, + 0x2050003, 0x2040002, 0x2050069, 0x2040000, + 0x2050068, 0x2040001, 0x205002E, 0x204290E, + 0x2050010, 0x2040020, 0x2050010, 0x2040020, + + /* Intel Meteor Lake HDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +static const u32 smartamp_verbs[] = { + 0x1471CF0, 0x1471D11, 0x1471E11, 0x1471F41, + 0x1771C10, 0x1771D01, 0x1771E17, 0x1771F90, +}; + +static const u32 no_smartamp_verbs[] = { + 0x1471C10, 0x1471D01, 0x1471E17, 0x1471F90, + 0x1771C11, 0x1771D01, 0x1771E17, 0x1771F90, + 0x205006B, 0x204A390, 0x205006B, 0x204A390, + 0x205006C, 0x2040C9E, 0x205006D, 0x2040C00, +}; + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + if (gpio_get(GPP_E00)) { + printk(BIOS_INFO, "Normal amp detected\n"); + azalia_program_verb_table(base, no_smartamp_verbs, + ARRAY_SIZE(no_smartamp_verbs)); + } else { + printk(BIOS_INFO, "Smart amp detected\n"); + azalia_program_verb_table(base, smartamp_verbs, + ARRAY_SIZE(smartamp_verbs)); + } +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb new file mode 100644 index 00000000000..cd92732225d --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb @@ -0,0 +1,75 @@ +chip soc/intel/meteorlake + # Power limits, + # PsysPL2, PsysPL3, PL4 are configured by EC at runtime + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + .psys_pmax = 180, + }" + + # MTL SOC has additional setting for PsysPmax + register "psys_pmax_watts" = "180" + + device domain 0 on + subsystemid 0x1558 0xa741 inherit + device ref pcie_rp12 on # PEG + register "pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_HOTPLUG, + }" + device pci 00.0 on + subsystemid 0x1558 0xa761 + end + end + device ref igpu on + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */ + }" + end + device ref i2c0 on # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c4 on # ANX7443 USB-C Retimer + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + end + device ref i2c5 on # TAS5825M SmartAmp + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end + end + end + device ref pcie_rp5 on # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_V11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c new file mode 100644 index 00000000000..b1dcfa472a7 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void variant_devtree_update(void) +{ + struct device *i2c_amp_dev = pcidev_on_root(0x19, 1); + if (i2c_amp_dev) { + bool have_smartamp = !gpio_get(GPP_E00); + i2c_amp_dev->enabled = have_smartamp; + } + + struct device *dgpu_dev = pcidev_on_root(0x01, 0); + if (dgpu_dev) { + dgpu_dev->enabled = dasharo_dgpu_state() != IGPU_ONLY; + printk(BIOS_DEBUG, "dgpu_dev->enabled: %d\n", dgpu_dev->enabled); + } +} + +#define REG_DATA 2 + +static void set_dgpu_only(void) +{ + uint8_t initial_option_state = 99; + dasharo_read_option(OPT_GPU_MUX_CTRL, &initial_option_state); + printk(BIOS_DEBUG, "MUX_CTRL_BIOS state in coreboot: %d", initial_option_state); + + /* + * If the MUX_CTRL_BIOS option needs to be changed to match the settings, we need a + * global reset + */ + + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_GPU_MUX_CTRL, + 1 + }; + + if (dasharo_dgpu_state() == DGPU_ONLY) { + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); + if (initial_option_state == 0) { + printk(BIOS_INFO, "dGPU Only mode selected - calling global reset to toggle EC display mux\n"); + do_global_reset(); + } + } else { + cmd.value = 0; + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); + if (initial_option_state == 1) { + printk(BIOS_INFO, "dGPU Only mode disabled - calling global reset to toggle EC display mux\n"); + do_global_reset(); + } + } + + printk(BIOS_DEBUG, "dgpu_state = %d, option_index = %d, option_value = %d; global reset not called \n", dasharo_dgpu_state(), cmd.index, initial_option_state); +} + +void variant_final(void) +{ + struct device *dgpu_rp_dev = pcidev_on_root(0x01, 0); + + if (!dgpu_rp_dev) + return; + + struct device *dgpu_dev = pcidev_path_behind(dgpu_rp_dev->downstream, PCI_DEVFN(0, 0)); + + /* + * The dGPU may fail to come up after changing from iGPU mode to dGPU + * mode. If that happens, we need to kick the platform via global reset. + */ + if (!dgpu_dev && dasharo_dgpu_state() != IGPU_ONLY) { + printk(BIOS_DEBUG, "dGPU did not come up! Kicking the platform to work around it\n"); + do_global_reset(); + } else { + printk(BIOS_DEBUG, "dGPU is up.\n"); + } + + set_dgpu_only(); + +} + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + switch (dimm->ctrlr_num) { + case 0: + t->device_locator = smbios_add_string(t->eos, "RAM1"); + break; + case 1: + t->device_locator = smbios_add_string(t->eos, "RAM2"); + break; + default: + t->device_locator = smbios_add_string(t->eos, "UNKNOWN"); + break; + } +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c new file mode 100644 index 00000000000..5e95c4b13cd --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c @@ -0,0 +1,2396 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * This code was auto-generated using extract.rs from + * https://github.com/system76/smart-amp + */ + +int tas5825m_setup(struct device *dev, int id) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + mdelay(5); + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xFE, 0x16, 0xD5, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x90, 0xB5, 0x11, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF6, 0x71, 0xFB, 0xF0, 0x5E, 0x48, 0xD6, + 0x07, 0xAC, 0xA4, 0x5B, 0x0F, 0xA1, 0xB7, 0x2A, + 0xF8, 0x5C, 0xE9, 0xAA, 0x08, 0x00, 0x00, 0x00, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x4B, 0x87, 0x16, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + 0x08, 0x00, 0x00, 0x00, 0xF1, 0x2E, 0x37, 0x44, + 0x06, 0xE6, 0xAE, 0x6C, 0x0E, 0xD1, 0xC8, 0xBC, + 0xF9, 0x19, 0x51, 0x94, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xB6, 0x0E, + 0xF0, 0x38, 0x93, 0xE5, 0x07, 0xE3, 0xB6, 0x0E, + 0x0F, 0xC7, 0x37, 0xC3, 0xF8, 0x38, 0x5F, 0x8D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xE7, 0xF3, 0x30, 0xF0, 0x30, 0x19, 0xA1, + 0x07, 0xE7, 0xF3, 0x30, 0x0F, 0xCF, 0xB1, 0xEB, + 0xF8, 0x2F, 0xE5, 0x2D, 0x07, 0xEF, 0xD5, 0xCD, + 0xF0, 0x20, 0x54, 0x66, 0x07, 0xEF, 0xD5, 0xCD, + 0x0F, 0xDF, 0x76, 0xF1, 0xF8, 0x20, 0x1F, 0xBE, + 0x07, 0xF8, 0xC3, 0x5E, 0xF0, 0x17, 0xB1, 0xEA, + 0x07, 0xEF, 0xAD, 0x9B, 0x0F, 0xE8, 0x4E, 0x16, + 0xF8, 0x17, 0x8F, 0x07, 0x08, 0x06, 0x13, 0x6A, + 0xF0, 0x0B, 0x9D, 0x15, 0x07, 0xEE, 0x72, 0x7F, + 0x0F, 0xF4, 0x3F, 0x7D, 0xF8, 0x0B, 0x56, 0xA9, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xE3, 0xB6, 0x0E, 0xF0, 0x38, 0x93, 0xE5, + 0x07, 0xE3, 0xB6, 0x0E, 0x0F, 0xC7, 0x37, 0xC3, + 0xF8, 0x38, 0x5F, 0x8D, 0x07, 0xE7, 0xF3, 0x30, + 0xF0, 0x30, 0x19, 0xA1, 0x07, 0xE7, 0xF3, 0x30, + 0x0F, 0xCF, 0xB1, 0xEB, 0xF8, 0x2F, 0xE5, 0x2D, + 0x07, 0xEF, 0xD5, 0xCD, 0xF0, 0x20, 0x54, 0x66, + 0x07, 0xEF, 0xD5, 0xCD, 0x0F, 0xDF, 0x76, 0xF1, + 0xF8, 0x20, 0x1F, 0xBE, 0x07, 0xF8, 0xC3, 0x5E, + 0xF0, 0x17, 0xB1, 0xEA, 0x07, 0xEF, 0xAD, 0x9B, + 0x0F, 0xE8, 0x4E, 0x16, 0xF8, 0x17, 0x8F, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x06, 0x13, 0x6A, 0xF0, 0x0B, 0x9D, 0x15, + 0x07, 0xEE, 0x72, 0x7F, 0x0F, 0xF4, 0x3F, 0x7D, + 0xF8, 0x0B, 0x56, 0xA9, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x82, 0xB3, 0xD2, 0xFF, 0x00, 0xA4, 0x7A, + 0x00, 0x7C, 0xCA, 0xB8, 0x0F, 0xF6, 0xBE, 0xFB, + 0xF8, 0x09, 0x1E, 0x02, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x40); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + mdelay(5); + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xFE, 0x16, 0xD5, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x90, 0xB5, 0x11, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF6, 0x71, 0xFB, 0xF0, 0x5E, 0x48, 0xD6, + 0x07, 0xAC, 0xA4, 0x5B, 0x0F, 0xA1, 0xB7, 0x2A, + 0xF8, 0x5C, 0xE9, 0xAA, 0x08, 0x00, 0x00, 0x00, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x4B, 0x87, 0x16, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + 0x08, 0x00, 0x00, 0x00, 0xF1, 0x2E, 0x37, 0x44, + 0x06, 0xE6, 0xAE, 0x6C, 0x0E, 0xD1, 0xC8, 0xBC, + 0xF9, 0x19, 0x51, 0x94, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xB6, 0x0E, + 0xF0, 0x38, 0x93, 0xE5, 0x07, 0xE3, 0xB6, 0x0E, + 0x0F, 0xC7, 0x37, 0xC3, 0xF8, 0x38, 0x5F, 0x8D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xE7, 0xF3, 0x30, 0xF0, 0x30, 0x19, 0xA1, + 0x07, 0xE7, 0xF3, 0x30, 0x0F, 0xCF, 0xB1, 0xEB, + 0xF8, 0x2F, 0xE5, 0x2D, 0x07, 0xEF, 0xD5, 0xCD, + 0xF0, 0x20, 0x54, 0x66, 0x07, 0xEF, 0xD5, 0xCD, + 0x0F, 0xDF, 0x76, 0xF1, 0xF8, 0x20, 0x1F, 0xBE, + 0x07, 0xF8, 0xC3, 0x5E, 0xF0, 0x17, 0xB1, 0xEA, + 0x07, 0xEF, 0xAD, 0x9B, 0x0F, 0xE8, 0x4E, 0x16, + 0xF8, 0x17, 0x8F, 0x07, 0x08, 0x06, 0x13, 0x6A, + 0xF0, 0x0B, 0x9D, 0x15, 0x07, 0xEE, 0x72, 0x7F, + 0x0F, 0xF4, 0x3F, 0x7D, 0xF8, 0x0B, 0x56, 0xA9, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xE3, 0xB6, 0x0E, 0xF0, 0x38, 0x93, 0xE5, + 0x07, 0xE3, 0xB6, 0x0E, 0x0F, 0xC7, 0x37, 0xC3, + 0xF8, 0x38, 0x5F, 0x8D, 0x07, 0xE7, 0xF3, 0x30, + 0xF0, 0x30, 0x19, 0xA1, 0x07, 0xE7, 0xF3, 0x30, + 0x0F, 0xCF, 0xB1, 0xEB, 0xF8, 0x2F, 0xE5, 0x2D, + 0x07, 0xEF, 0xD5, 0xCD, 0xF0, 0x20, 0x54, 0x66, + 0x07, 0xEF, 0xD5, 0xCD, 0x0F, 0xDF, 0x76, 0xF1, + 0xF8, 0x20, 0x1F, 0xBE, 0x07, 0xF8, 0xC3, 0x5E, + 0xF0, 0x17, 0xB1, 0xEA, 0x07, 0xEF, 0xAD, 0x9B, + 0x0F, 0xE8, 0x4E, 0x16, 0xF8, 0x17, 0x8F, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x06, 0x13, 0x6A, 0xF0, 0x0B, 0x9D, 0x15, + 0x07, 0xEE, 0x72, 0x7F, 0x0F, 0xF4, 0x3F, 0x7D, + 0xF8, 0x0B, 0x56, 0xA9, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x82, 0xB3, 0xD2, 0xFF, 0x00, 0xA4, 0x7A, + 0x00, 0x7C, 0xCA, 0xB8, 0x0F, 0xF6, 0xBE, 0xFB, + 0xF8, 0x09, 0x1E, 0x02, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x40); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + return 0; +} diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt b/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt new file mode 100644 index 00000000000..4151d024a9a Binary files /dev/null and b/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt differ diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c new file mode 100644 index 00000000000..b91b888430d --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c @@ -0,0 +1,671 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group CPU ------- */ + + /* ------- GPIO Group V ------- */ + + /* GPP_V00 - BATLOW# */ + PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), + + /* GPP_V01 - ACPRESENT */ + PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), + + /* GPP_V02 - SOC_WAKE# */ + PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1), + + /* GPP_V03 - PWRBTN# */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), + + /* GPP_V04 - SLP_S3# */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + + /* GPP_V05 - SLP_S4# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + + /* GPP_V06 - SLP_A# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + + /* GPP_V07 - GPIO */ + PAD_CFG_GPO(GPP_V07, 0, DEEP), + + /* GPP_V08 - SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + + /* GPP_V09 - SLP_WLAN# */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + + /* GPP_V10 - SLP_S5# */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + + /* GPP_V11 - LANPHYPC */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + + /* GPP_V12 - SLP_LAN# */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + + /* GPP_V13 - GPIO */ + PAD_CFG_GPO(GPP_V13, 0, DEEP), + + /* GPP_V14 - WAKE# */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + + /* GPP_V15 - GPIO */ + PAD_CFG_GPO(GPP_V15, 0, DEEP), + + /* GPP_V16 - GPIO */ + PAD_CFG_GPO(GPP_V16, 0, DEEP), + + /* GPP_V17 - GPIO */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), + + /* GPP_V18 - GPIO */ + PAD_CFG_GPO(GPP_V18, 0, DEEP), + + /* GPP_V19 - n/a */ + PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), + + /* GPP_V20 - n/a */ + PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), + + /* GPP_V21 - n/a */ + PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), + + /* GPP_V22 - GPIO */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), + + /* GPP_V23 - GPIO */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C00 - SMBCLK */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), + + /* GPP_C01 - SMBDATA */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), + + /* GPP_C02 - GPIO */ + PAD_CFG_GPO(GPP_C02, 0, DEEP), + + /* GPP_C03 - SML0CLK */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + + /* GPP_C04 - SML0DATA */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + + /* GPP_C05 - GPIO */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + + /* GPP_C06 - SML1CLK */ + PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), + + /* GPP_C07 - SML1DATA */ + PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), + + /* GPP_C08 - GPIO */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), + + /* GPP_C09 - GPIO */ + PAD_CFG_GPO(GPP_C09, 0, DEEP), + + /* GPP_C10 - GPIO */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + + /* GPP_C11 - SRCCLKREQ2# (LAN) */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + + /* GPP_C12 - SRCCLKREQ3# (SDCARD) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + + /* GPP_C13 - GPIO */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + + /* GPP_C14 - GPIO */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + + /* GPP_C15 - GPIO */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + + /* GPP_C16 - TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + + /* GPP_C17 - TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + + /* GPP_C18 - GPIO */ + PAD_CFG_GPO(GPP_C18, 0, DEEP), + + /* GPP_C19 - GPIO */ + PAD_CFG_GPO(GPP_C19, 0, DEEP), + + /* GPP_C20 - DDP2_CTRLCLK */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), + + /* GPP_C21 - DDP2_CTRLDATA */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), + + /* GPP_C22 - GPIO */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* GPP_C23 - GPIO */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A00 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), + + /* GPP_A01 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), + + /* GPP_A02 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), + + /* GPP_A03 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), + + /* GPP_A04 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), + + /* GPP_A05 - ESPI_CLK */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), + + /* GPP_A06 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), + + /* GPP_A07 - GPIO */ + PAD_CFG_GPO(GPP_A07, 0, DEEP), + + /* GPP_A08 - GPIO */ + PAD_CFG_GPO(GPP_A08, 0, DEEP), + + /* GPP_A09 - GPIO */ + PAD_CFG_GPO(GPP_A09, 0, DEEP), + + /* GPP_A10 - GPIO */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + + /* GPP_A11 - GPIO (ADDS_CODE) */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + + /* GPP_A12 - GPIO (WLAN_WAKEUP#) */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), + + /* GPP_A13 - GPIO (M2_SSD2_RST#) */ + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), + + /* GPP_A14 - GPIO */ + PAD_CFG_GPO(GPP_A14, 0, DEEP), + + /* GPP_A15 - GPIO */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), + + /* GPP_A16 - RSVD/ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), + + /* GPP_A17 - GPIO (TP_ATTN#_A17) */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), + + /* GPP_A18 - GPIO */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), + + /* GPP_A19 - GPIO */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + + /* GPP_A20 - GPIO */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + + /* GPP_A21 - PMCALERT# */ + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), + + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NATIVE), + + /* GPP_A23 - GPIO */ + PAD_NC(GPP_A23, NATIVE), + + /* GPP_ESPI_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_ESPI_CLK_LPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E00 - GPIO */ + PAD_CFG_GPO(GPP_E00, 0, DEEP), + + /* GPP_E01 - GPIO (TPM_PIRQ#) */ + PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), + + /* GPP_E02 - GPIO (BOARD_ID4) */ + PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), + + /* GPP_E03 - GPIO (CNVI_WAKE#) */ + PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), + + /* GPP_E04 - GPIO */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), + + /* GPP_E05 - GPIO */ + PAD_CFG_GPO(GPP_E05, 0, DEEP), + + /* GPP_E06 - GPIO */ + PAD_CFG_GPO(GPP_E06, 0, DEEP), + + /* GPP_E07 - GPIO */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), + + /* GPP_E08 - GPIO */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), + + /* GPP_E09 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E09, NONE, DEEP, OFF, ACPI), + + /* GPP_E10 - GPIO */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + + /* GPP_E11 - GPIO (BOARD_ID6) */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), + + /* GPP_E12 - GPIO */ + PAD_CFG_GPO(GPP_E12, 0, DEEP), + + /* GPP_E13 - GPIO */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), + + /* GPP_E16 - VRALERT# */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), + + /* GPP_E17 - GPIO (BOARD_ID5) */ + PAD_CFG_GPO(GPP_E17, 0, DEEP), + + /* GPP_E18 - GPIO */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), + + /* GPP_E19 - GPIO */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), + + /* GPP_E20 - GPIO */ + PAD_CFG_GPO(GPP_E20, 0, DEEP), + + /* GPP_E21 - GPIO */ + PAD_CFG_GPO(GPP_E21, 0, DEEP), + + /* GPP_E22 - GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), + + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + + /* GPP_THC0_GSPI_CLK_LPBK - GPIO */ + PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H00 - GPIO */ + PAD_CFG_GPO(GPP_H00, 0, DEEP), + + /* GPP_H01 - GPIO */ + PAD_CFG_GPO(GPP_H01, 0, DEEP), + + /* GPP_H02 - GPIO */ + PAD_CFG_GPO(GPP_H02, 0, DEEP), + + /* GPP_H03 - GPIO */ + PAD_CFG_GPO(GPP_H03, 0, DEEP), + + /* GPP_H04 - GPIO (TODO: should be CNV_MFUART2_RXD - NF2) */ + PAD_CFG_GPO(GPP_H04, 0, DEEP), + + /* GPP_H05 - GPIO (TODO: should be CNV_MFUART2_TXD - NF2) */ + PAD_CFG_GPO(GPP_H05, 0, DEEP), + + /* GPP_H06 - I2C3_SDA */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + + /* GPP_H07 - I2C3_SCL */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + + /* GPP_H08 - GPIO */ + PAD_CFG_GPO(GPP_H08, 0, DEEP), + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + + /* GPP_H09 - GPIO */ + PAD_CFG_GPO(GPP_H09, 0, DEEP), + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ + + /* GPP_H10 - GPIO */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), + + /* GPP_H11 - GPIO */ + PAD_CFG_GPO(GPP_H11, 0, DEEP), + + /* GPP_H12 - GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + + /* GPP_H13 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + + /* GPP_H14 - GPIO */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), + + /* GPP_H15 - GPIO */ + PAD_CFG_GPO(GPP_H15, 0, DEEP), + + /* GPP_H16 - GPIO */ + PAD_CFG_GPO(GPP_H16, 0, DEEP), + + /* GPP_H17 - GPIO */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), + + /* GPP_H18 - GPIO */ + PAD_CFG_GPO(GPP_H18, 0, DEEP), + + /* GPP_H19 - I2C0_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + + /* GPP_H20 - I2C0_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + + /* GPP_H21 - I2C1_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + + /* GPP_H22 - I2C1_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* GPP_LPI3C1_CLK_LPBK - GPIO */ + PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), + + /* GPP_LPI3C0_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F00 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + + /* GPP_F01 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + + /* GPP_F02 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + + /* GPP_F03 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + + /* GPP_F04 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), + + /* GPP_F05 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), + + /* GPP_F06 - GPIO (should be CNV_PA_BLANKING - NF1)*/ + PAD_CFG_GPO(GPP_F06, 0, DEEP), + + /* GPP_F07 - GPIO */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), + + /* GPP_F08 - GPIO */ + PAD_CFG_GPO(GPP_F08, 0, DEEP), + + /* GPP_F09 - GPIO (TPM_DET) */ + PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), + + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + + /* GPP_F11 - GPIO (BOARD_ID3) */ + PAD_CFG_GPO(GPP_F11, 0, DEEP), + + /* GPP_F12 - GPIO (I2C5_SCL smart amp) */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, ACPI), + + /* GPP_F13 - GPIO (I2C5_SDA smart amp) */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + + /* GPP_F14 - GPIO (BOARD_ID1) */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), + + /* GPP_F15 - GPIO (BOARD_ID2) */ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + + /* GPP_F16 - GPIO */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + + /* GPP_F17 - GPIO */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + + /* GPP_F18 - GPIO (CPU_CCD_WP#) */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + + /* GPP_F19 - GPIO */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), + + /* GPP_F20 - GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + + /* GPP_F21 - GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + + /* GPP_F22 - GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), + + /* GPP_F23 - GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), + + /* GPP_THC1_GSPI1_CLK_LPBK - GPIO */ + PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), + + /* GPP_GSPI0A_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S00 - GPIO */ + PAD_CFG_GPO(GPP_S00, 0, DEEP), + + /* GPP_S01 - GPIO */ + PAD_CFG_GPO(GPP_S01, 0, DEEP), + + /* GPP_S02 - GPIO */ + PAD_CFG_GPO(GPP_S02, 0, DEEP), + + /* GPP_S03 - GPIO */ + PAD_CFG_GPO(GPP_S03, 0, DEEP), + + /* GPP_S04 - GPIO */ + PAD_CFG_GPO(GPP_S04, 0, DEEP), + + /* GPP_S05 - GPIO */ + PAD_CFG_GPO(GPP_S05, 0, DEEP), + + /* GPP_S06 - GPIO */ + PAD_CFG_GPO(GPP_S06, 0, DEEP), + + /* GPP_S07 - GPIO */ + PAD_CFG_GPO(GPP_S07, 0, DEEP), + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B00 - GPIO (TP_ATTN#) */ + PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), + + /* GPP_B01 - GPIO */ + PAD_CFG_GPO(GPP_B01, 0, DEEP), + + /* GPP_B02 - GPIO */ + PAD_CFG_GPO(GPP_B02, 0, DEEP), + + /* GPP_B03 - GPIO */ + PAD_CFG_GPO(GPP_B03, 0, DEEP), + + /* GPP_B04 - GPIO */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), + + /* GPP_B05 - GPIO */ + PAD_CFG_GPO(GPP_B05, 0, DEEP), + + /* GPP_B06 - GPIO (ROM_I2C_EN) */ + PAD_CFG_GPO(GPP_B06, 1, DEEP), + + /* GPP_B07 - GPIO */ + PAD_CFG_GPO(GPP_B07, 0, DEEP), + + /* GPP_B08 - GPIO */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), + + /* GPP_B09 - GPIO */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), + + /* GPP_B10 - GPIO */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), + + /* GPP_B11 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B14, NONE, DEEP, OFF, ACPI), + + /* GPP_B15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), + + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), + + /* GPP_B17 - GPIO */ + PAD_CFG_GPO(GPP_B17, 0, DEEP), + + /* GPP_B18 - GPIO (PCH_BT_EN) */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), + + /* GPP_B19 - GPIO (WIFI_RF_EN) */ + PAD_CFG_GPO(GPP_B19, 1, DEEP), + + /* GPP_B20 - GPIO */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), + + /* GPP_B21 - GPIO (TCP_RETIMER_FORCE_PWR) */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + + /* GPP_B22 - GPIO */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* GPP_ACI3C0_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D00 - GPIO (SB_BLON) */ + PAD_CFG_GPO(GPP_D00, 1, DEEP), + + /* GPP_D01 - GPIO (SSD2_PWR_EN) */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + + /* GPP_D02 - GPIO (M2_SSD1_RST#) */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), + + /* GPP_D03 - GPIO */ + PAD_CFG_GPO(GPP_D03, 0, DEEP), + + /* GPP_D04 - GPIO */ + PAD_CFG_GPO(GPP_D04, 0, DEEP), + + /* GPP_D05 - GPIO (SSD1_PWR_EN) */ + PAD_CFG_GPO(GPP_D05, 1, DEEP), + + /* GPP_D06 - GPIO */ + PAD_CFG_GPO(GPP_D06, 0, DEEP), + + /* GPP_D07 - GPIO */ + PAD_CFG_GPO(GPP_D07, 0, DEEP), + + /* GPP_D08 - GPIO */ + PAD_CFG_GPO(GPP_D08, 0, DEEP), + + /* GPP_D09 - GPIO */ + PAD_CFG_GPO(GPP_D09, 0, DEEP), + + /* GPP_D10 - HDA_BCLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + + /* GPP_D11 - HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + + /* GPP_D12 - HDA_SDO */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + + /* GPP_D13 - HDA_SDI0 */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), + + /* GPP_D15 - GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + + /* GPP_D16 - GPIO (GPIO_SPK_MUTE) */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), + + /* GPP_D17 - HDA_RST# */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + + /* GPP_D18 - SRCCLKREQ6# (NC?) */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* GPP_D19 - SRCCLKREQ7# (SSD1) */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* GPP_D20 - SRCCLKREQ8# (SSD2) */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* GPP_D21 - SRCCLKREQ5# (WLAN) */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), + + /* GPP_D22 - n/a */ + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), + + /* GPP_D23 - n/a */ + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), + + /* GPP_BOOTHALT_B - n/a */ + PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c b/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c new file mode 100644 index 00000000000..b94a1947376 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a763, /* Subsystem ID */ + 40, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558a763), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + 0x5B50006, 0x5B40011, 0x205001A, 0x204810B, + 0x205004A, 0x2042010, 0x2050038, 0x2047909, + 0x5C50000, 0x5C43D82, 0x5C50000, 0x5C43D82, + 0x5350000, 0x534201A, 0x5350000, 0x534201A, + 0x535001D, 0x5340800, 0x535001E, 0x5340800, + 0x5350003, 0x5341EC4, 0x5350004, 0x5340000, + 0x5450000, 0x5442000, 0x545001D, 0x5440800, + 0x545001E, 0x5440800, 0x5450003, 0x5441EC4, + 0x5450004, 0x5440000, 0x5350000, 0x534A01A, + 0x205003C, 0x204F175, 0x205003C, 0x204F135, + 0x2050040, 0x2048800, 0x5A50001, 0x5A4001F, + 0x2050010, 0x2040020, 0x2050010, 0x2040020, + 0x205006B, 0x204A390, 0x205006B, 0x204A390, + 0x205006C, 0x2040C9E, 0x205006D, 0x2040C00, + 0x170500, 0x170500, 0x5A50004, 0x5A40113, + 0x2050008, 0x2046A8C, 0x2050076, 0x204F000, + 0x205000E, 0x20465C0, 0x2050033, 0x2048580, + 0x2050069, 0x204FDA8, 0x2050068, 0x2040000, + 0x2050003, 0x2040002, 0x2050069, 0x2040000, + 0x2050068, 0x2040001, 0x205002E, 0x204290E, + 0x2236100, 0x2235100, 0x920011, 0x970610, + 0x936000, 0x935000, 0x205000D, 0x204A020, + 0x220011, 0x270610, 0x23A046, 0x239046, + 0x173B000, 0x1770740, 0x5A50001, 0x5A4001F, + 0x5C5000F, 0x5C40003, 0x2050036, 0x20437D7, + 0x143B000, 0x1470740, 0x2050010, 0x2040020, + 0x1470C02, 0x1470C02, 0x1470C02, 0x1470C02, + + /* Intel Meteor Lake HDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb new file mode 100644 index 00000000000..d668c7c79c6 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb @@ -0,0 +1,51 @@ +chip soc/intel/meteorlake + # Power limits, + # PsysPL2, PsysPL3, PL4 are configured by EC at runtime + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 64, + .tdp_pl4 = 90, + .psys_pmax = 99, + }" + + # MTL SOC has additional setting for PsysPmax + register "psys_pmax_watts" = "99" + + device domain 0 on + subsystemid 0x1558 0xa743 inherit + device ref igpu on + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */ + [DDI_PORT_3] = DDI_ENABLE_DDC | DDI_ENABLE_HPD, /* HDMI 2.1 */ + }" + end + device ref i2c0 on # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref pcie_rp5 on # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR, + }" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN" + end + device ref gbe on end + end +end diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c b/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c new file mode 100644 index 00000000000..36856a902a0 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + switch (dimm->ctrlr_num) { + case 0: + t->device_locator = smbios_add_string(t->eos, "RAM2"); + break; + case 1: + t->device_locator = smbios_add_string(t->eos, "RAM1"); + break; + default: + t->device_locator = smbios_add_string(t->eos, "UNKNOWN"); + break; + } +} diff --git a/src/mainboard/novacustom/mtl-h/vboot-rwa.fmd b/src/mainboard/novacustom/mtl-h/vboot-rwa.fmd new file mode 100644 index 00000000000..e12944237e1 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/vboot-rwa.fmd @@ -0,0 +1,48 @@ +FLASH 32M { + SI_ALL 10M { + SI_DESC 16K +#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION + SI_GBE 8K +#endif + SI_ME + } + RW_UNUSED 6M + + SI_BIOS { + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M + } + + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + + WP_RO 7M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd new file mode 100644 index 00000000000..d785dffb4c9 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd @@ -0,0 +1,53 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K +#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION + SI_GBE 8K +#endif + SI_ME + } + SI_BIOS { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M + } + + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + + WP_RO 7M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 0x100 + RO_FRID_PAD 0xf00 + GBB 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/novacustom/nuc_box/Kconfig b/src/mainboard/novacustom/nuc_box/Kconfig new file mode 100644 index 00000000000..83b63e8cbb9 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/Kconfig @@ -0,0 +1,105 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_NOVACUSTOM_NUC_BOX_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select CRB_TPM + select DRIVERS_GENERIC_CBFS_SERIAL + select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_INTEL_PTT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select PCIEXP_SUPPORT_RESIZABLE_BARS + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_METEORLAKE + select SPD_READ_BY_WORD + +config BOARD_NOVACUSTOM_NUC_BOX + select BOARD_NOVACUSTOM_NUC_BOX_COMMON + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + +if BOARD_NOVACUSTOM_NUC_BOX_COMMON + +config MAINBOARD_DIR + default "novacustom/nuc_box" + +config VARIANT_DIR + default "nuc_box" if BOARD_NOVACUSTOM_NUC_BOX + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + default "NUC BOX" if BOARD_NOVACUSTOM_NUC_BOX + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "NUC_BOX" if BOARD_NOVACUSTOM_NUC_BOX + +config MAINBOARD_VERSION + default "nuc_box" if BOARD_NOVACUSTOM_NUC_BOX + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match Insyde firmware + +config CMOS_DEFAULT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" + +config CONSOLE_POST + default y + +config D3COLD_SUPPORT + default n + +config DIMM_SPD_SIZE + default 1024 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" + +config ONBOARD_VGA_IS_PRIMARY + default y + +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + default 36 + +config POST_DEVICE + default n + +config TPM_MEASURED_BOOT + default y + +config UART_FOR_CONSOLE + default 0 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_NO_TPM + +config VBOOT_VBNV_OFFSET + default 0x28 + +config VBOOT_FWID_VERSION + default "\$(CONFIG_LOCALVERSION)" + +endif diff --git a/src/mainboard/novacustom/nuc_box/Kconfig.name b/src/mainboard/novacustom/nuc_box/Kconfig.name new file mode 100644 index 00000000000..622332715d1 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_NOVACUSTOM_NUC_BOX + bool "nuc_box" diff --git a/src/mainboard/novacustom/nuc_box/Makefile.mk b/src/mainboard/novacustom/nuc_box/Makefile.mk new file mode 100644 index 00000000000..da65009f458 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/Makefile.mk @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c diff --git a/src/mainboard/novacustom/nuc_box/acpi/mainboard.asl b/src/mainboard/novacustom/nuc_box/acpi/mainboard.asl new file mode 100644 index 00000000000..b7ee9d139cb --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/acpi/mainboard.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "sio.asl" + #include "sleep.asl" +} diff --git a/src/mainboard/novacustom/nuc_box/acpi/sio.asl b/src/mainboard/novacustom/nuc_box/acpi/sio.asl new file mode 100644 index 00000000000..4f91a837120 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/acpi/sio.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (SIO) { + Name (_ADR, 0x2E) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) + Field (SIOA, ByteAcc, NoLock, Preserve) + { + SI2E, 8, + SI2F, 8, + } + IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset(0xE5), + SRE5, 8, /* Register 0xE5 */ + } + + Method (ENTR, 0, Serialized) { + // Enter config mode + SI2E = 0x87 + SI2E = 0x87 + } + + Method (EXIT, 0, Serialized) { + // Exit config mode + SI2E = 0xAA + } + + Method (PTS, 0, Serialized) { + ENTR() + + // Turn on fading LED + SLDN = 0x15 + SRE5 = 0x43 + + EXIT() + } + + Method (WAK, 0, Serialized) { + ENTR() + + // Turn off fading LED + SLDN = 0x15 + SRE5 = 0x42 + + EXIT() + } +} diff --git a/src/mainboard/novacustom/nuc_box/acpi/sleep.asl b/src/mainboard/novacustom/nuc_box/acpi/sleep.asl new file mode 100644 index 00000000000..0212e7aeeb8 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.SIO.PTS() +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.SIO.WAK() +} diff --git a/src/mainboard/novacustom/nuc_box/board_info.txt b/src/mainboard/novacustom/nuc_box/board_info.txt new file mode 100644 index 00000000000..9aeb8f5ff6b --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: NovaCustom +Category: desktop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/novacustom/nuc_box/bootblock.c b/src/mainboard/novacustom/nuc_box/bootblock.c new file mode 100644 index 00000000000..ca7367297fa --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/bootblock.c @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +// nuvoton_pnp_enter_conf_state +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +// nuvoton_pnp_exit_conf_state +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void superio_init(void) +{ + //TODO: use superio driver? + pnp_devfn_t dev = PNP_DEV(0x2E, 0x00); + + printk(BIOS_DEBUG, "entering PNP config mode\n"); + pnp_enter_conf_state(dev); + + printk(BIOS_DEBUG, "configure global PNP\n"); + //TODO: document these + pnp_write_config(dev, 0x1A, 0x88); // Default is 0x03 + pnp_write_config(dev, 0x1B, 0x00); // Default is 0x03 + pnp_write_config(dev, 0x1D, 0x08); // Default is 0x00 + pnp_write_config(dev, 0x2C, 0x03); // Default is 0x0F + pnp_write_config(dev, 0x2F, 0xE4); // Default is 0x74 + + printk(BIOS_DEBUG, "configure GPIO (logical device 7)\n"); + dev = PNP_DEV(0x2E, 0x07); + pnp_set_logical_device(dev); + // Enable GPIO 0, 5, and 6 + pnp_write_config(dev, 0x30, 0x61); // Default is 0x00 + // Set GPIO 00-06 as output, 07 as input + pnp_write_config(dev, 0xE0, 0x80); // Default is 0xFF + // Set GPIO 00-02 and 04-05 high + pnp_write_config(dev, 0xE1, 0x37); // Default is 0x00 + // Set GPIO 53-54 as output, 50-52 and 55-57 as input + pnp_write_config(dev, 0xF8, 0xE7); // Default is 0xFF + // Set GPIO 53-53 high + pnp_write_config(dev, 0xF9, 0x18); // Default is 0x00 + + printk(BIOS_DEBUG, "configure GPIO (logical device 8)\n"); + dev = PNP_DEV(0x2E, 0x08); + pnp_set_logical_device(dev); + // Disable WDT1 + pnp_write_config(dev, 0x30, 0x00); // Default is 0x01 + // GPIO0 multi-function select, set GPIO0 as SUSLED + pnp_write_config(dev, 0xE0, 0x01); // Default is 0x00 + pnp_write_config(dev, 0xE9, 0x00); // Default is 0xFF TODO? + pnp_write_config(dev, 0xEA, 0x00); // Default is 0xFF TODO? + + printk(BIOS_DEBUG, "configure GPIO (logical device 9)\n"); + dev = PNP_DEV(0x2E, 0x09); + pnp_set_logical_device(dev); + // Enable GPIO 8 and 9 + pnp_write_config(dev, 0x30, 0x03); // Default is 0x00 + // GPIO 80-86 set as input, 87 as output + pnp_write_config(dev, 0xF0, 0x7F); // Default is 0xFF + // GPIO 87 set high + pnp_write_config(dev, 0xF1, 0x80); // Default is 0xFF + + printk(BIOS_DEBUG, "configure ACPI (logical device A)\n"); + dev = PNP_DEV(0x2E, 0x0A); + pnp_set_logical_device(dev); + // User-defined resume state after power loss + pnp_write_config(dev, 0xE4, 0x60); // Default is 0x00 + + // Set the user-defined resume state based on the Dasharo option + u8 cre6 = pnp_read_config(dev, 0xE6); + if (dasharo_get_power_on_after_fail()) { + cre6 &= ~(1 << 4); + } else { + cre6 |= (1 << 4); + } + pnp_write_config(dev, 0xE6, cre6); + + printk(BIOS_DEBUG, "configure hardware monitor (logical device B)\n"); + dev = PNP_DEV(0x2E, 0x0B); + pnp_set_logical_device(dev); + // Enable hardware monitor + pnp_write_config(dev, 0x30, 0x01); // Default is 0x00 + // Set address base to 0x290 + pnp_write_config(dev, 0x60, 0x02); + pnp_write_config(dev, 0x61, 0x90); + + printk(BIOS_DEBUG, "configure GPIO (logical device F)\n"); + dev = PNP_DEV(0x2E, 0x0F); + pnp_set_logical_device(dev); + // Set GPIO 00, 01, and 07 as open drain, and 2-6 as push-pull + pnp_write_config(dev, 0xE0, 0x83); // Default is 0xFF + // Set GPIO 52-57 as open drain, and 50-51 as push-pull + pnp_write_config(dev, 0xE5, 0xFC); // Default is 0xFF + // Set GPIO 60-62 and 65-67 as open drain, and 63-64 as push-pull + pnp_write_config(dev, 0xE6, 0xE7); // Default is 0xFF + // Set GPIO 80-86 as open drain, and 87 as push-pull + pnp_write_config(dev, 0xE8, 0x7F); // Default is 0xFF + + printk(BIOS_DEBUG, "configure fading LED (logical device 15)\n"); + dev = PNP_DEV(0x2E, 0x15); + pnp_set_logical_device(dev); + // Configure fading LED (divide by 4, frequency 1 Khz, off) + pnp_write_config(dev, 0xE5, 0x42); + + printk(BIOS_DEBUG, "configure deep sleep (logical device 16)\n"); + dev = PNP_DEV(0x2E, 0x16); + pnp_set_logical_device(dev); + // Set deep sleep delay time to 0s + pnp_write_config(dev, 0xE2, 0x00); + + printk(BIOS_DEBUG, "exiting PNP config mode\n"); + pnp_exit_conf_state(dev); +} + +static void hm_write(uint8_t reg, uint8_t value) +{ + outb(reg, 0x295); + outb(value, 0x296); +} + +static void hm_init(uint8_t fan_curve) +{ + // --- Generic setup --- + // Bank 2: PECI settings + hm_write(0x4E, 0x82); + hm_write(0x00, 0x85); // Enable PECI 3.0 + hm_write(0x02, 0x10); // Enable PECI agent 30 + hm_write(0x04, 110); // Tbase0 = 110C + + // Bank 3: PECI agent mode + hm_write(0x4E, 0x83); + hm_write(0x90, 0x01); // Enable PECI agent 0 + + // Bank 1: Smart FAN IV setup + hm_write(0x4E, 0x81); + + // CPUFAN: Enable Smart Fan IV mode + hm_write(0x23, 0x40); // Mode select: Smart FAN IV + + // Set PECI agent 0 as CPUFAN temperature source + hm_write(0x20, 0x0C); // Source = PECI agent 0 + + // Set fan ramp timings + hm_write(0x24, 10); // Step up = 1s + hm_write(0x25, 5); // Step down = 0.5s + + // Set critical temperature + hm_write(0x2A, 105); // Trip point to force 100% duty + + // --- Curve-specific thresholds --- + switch (fan_curve) { + case FAN_CURVE_OPTION_OFF: + // Fan off curve (only reacts at critical temp) + hm_write(0x70, 90); hm_write(0x74, 0x00); // T1 + hm_write(0x71, 95); hm_write(0x75, 0x00); // T2 + hm_write(0x72,100); hm_write(0x76, 0x00); // T3 + hm_write(0x73,105); hm_write(0x77, 0x00); // T4 + break; + + case FAN_CURVE_OPTION_PERFORMANCE: + // Aggressive response + hm_write(0x70, 40); hm_write(0x74, 0x40); // 25% + hm_write(0x71, 60); hm_write(0x75, 0x80); // 50% + hm_write(0x72, 75); hm_write(0x76, 0xC0); // 75% + hm_write(0x73, 85); hm_write(0x77, 0xFF); // 100% + break; + + case FAN_CURVE_OPTION_SILENT: + default: + // Quiet, conservative curve + hm_write(0x70, 60); hm_write(0x74, 0x2A); // ~16% + hm_write(0x71, 75); hm_write(0x75, 0x50); // ~31% + hm_write(0x72, 85); hm_write(0x76, 0x80); // ~50% + hm_write(0x73, 95); hm_write(0x77, 0xC0); // ~75% + break; + } +} + +void bootblock_mainboard_early_init(void) +{ + uint8_t fan_curve = get_fan_curve_option(); + mainboard_configure_early_gpios(); + mainboard_configure_gpios(); + superio_init(); + hm_init(fan_curve); +} diff --git a/src/mainboard/novacustom/nuc_box/cmos.default b/src/mainboard/novacustom/nuc_box/cmos.default new file mode 100644 index 00000000000..d2ca53be53c --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/cmos.default @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +me_state=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/novacustom/nuc_box/cmos.layout b/src/mainboard/novacustom/nuc_box/cmos.layout new file mode 100644 index 00000000000..a27267dd926 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/cmos.layout @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +# TODO: Use enum 7 to allow `Keep` +409 2 e 1 power_on_after_fail +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# Vboot non-volatile data +432 128 r 0 vbnv + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + +984 16 h 0 check_sum + +enumerations + +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +7 0 Disable +7 1 Enable +7 2 Keep + +checksums + +checksum 408 431 984 diff --git a/src/mainboard/novacustom/nuc_box/devicetree.cb b/src/mainboard/novacustom/nuc_box/devicetree.cb new file mode 100644 index 00000000000..392c9c50f2a --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/devicetree.cb @@ -0,0 +1,61 @@ +chip soc/intel/meteorlake + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Thermal + register "tcc_offset" = "11" # 110C - 11C = 99C + + device cpu_cluster 0 on end + + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 40, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + }" + + device domain 0 on + device ref system_agent on end + device ref igpu on + # DDIA is HDMI1, DDIB is HDMI2 + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + device ref vpu on end + device ref ioe_shared_sram on end + device ref pmc_shared_sram on end + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + + device ref heci1 on end + device ref soc_espi on + register "gen1_dec" = "0x007c0281" # Port 0x280 to 0x2FF (hardware monitor) + register "gen2_dec" = "0x000c0081" # Port 0x80 to 0x8F (debug) + end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_E" + register "pmc_gpe0_dw2" = "PMC_GPP_H" + end + device ref p2sb hidden end + device ref hda on + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + device ref fast_spi on end + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/novacustom/nuc_box/dsdt.asl b/src/mainboard/novacustom/nuc_box/dsdt.asl new file mode 100644 index 00000000000..cf8d58d4345 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS +#include + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } + + #include + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/novacustom/nuc_box/include/mainboard/gpio.h b/src/mainboard/novacustom/nuc_box/include/mainboard/gpio.h new file mode 100644 index 00000000000..c6393beebb6 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/novacustom/nuc_box/ramstage.c b/src/mainboard/novacustom/nuc_box/ramstage.c new file mode 100644 index 00000000000..b83d622455a --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/ramstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void mainboard_init(void *chip_info) +{ + // The DACC feature resets CMOS if the firmware does not send this message + printk(BIOS_DEBUG, "Handling DACC\n"); + do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE, 0xBA >> 1, 0x0F, 0xAA); +} + +void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3) + config->s0ix_enable = 0; + else + config->s0ix_enable = 1; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/board.fmd b/src/mainboard/novacustom/nuc_box/variants/nuc_box/board.fmd new file mode 100644 index 00000000000..847cbcdfb37 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/variants/nuc_box/board.fmd @@ -0,0 +1,46 @@ +FLASH 32M { + SI_ALL 16M { + SI_DESC 0x4000 # 16K +#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION + SI_GBE 0x1000 # 4K (overlaps with PD) +#endif + SI_ME 0x009ec000 # 10,137,600 bytes = matches IFD exactly + } + + SI_BIOS@0x01000000 16M { + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + + CONSOLE(PRESERVE) 128K # <== SPI flash console region here + + BOOTSPLASH(CBFS) 1M + } + + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + + WP_RO 7M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/board_info.txt b/src/mainboard/novacustom/nuc_box/variants/nuc_box/board_info.txt new file mode 100644 index 00000000000..55abda68a78 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/variants/nuc_box/board_info.txt @@ -0,0 +1,2 @@ +Board name: nuc_box +Release year: 2024 diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/data.vbt b/src/mainboard/novacustom/nuc_box/variants/nuc_box/data.vbt new file mode 100644 index 00000000000..64207eb3e25 Binary files /dev/null and b/src/mainboard/novacustom/nuc_box/variants/nuc_box/data.vbt differ diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/gpio.c b/src/mainboard/novacustom/nuc_box/variants/nuc_box/gpio.c new file mode 100644 index 00000000000..c7fc1810b78 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/variants/nuc_box/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3 + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS0# + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A07, NONE), + PAD_NC(GPP_A08, NONE), + PAD_NC(GPP_A09, NONE), + PAD_NC(GPP_A10, NONE), + PAD_CFG_GPI(GPP_A11, NONE, PLTRST), + PAD_CFG_GPI(GPP_A12, NONE, PLTRST), + PAD_CFG_GPI(GPP_A13, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_A14, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_A15, NONE, PLTRST), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALERT0# + PAD_CFG_GPI(GPP_A17, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_A18, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_A19, UP_20K, DEEP), + PAD_CFG_GPI(GPP_A20, NATIVE, DEEP), + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), // PMCALERT# + + PAD_CFG_GPI(GPP_B00, NONE, PLTRST), + PAD_CFG_GPI(GPP_B01, NONE, PLTRST), + PAD_CFG_GPI(GPP_B02, NONE, PLTRST), + PAD_CFG_GPI(GPP_B03, NONE, PLTRST), + PAD_CFG_GPI(GPP_B04, NONE, PLTRST), + PAD_CFG_GPI(GPP_B05, NONE, PLTRST), + PAD_CFG_GPI(GPP_B06, NONE, PLTRST), + PAD_CFG_GPI(GPP_B07, NONE, PLTRST), + PAD_CFG_GPO(GPP_B08, 1, PLTRST), + PAD_CFG_GPI(GPP_B09, NONE, PLTRST), + PAD_CFG_GPI(GPP_B10, NONE, PLTRST), + PAD_CFG_GPI(GPP_B11, NONE, PLTRST), + PAD_CFG_GPI(GPP_B12, NONE, PLTRST), + PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1), // PLTRST# + PAD_CFG_GPI(GPP_B14, NONE, PLTRST), + PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF2), // HDMI_HPD2 + PAD_CFG_GPI(GPP_B17, NONE, PLTRST), + PAD_CFG_GPO(GPP_B18, 1, PLTRST), + PAD_CFG_GPO(GPP_B19, 1, PLTRST), + PAD_CFG_GPI(GPP_B20, NONE, PLTRST), + PAD_CFG_GPI(GPP_B21, NONE, PLTRST), + PAD_CFG_GPI(GPP_B22, NONE, PLTRST), + PAD_CFG_GPI(GPP_B23, NONE, PLTRST), + + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C00, NONE, DEEP, NF1), // SMBCLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C01, NONE, DEEP, NF1), // SMBDATA + PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C03, NONE, DEEP, NF1), // SML0CLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C04, NONE, DEEP, NF1), // SML0DATA + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C05, UP_20K, DEEP, NF1), // SM0ALERT# + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1), // SML1CLK + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1), // SML1DATA + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C08, NONE, DEEP, NF1), // SML1ALERT# + PAD_CFG_NF(GPP_C09, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), // SRCCLKREQ1# + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), // SRCCLKREQ2# + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), // SRCCLKREQ3# + PAD_CFG_GPI(GPP_C13, NONE, PLTRST), + PAD_NC(GPP_C14, NONE), + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_CFG_GPI(GPP_C20, NONE, PLTRST), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_C23, NONE, PLTRST), + + PAD_CFG_GPO(GPP_D00, 0, PWROK), + PAD_CFG_GPI(GPP_D01, NONE, PLTRST), + PAD_CFG_GPI(GPP_D02, NONE, PLTRST), + PAD_CFG_GPI(GPP_D03, NONE, PLTRST), + PAD_CFG_GPO(GPP_D04, 1, PWROK), + PAD_CFG_GPO(GPP_D05, 1, PLTRST), + PAD_CFG_GPO(GPP_D06, 1, PLTRST), + PAD_CFG_GPO(GPP_D07, 1, PLTRST), + PAD_CFG_GPO(GPP_D08, 1, PLTRST), + PAD_CFG_GPO(GPP_D09, 0, PWROK), // ME_OVERRIDE + PAD_CFG_NF(GPP_D10, NONE, PLTRST, NF1), // HDA_BCLK + PAD_CFG_NF(GPP_D11, NATIVE, PLTRST, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_D12, NATIVE, PLTRST, NF1), // HDA_SDO + PAD_CFG_NF(GPP_D13, NATIVE, PLTRST, NF1), // HDA_SDI0 + PAD_CFG_GPI(GPP_D14, NONE, PLTRST), + PAD_CFG_GPI(GPP_D15, NONE, PLTRST), + PAD_CFG_GPI(GPP_D16, NONE, PLTRST), + PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), // HDA_RST# + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), // SRCCLKREQ6# + PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // SRCCLKREQ8# + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_D22, NATIVE, PLTRST), + PAD_CFG_GPI(GPP_D23, NATIVE, PLTRST), + + PAD_CFG_GPI(GPP_E00, NONE, PLTRST), + PAD_CFG_GPI(GPP_E01, NONE, PLTRST), + PAD_CFG_GPI(GPP_E02, NONE, PLTRST), + PAD_CFG_GPI(GPP_E03, NONE, PLTRST), + PAD_CFG_GPO(GPP_E04, 0, PLTRST), + PAD_CFG_GPO(GPP_E05, 1, PLTRST), + PAD_CFG_GPI(GPP_E06, NONE, PLTRST), + PAD_CFG_GPI(GPP_E07, NONE, PLTRST), + PAD_CFG_NF(GPP_E08, NONE, PLTRST, NF1), // DDPA_CTRLDATA + PAD_CFG_GPI(GPP_E09, NONE, PLTRST), + PAD_CFG_GPI(GPP_E10, NONE, PLTRST), + PAD_CFG_GPI(GPP_E11, NONE, PLTRST), + PAD_CFG_GPI(GPP_E12, NONE, PLTRST), + PAD_CFG_GPI(GPP_E13, NONE, PLTRST), + PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1), // HDMI_HPD + PAD_CFG_GPI(GPP_E15, NONE, PLTRST), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_E16, NONE, PLTRST, NF2), // VRALERT# + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + PAD_NC(GPP_E18, NONE), + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_CFG_NF(GPP_E22, DN_20K, PLTRST, NF1), // DDPA_CTRLCLK + + PAD_CFG_NF(GPP_F00, NONE, PLTRST, NF1), // CNV_BRI_DT + PAD_CFG_NF(GPP_F01, UP_20K, PLTRST, NF1), // CNV_BRI_RSP + PAD_CFG_NF(GPP_F02, NONE, PLTRST, NF1), // CNV_BRI_RSP + PAD_CFG_NF(GPP_F03, UP_20K, PLTRST, NF1), // CNV_RGI_DT + PAD_CFG_NF(GPP_F04, NONE, PLTRST, NF1), // CNV_RGI_RSP + PAD_CFG_NF(GPP_F05, NONE, PLTRST, NF3), // CNV_RF_RESET# + PAD_CFG_NF(GPP_F06, NONE, PLTRST, NF1), // MODEM_CLKREQ + PAD_CFG_TERM_GPO(GPP_F07, 1, DN_20K, PWROK), // CNV_PA_BLANKING + PAD_CFG_GPI(GPP_F08, DN_20K, PLTRST), + PAD_CFG_GPI(GPP_F09, NONE, PLTRST), + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + PAD_CFG_GPI(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI(GPP_F14, NONE, PLTRST), + PAD_CFG_GPI(GPP_F15, NONE, PLTRST), + PAD_CFG_GPI(GPP_F16, NONE, PLTRST), + PAD_CFG_GPI(GPP_F17, NONE, PLTRST), + PAD_CFG_GPI(GPP_F18, NONE, PLTRST), + PAD_CFG_GPI(GPP_F19, NONE, PLTRST), + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + PAD_CFG_GPI(GPP_F23, NONE, PLTRST), + + PAD_CFG_GPI(GPP_H00, NONE, PLTRST), + PAD_CFG_GPI(GPP_H01, NONE, PLTRST), + PAD_CFG_GPI(GPP_H02, NONE, PLTRST), + PAD_NC(GPP_H03, NONE), + PAD_CFG_NF(GPP_H04, NONE, PLTRST, NF2), // CNV_MFUART2_RXD + PAD_CFG_NF(GPP_H05, NONE, PLTRST, NF2), // CNV_MFUART2_TXD + PAD_CFG_GPI(GPP_H06, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_H07, UP_20K, PLTRST), + PAD_CFG_GPI(GPP_H08, NONE, PLTRST), + PAD_CFG_GPI(GPP_H09, NONE, PLTRST), + PAD_CFG_GPI(GPP_H10, NONE, PLTRST), + PAD_CFG_GPI(GPP_H11, NONE, PLTRST), + PAD_NC(GPP_H12, NONE), + PAD_CFG_GPI(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI(GPP_H14, NONE, PLTRST), + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1), // DDPB_CTRLCLK + PAD_CFG_NF(GPP_H17, NONE, PLTRST, NF1), // DDPB_CTRLDATA + PAD_NC(GPP_H18, NONE), + PAD_CFG_NF(GPP_H19, NONE, PLTRST, NF1), // CCG6DF_I2C_SDA (PD) + PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), // CCG6DF_I2C_SCL (PD) + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), + + PAD_CFG_GPI(GPP_S00, NONE, PLTRST), + PAD_CFG_GPI(GPP_S01, NONE, PLTRST), + PAD_CFG_GPI(GPP_S02, NONE, PLTRST), + PAD_CFG_GPI(GPP_S03, NONE, PLTRST), + PAD_CFG_GPI(GPP_S04, NONE, PLTRST), + PAD_CFG_GPI(GPP_S05, NONE, PLTRST), + PAD_CFG_GPI(GPP_S06, NONE, PLTRST), + PAD_CFG_GPI(GPP_S07, NONE, PLTRST), + + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // BATLOW# + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // ACPRESENT + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // SOC_WAKE# + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PWRBTN# + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SLP_S3# + PAD_CFG_NF(GPP_V05, UP_20K, PLTRST, NF1), // SLP_S4# + PAD_CFG_NF(GPP_V06, NATIVE, PLTRST, NF1), + PAD_CFG_NF(GPP_V07, NATIVE, PLTRST, NF1), + PAD_CFG_NF(GPP_V08, UP_20K, PLTRST, NF1), // SUSCLK + PAD_CFG_NF(GPP_V09, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_V10, NONE, PLTRST, NF1), + PAD_CFG_GPI(GPP_V11, NONE, PLTRST), + PAD_NC(GPP_V12, NONE), + PAD_CFG_NF(GPP_V13, NONE, PLTRST, NF1), + PAD_CFG_GPI(GPP_V14, NONE, PLTRST), // WAKE# + PAD_CFG_GPI(GPP_V15, NONE, PLTRST), + PAD_CFG_GPI(GPP_V16, NONE, PLTRST), + PAD_CFG_GPI(GPP_V17, NONE, PLTRST), + PAD_NC(GPP_V18, NONE), + PAD_CFG_NF(GPP_V19, NONE, PLTRST, NF1), + PAD_NC(GPP_V20, NONE), + PAD_NC(GPP_V21, NONE), + PAD_NC(GPP_V22, NONE), + PAD_NC(GPP_V23, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/gpio_early.c b/src/mainboard/novacustom/nuc_box/variants/nuc_box/gpio_early.c new file mode 100644 index 00000000000..b3cd0c99242 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/variants/nuc_box/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/hda_verb.c b/src/mainboard/novacustom/nuc_box/variants/nuc_box/hda_verb.c new file mode 100644 index 00000000000..c824b142612 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/variants/nuc_box/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x18490256, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x18490256), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), // DMIC + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), // DMIC + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)), // Front (Port-D) + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), // NPC + AZALIA_PIN_CFG(0, 0x19, 0x02a11020), // MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // LINE1 (Port-C) + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), // LINE2 (Port-E) + AZALIA_PIN_CFG(0, 0x1d, 0x40400001), // BEEP-IN + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), // S/PDIF-OUT + AZALIA_PIN_CFG(0, 0x21, 0x02211010), // HP1-OUT (Port-I) + + // Enable HP-JD + 0x0205001B, 0x02040A4B, 0x0205001B, 0x02040A4B, +}; + +const u32 pc_beep_verbs[] = { + // Dos beep path - 1 + 0x02170C00, 0x02050036, 0x02041151, 0x021707C0, + // Dos beep path - 2 + 0x0213B000, 0x02170C02, 0x02170C02, 0x02170C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/overridetree.cb b/src/mainboard/novacustom/nuc_box/variants/nuc_box/overridetree.cb new file mode 100644 index 00000000000..8807034adf4 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/variants/nuc_box/overridetree.cb @@ -0,0 +1,102 @@ +chip soc/intel/meteorlake + device domain 0 on + #TODO: all the devices have different subsystem product IDs + #subsystemid 0x1849 TODO inherit + + device ref tbt_pcie_rp0 on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # TBT + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # Type-C + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3 Front + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* USB3 Rear */ + [1] = USB2_PORT_MID(OC_SKIP), /* USB3 Rear */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB2 Header */ + [3] = USB2_PORT_MID(OC_SKIP), /* USB2 Header */ + [4] = USB2_PORT_TYPE_C(OC_SKIP), /* TBT */ + [5] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */ + [6] = USB2_PORT_MID(OC_SKIP), /* USB3 Front */ + [7] = USB2_PORT_MID(OC_SKIP), /* USB3 Front */ + [8] = USB2_PORT_MID(OC_SKIP), /* M.2 Key M */ + [9] = USB2_PORT_MID(OC_SKIP), /* M.2 Key E */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3 Rear */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB3 Rear */ + }" + end + device ref pcie_rp5 on + # GLAN1 + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end + end + device ref pcie_rp6 on + # GLAN2 + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp7 on + # M.2 Key-E1 + register "pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp10 on + # M.2 Key-M1 + # XXX: Schematics show RP[13:16] used + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp11 on + # M.2 Key-M2 + # XXX: Schematics show RP[17:20] used + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref sata on + register "sata_salp_support" = "1" + register "sata_ports_enable[0]" = "1" # SATA 0 + register "sata_ports_dev_slp[0]" = "1" + end + device ref hda on + subsystemid 0x1849 0x0256 + end + end +end diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/ramstage.c b/src/mainboard/novacustom/nuc_box/variants/nuc_box/ramstage.c new file mode 100644 index 00000000000..41cb35a46a7 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/variants/nuc_box/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Enable TCP1 and TCP2 USB-A conversion + // BIT 0:3 is mapping to PCH XHCI USB2 port + // BIT 4:5 is reserved + // BIT 6 is orientational + // BIT 7 is enable + params->EnableTcssCovTypeA[1] = 0x86; + params->EnableTcssCovTypeA[2] = 0x87; + + // XXX: Enabling C10 reporting causes system to constantly enter and + // exit opportunistic suspend when idle. + params->PchEspiHostC10ReportEnable = 1; +} diff --git a/src/mainboard/novacustom/nuc_box/variants/nuc_box/romstage.c b/src/mainboard/novacustom/nuc_box/variants/nuc_box/romstage.c new file mode 100644 index 00000000000..353f6662f73 --- /dev/null +++ b/src/mainboard/novacustom/nuc_box/variants/nuc_box/romstage.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/novacustom/tgl-u/Kconfig b/src/mainboard/novacustom/tgl-u/Kconfig new file mode 100644 index 00000000000..c63e7f9ab3d --- /dev/null +++ b/src/mainboard/novacustom/tgl-u/Kconfig @@ -0,0 +1,9 @@ +config BOARD_NOVACUSTOM_NV4X_TGLU + select BOARD_CLEVO_NV40MZ_BASE + +config BOARD_NOVACUSTOM_NS5X_TGLU + select BOARD_CLEVO_NS50MU_BASE + +config MAINBOARD_PART_NUMBER + default "nv40mz" if BOARD_NOVACUSTOM_NV4X_TGLU + default "ns50mu" if BOARD_NOVACUSTOM_NS5X_TGLU diff --git a/src/mainboard/novacustom/tgl-u/Kconfig.name b/src/mainboard/novacustom/tgl-u/Kconfig.name new file mode 100644 index 00000000000..3ef1695e3dc --- /dev/null +++ b/src/mainboard/novacustom/tgl-u/Kconfig.name @@ -0,0 +1,7 @@ +comment "Tiger Lake U (2021)" + +config BOARD_NOVACUSTOM_NV4X_TGLU + bool "NV4x TGL" + +config BOARD_NOVACUSTOM_NS5X_TGLU + bool "NS5x TGL" diff --git a/src/mainboard/novacustom/tgl-u/board_info.txt b/src/mainboard/novacustom/tgl-u/board_info.txt new file mode 100644 index 00000000000..a947b7df00f --- /dev/null +++ b/src/mainboard/novacustom/tgl-u/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: NovaCustom +Board name: tgl-u +Category: laptop +Release year: 2021 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 381bfcbd808..43c7b03d1ae 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ - BOARD_PCENGINES_APU5 + BOARD_PCENGINES_APU5 || BOARD_PCENGINES_APU6 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE + select HAVE_SMI_HANDLER config MAINBOARD_DIR default "pcengines/apu2" @@ -30,6 +31,7 @@ config VARIANT_DIR default "apu3" if BOARD_PCENGINES_APU3 default "apu4" if BOARD_PCENGINES_APU4 default "apu5" if BOARD_PCENGINES_APU5 + default "apu6" if BOARD_PCENGINES_APU6 config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" @@ -39,6 +41,7 @@ config MAINBOARD_PART_NUMBER default "apu3" if BOARD_PCENGINES_APU3 default "apu4" if BOARD_PCENGINES_APU4 default "apu5" if BOARD_PCENGINES_APU5 + default "apu6" if BOARD_PCENGINES_APU6 config MAX_CPUS int @@ -66,7 +69,7 @@ config APU2_PINMUX_OFF_C config APU2_PINMUX_GPIO0 bool "GPIO" depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ - BOARD_PCENGINES_APU4 + BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 config APU2_PINMUX_UART_C bool "UART 0x3e8" @@ -83,7 +86,7 @@ config APU2_PINMUX_OFF_D config APU2_PINMUX_GPIO1 bool "GPIO" depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ - BOARD_PCENGINES_APU4 + BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 config APU2_PINMUX_UART_D bool "UART 0x2e8" @@ -103,4 +106,39 @@ config AGESA_USE_1_0_0_4_HEADER revisions. This option removes the changes in headers introduced with AGESA 1.0.0.A to fit the 1.0.0.4 revision. +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config VBOOT_VBNV_OFFSET + hex + default 0x38 + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_NO_TPM + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select CBFS_VERIFICATION + select VBOOT_CBFS_INTEGRATION + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + +if VBOOT + +config VBOOT_SLOTS_RW_A + default y + +config RO_REGION_ONLY + default "AGESA apu/amdfw" + +endif + endif # BOARD_PCENGINES_APU2 diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name index 170080396ce..8ee55dbe605 100644 --- a/src/mainboard/pcengines/apu2/Kconfig.name +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -11,3 +11,6 @@ config BOARD_PCENGINES_APU4 config BOARD_PCENGINES_APU5 bool "APU5" + +config BOARD_PCENGINES_APU6 + bool "APU6" diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 95af6ef92d5..0a0f91a65bf 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include +#include #include "gpio_ftns.h" -static const PCIe_PORT_DESCRIPTOR PortList[] = { +/* + * The configuration data is duplicated for different states of power management + * because modifiable globals aren't allowed in romstage. + */ + +static const PCIe_PORT_DESCRIPTOR PortListAspm[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), @@ -15,7 +23,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x01, - 0) + 1) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -27,7 +35,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x02, - 0) + 1) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -39,7 +47,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x03, - 0) + 1) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -51,7 +59,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x04, - 0) + 1) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -63,6 +71,68 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x05, + 1) + } +}; + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x01, + 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x02, + 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x03, + 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x04, + 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x05, 0) } }; @@ -74,11 +144,57 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = NULL, }; +static const PCIe_COMPLEX_DESCRIPTOR PcieComplexAspm = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortListAspm, + .DdiLinkList = NULL, +}; + void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->PlatformConfig.CStateMode = CStateModeC6; - InitEarly->PlatformConfig.CpbMode = CpbModeAuto; + if (dasharo_apu_pcie_pm_enabled()) + InitEarly->GnbConfig.PcieComplexList = &PcieComplexAspm; + else + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + + if (dasharo_apu_cpu_boost_enabled()) { + InitEarly->PlatformConfig.CStateMode = CStateModeC6; + InitEarly->PlatformConfig.CpbMode = CpbModeAuto; + } + + if (boot_cpu()) { + volatile uint32_t *ptr = (uint32_t *)(ACPI_MMIO_BASE + WATCHDOG_BASE); + + /* + * Set PMxBE[RstToCpuPwrGdEn] = 1: FCH toggles CpuPwrGd on every reset. + * Without it, after watchdog causes a restart, D18F5x84[CmpCap] + * (number of cores on the node) sometimes reads as 0. Because of that + * AGESA hangs in subsequent InitReset calls, until next cold reset. + */ + volatile u8 *rc1 = (u8 *)(ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE); + *rc1 |= 0x80; + + uint16_t watchdog_timeout = dasharo_apu_watchdog_timeout(); + + if (watchdog_timeout == 0) { + /* watchdog disabled - default state */ + printk(BIOS_INFO, "Watchdog is disabled\n"); + } else { + /* bit 1 (WatchdogFired) is write-1-to-clear, needs to be preserved */ + uint32_t val = *ptr & ~(1 << 1); + /* enable */ + *ptr = val | (1 << 0); + /* configure timeout */ + *(ptr + 1) = (uint16_t)watchdog_timeout; + /* trigger */ + val = *ptr & ~(1 << 1); + *ptr = val | (1 << 7); + + printk(BIOS_INFO, "Watchdog is enabled, state = 0x%x, time = %d\n", + *ptr, *(ptr + 1)); + } + } } void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) diff --git a/src/mainboard/pcengines/apu2/board.fmd b/src/mainboard/pcengines/apu2/board.fmd new file mode 100644 index 00000000000..242e15c4e28 --- /dev/null +++ b/src/mainboard/pcengines/apu2/board.fmd @@ -0,0 +1,18 @@ +FLASH 8M { + SI_BIOS@0x0 0x800000 { + SMMSTORE(PRESERVE)@0x0 0x40000 + BOOTORDER(PRESERVE)@0x40000 0x1000 + + RW_UNUSED@0x41000 0x1bf000 + + WP_RO@0x200000 0x600000 { + RO_SECTION@0x0 0x600000{ + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x40000 + COREBOOT(CBFS)@0x41000 0x5bf000 + } + } + } +} diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout index fbfe445741f..93b4aeff840 100644 --- a/src/mainboard/pcengines/apu2/cmos.layout +++ b/src/mainboard/pcengines/apu2/cmos.layout @@ -11,7 +11,7 @@ entries 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -728 256 h 0 user_data +448 128 r 0 vbnv 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved @@ -32,4 +32,4 @@ enumerations checksums -checksum 392 983 984 +checksum 392 447 984 diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 242ad9d932e..3f73eb2075d 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -22,7 +23,9 @@ #define SPD_SIZE 128 #define PM_RTC_CONTROL 0x56 +#define PM_RTC_SHADOW 0x5B #define PM_S_STATE_CONTROL 0xBA +#define PM_PCI_CONFIG 0xEA /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -167,20 +170,42 @@ static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, const int len = smbios_full_table_len(&t->header, t->eos); *current += len; + *handle += 1; + return len; } -static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, +static int ddr_speed_from_bus_speed(int bus) +{ + switch (bus) { + case 166: + case 216: + case 266: + case 333: + case 1066: + case 1666: + return bus * 2 + 1; + case 556: + case 667: + case 688: + case 813: + return bus * 2 - 1; + default: + return bus * 2; + } +} + +static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, int type16, unsigned long *current) { struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE, - sizeof(*t), *handle + 1); + sizeof(*t), *handle); - t->phys_memory_array_handle = *handle; + t->phys_memory_array_handle = type16; t->memory_error_information_handle = 0xfffe; t->total_width = agesa_dmi->T17[0][0][0].TotalWidth; t->data_width = agesa_dmi->T17[0][0][0].DataWidth; - t->size = agesa_dmi->T17[0][0][0].MemorySize; + t->size = get_spd_offset() == 0 ? 2 * 1024 : 4 * 1024; /* unit: megabytes */ t->form_factor = agesa_dmi->T17[0][0][0].FormFactor; t->device_set = agesa_dmi->T17[0][0][0].DeviceSet; t->device_locator = smbios_add_string(t->eos, @@ -189,7 +214,7 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, agesa_dmi->T17[0][0][0].BankLocator); t->memory_type = agesa_dmi->T17[0][0][0].MemoryType; t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail; - t->speed = agesa_dmi->T17[0][0][0].Speed; + t->speed = ddr_speed_from_bus_speed(agesa_dmi->T17[0][0][0].Speed); t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode; t->serial_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].SerialNumber); @@ -197,12 +222,59 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, agesa_dmi->T17[0][0][0].PartNumber); t->attributes = agesa_dmi->T17[0][0][0].Attributes; t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; - t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed; + t->clock_speed = + ddr_speed_from_bus_speed(agesa_dmi->T17[0][0][0].ConfigSpeed); t->minimum_voltage = 1500; /* From SPD: 1.5V */ t->maximum_voltage = 1500; const int len = smbios_full_table_len(&t->header, t->eos); *current += len; + *handle += 1; + + return len; +} + +static int mainboard_smbios_type19(unsigned long *current, int *handle, int type16, u64 *addr_end) +{ + struct smbios_type19 *t = smbios_carve_table(*current, + SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS, + sizeof(*t), *handle); + + t->memory_array_handle = type16; + t->extended_ending_address = get_spd_offset() == 0 ? 2 * 1024 : 4 * 1024; /* unit: megabytes */ + t->partition_width = 1; + t->extended_ending_address *= MiB; + t->starting_address = 0; + t->ending_address = t->extended_ending_address / KiB - 1; + t->extended_starting_address = 0; + t->extended_ending_address = 0; + *addr_end = t->ending_address; + + const int len = smbios_full_table_len(&t->header, t->eos); + *current += len; + *handle += 1; + + return len; +} + +static int mainboard_smbios_type20(unsigned long *current, int *handle, int type17, int type19, + u64 addr_end) +{ + struct smbios_type20 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS, + sizeof(*t), *handle); + + t->memory_device_handle = type17; + t->memory_array_mapped_address_handle = type19; + t->addr_start = 0; + t->addr_end = addr_end; + t->partition_row_pos = 0xff; + t->interleave_pos = 0xff; + t->interleave_depth = 0xff; + + const int len = smbios_full_table_len(&t->header, t->eos); + *current += len; + *handle += 1; + return len; } @@ -211,21 +283,82 @@ static int mainboard_smbios_data(struct device *dev, int *handle, { DMI_INFO *agesa_dmi; int len = 0; + u64 addr_end; + int type16, type17, type19; agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); if (!agesa_dmi) return len; + type16 = *handle; len += mainboard_smbios_type16(agesa_dmi, handle, current); - len += mainboard_smbios_type17(agesa_dmi, handle, current); - - *handle += 2; + type17 = *handle; + len += mainboard_smbios_type17(agesa_dmi, handle, type16, current); + type19 = *handle; + len += mainboard_smbios_type19(current, handle, type16, &addr_end); + len += mainboard_smbios_type20(current, handle, type17, type19, addr_end); return len; } + +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + DMI_INFO *agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + return agesa_dmi->T4[0].T4CurrentSpeed; +} + +unsigned int smbios_processor_external_clock(void) +{ + DMI_INFO *agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + return agesa_dmi->T4[0].T4ExternalClock; +} + +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + DMI_INFO *agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + return agesa_dmi->T4[0].T4MaxSpeed; +} + +unsigned int smbios_cpu_get_voltage(void) +{ + DMI_INFO *agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + return agesa_dmi->T4[0].T4Voltage; +} #endif +static void measure_amd_blobs(void) +{ + void *amdfw = NULL; + size_t size; + + /* Simply mapping the CBFS file will trigger the measurement */ + amdfw = cbfs_unverified_area_map("COREBOOT", "apu/amdfw", &size); + + if (!amdfw) { + printk(BIOS_ERR,"Could not map apu/amdfw CBFS file\n"); + return; + } + + cbfs_unmap(amdfw); +} + static void mainboard_enable(struct device *dev) { /* Maintain this text unchanged for manufacture process. */ @@ -243,15 +376,68 @@ static void mainboard_enable(struct device *dev) // pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); + // + // Enable power on after power fail + // + pm_write8(PM_RTC_SHADOW, pm_read8(PM_RTC_SHADOW) | (1 << 0)); + + // + // Enable GENINTx as GPIO + // + pm_write8(PM_PCI_CONFIG, 1); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); #if CONFIG(GENERATE_SMBIOS_TABLES) dev->ops->get_smbios_data = mainboard_smbios_data; #endif + + if (CONFIG(TPM_MEASURED_BOOT)) + measure_amd_blobs(); } static void mainboard_final(void *chip_info) { + /* ECC was not working because all memory was marked + * as excluded from ECC checking and error reporting. + * Normally one contiguous range is excluded to cover + * framebuffer region in systems with internal GPUs. + * AGESA set bit 0, EccExclEn, in register D18F5x240 as 1. + * Range was incorrectly enabled to cover all memory + * for cases without UMA (no integrated graphics). + * + * In order to clear EccExclEn DRAM scrubber needs to be + * disabled temporarily by setting D18F3x88[DisDramScrub] + */ + u32 val; + struct device *D18F3 = dev_find_device(0x1022, 0x1583, NULL); + struct device *D18F5 = dev_find_device(0x1022, 0x1585, NULL); + + /* Disable DRAM ECC scrubbing */ + val = pci_read_config32(D18F3, 0x88); + val |= (1 << 27); + pci_write_config32(D18F3, 0x88, val); + + /* Clear reserved bits in register D18F3xB8 + * + * D18F3xB8 NB Array Address has reserved bits [27:10] + * Multiple experiments showed that ECC injection + * doesn't work when these bits are set. + */ + val = pci_read_config32(D18F3, 0xB8); + val &= 0xF000003F; + pci_write_config32(D18F3, 0xB8, val); + + /* Disable ECC exclusion range */ + val = pci_read_config32(D18F5, 0x240); + val &= ~1; + pci_write_config32(D18F5, 0x240, val); + + /* Re-enable DRAM ECC scrubbing */ + val = pci_read_config32(D18F3, 0x88); + val &= ~(1 << 27); + pci_write_config32(D18F3, 0x88, val); + // // Turn off LED 2 and LED 3 // diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 2509031f3e5..a5d35dde4c1 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -8,6 +9,7 @@ #include #include #include +#include #include "gpio_ftns.h" @@ -17,6 +19,9 @@ void board_BeforeAgesa(struct sysinfo *cb) { u32 val; + /* CF9 shadow */ + pm_write8(FCH_PMIOA_REGC5, 0); + early_lpc_init(); /* Disable SVI2 controller to wait for command completion */ @@ -30,6 +35,31 @@ void board_BeforeAgesa(struct sysinfo *cb) pm_write8(0xea, 1); } +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + u32 val; + + if (boot_cpu()) { + /* CF9 shadow: 0 */ + pm_write8(FCH_PMIOA_REGC5, 0); + + /* Check if cold boot was requested */ + val = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x6C); + if (val & (1 << 4)) { + printk(BIOS_ALERT, "Forcing cold boot path\n"); + val &= ~(0x630); // ColdRstDet[4], BiosRstDet[10:9, 5] + pci_write_config32(PCI_DEV(0, 0x18, 0), 0x6C, val); + + /* S5ResetStatus */ + pm_write32(0xc0, 0x3fff003f); // Write-1-to-clear resets + + /* CF9 shadow: FullRst, SysRst, RstCmd */ + pm_write8(FCH_PMIOA_REGC5, 0xe); + printk(BIOS_ALERT, "Did not reset (yet)\n"); + } + } +} + const struct soc_amd_gpio gpio_common[] = { PAD_GPI(GPIO_49, PULL_NONE), PAD_GPI(GPIO_50, PULL_NONE), @@ -47,7 +77,7 @@ const struct soc_amd_gpio gpio_apu2[] = { PAD_GPI(GPIO_32, PULL_NONE), }; -const struct soc_amd_gpio gpio_apu34[] = { +const struct soc_amd_gpio gpio_apu346[] = { PAD_GPI(GPIO_32, PULL_NONE), PAD_GPO(GPIO_33, LOW), }; @@ -65,8 +95,9 @@ static void early_lpc_init(void) if (CONFIG(BOARD_PCENGINES_APU2)) gpio_configure_pads(gpio_apu2, ARRAY_SIZE(gpio_apu2)); - if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4)) - gpio_configure_pads(gpio_apu34, ARRAY_SIZE(gpio_apu34)); + if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4) || + CONFIG(BOARD_PCENGINES_APU6)) + gpio_configure_pads(gpio_apu346, ARRAY_SIZE(gpio_apu346)); if (CONFIG(BOARD_PCENGINES_APU5)) gpio_configure_pads(gpio_apu5, ARRAY_SIZE(gpio_apu5)); diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 5c169208b9c..a67cb885eaa 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -48,6 +48,9 @@ chip northbridge/amd/pi/00730F01 device pnp 2e.607 off end device pnp 2e.f on end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM end device ref sdhci on end device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index 57eebb65220..03fe0729d3f 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -48,6 +48,9 @@ chip northbridge/amd/pi/00730F01 device pnp 2e.607 off end device pnp 2e.f on end end # SIO NCT5104D + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM end device ref sdhci on end device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI diff --git a/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb new file mode 100644 index 00000000000..5e7f01c03e8 --- /dev/null +++ b/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/pi/00730F01 + device domain 0 on + subsystemid 0x1022 0x1410 inherit + + device ref iommu on end # IOMMU + device ref gpp_bridge_0 on end # LAN1 + device ref gpp_bridge_1 on end # LAN2 + device ref gpp_bridge_2 on end # LAN3 + device ref gpp_bridge_3 on end # LAN4 + device ref gpp_bridge_4 on end # mPCIe slot 1 + + chip southbridge/amd/pi/hudson + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_0 on end # USB EHCI0 usb[0:3] + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + register "reset_gpios" = "1" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.008 off end + device pnp 2e.108 on + io 0x60 = 0x220 + end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.f on end + end # SIO NCT5104D + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM + end + register "sd_mode" = "3" + device ref sdhci on end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/mainboard/pcengines/apu2/vboot-rwa.fmd b/src/mainboard/pcengines/apu2/vboot-rwa.fmd new file mode 100644 index 00000000000..8f3b555d437 --- /dev/null +++ b/src/mainboard/pcengines/apu2/vboot-rwa.fmd @@ -0,0 +1,22 @@ +FLASH@0xFF800000 8M { + SI_BIOS { + SMMSTORE(PRESERVE) 256K + RW_NVRAM(PRESERVE) 4K + + RW_SECTION_A { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + WP_RO 4M { + RO_SECTION { + FMAP 4K + RO_FRID 0x100 + RO_FRID_PAD 0x700 + GBB 64K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/protectli/vault_adl_n/Kconfig b/src/mainboard/protectli/vault_adl_n/Kconfig new file mode 100644 index 00000000000..3bb7ca0bb27 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/Kconfig @@ -0,0 +1,95 @@ +if BOARD_PROTECTLI_VP32XX || BOARD_PROTECTLI_VP2430 || BOARD_PROTECTLI_VP2440 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_COMMON_BLOCK_TCSS + select SUPERIO_ITE_IT8659E + select DRIVERS_UART_8250IO + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_PMC + select FSP_TYPE_IOT + select HAVE_ACPI_RESUME if !BOARD_PROTECTLI_VP2440 + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MEMORY_MAPPED_TPM + select USE_DDR5 + +config MAINBOARD_DIR + default "protectli/vault_adl_n" + +config MAINBOARD_PART_NUMBER + default "VP32XX" if BOARD_PROTECTLI_VP32XX + default "VP2430" if BOARD_PROTECTLI_VP2430 + default "VP2440" if BOARD_PROTECTLI_VP2440 + +config VARIANT_DIR + default "vp32xx" if BOARD_PROTECTLI_VP32XX + default "vp2430" if BOARD_PROTECTLI_VP2430 + default "vp2440" if BOARD_PROTECTLI_VP2440 + +config MAINBOARD_VENDOR + default "Protectli" + +config MAINBOARD_FAMILY + default "Vault Pro" + +config DIMM_SPD_SIZE + default 1024 + +config DIMM_MAX + default 2 + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config USE_LEGACY_8254_TIMER + default y + +config CBFS_SIZE + default 0xb00000 + +config TPM_PIRQ + default 0x39 # GPP_E13_IRQ + +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/data.vbt" + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select HAS_RECOVERY_MRC_CACHE + select VBOOT_NO_TPM + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +config BEEP_ON_BOOT + bool "Beep on successful boot" + default y + help + Make the platform beep using the PC speaker in final coreboot phase. + May serve as a useful indicator in headless mode that platform is + properly booting. + +endif diff --git a/src/mainboard/protectli/vault_adl_n/Kconfig.name b/src/mainboard/protectli/vault_adl_n/Kconfig.name new file mode 100644 index 00000000000..1d2bccacaae --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/Kconfig.name @@ -0,0 +1,8 @@ +config BOARD_PROTECTLI_VP32XX + bool "VP3210/VP3230" + +config BOARD_PROTECTLI_VP2430 + bool "VP2430" + +config BOARD_PROTECTLI_VP2440 + bool "VP2440" diff --git a/src/mainboard/protectli/vault_adl_n/Makefile.mk b/src/mainboard/protectli/vault_adl_n/Makefile.mk new file mode 100644 index 00000000000..634fb45d5e3 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/Makefile.mk @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c + +romstage-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c +ramstage-y += hda_verb.c + +all-y += die.c +smm-y += die.c + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/protectli/vault_adl_n/acpi/superio.asl b/src/mainboard/protectli/vault_adl_n/acpi/superio.asl new file mode 100644 index 00000000000..cf5a2c5d5fc --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/acpi/superio.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8659E_SHOW_UARTA +#define IT8659E_SHOW_UARTB + +#define IT8659E_EC_IO0 +#define IT8659E_EC_IO1 +#define IT8659E_SHOW_EC + +#define IT8659E_GPIO_IO0 +#define IT8659E_GPIO_IO1 +#define IT8659E_SHOW_GPIO + +#include diff --git a/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl b/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl new file mode 100644 index 00000000000..8da6a5e6df0 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (\_SB.PCI0.I2C4) +{ + Device (PD01) + { + Name (_HID, "INT3515") + Name (_UID, One) + Name (_DDN, "TPS65994 USB-C PD Controller") + Name (_STA, 0x0F) + Name (_CRS, ResourceTemplate () + { + I2cSerialBusV2 (0x0023, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , Exclusive, ) +/* Only one port on VP2440 */ +#if !CONFIG(BOARD_PROTECTLI_VP2440) + I2cSerialBusV2 (0x0027, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , Exclusive) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + GPP_F13_IRQ + } +#endif + /* Linux driver expects one interrupt resource per one I2C dev */ + Interrupt (ResourceConsumer, Level, ActiveLow) + { + GPP_F13_IRQ + } + }) + } +} diff --git a/src/mainboard/protectli/vault_adl_n/board_info.txt b/src/mainboard/protectli/vault_adl_n/board_info.txt new file mode 100644 index 00000000000..83ce8ec23e8 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/board_info.txt @@ -0,0 +1,7 @@ +Category: sbc +Board URL: https://eu.protectli.com/product/vp3230/ +ROM IC: Macronix KH25L12835F +ROM package: SOIC8 +ROM socketed: no +Flashrom support: yes +Release year: 2024 diff --git a/src/mainboard/protectli/vault_adl_n/bootblock.c b/src/mainboard/protectli/vault_adl_n/bootblock.c new file mode 100644 index 00000000000..20439474584 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/bootblock.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + + +#if CONFIG_UART_FOR_CONSOLE == 0 +#define UART_DEV PNP_DEV(0x2e, IT8659E_SP1) +#elif CONFIG_UART_FOR_CONSOLE == 1 +#define UART_DEV PNP_DEV(0x2e, IT8659E_SP2) +#else +#error "Wrong UART_FOR_CONSOLE setting" +#endif + +#define GPIO_DEV PNP_DEV(0x2e, IT8659E_GPIO) + +static void ite_set_gpio_iobase(u16 iobase) +{ + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(GPIO_DEV); +} + +void bootblock_mainboard_early_init(void) +{ + /* Internal VCC_OK */ + ite_reg_write(GPIO_DEV, 0x23, 0x00); + /* Set pin native functions */ + ite_reg_write(GPIO_DEV, 0x26, 0xc0); + /* Pin28 as GP41 - PC speaker */ + ite_reg_write(GPIO_DEV, 0x28, 0x02); + /* Set GPIOs exposed on pin header as GPIO functions */ + ite_reg_write(GPIO_DEV, 0x29, 0xc0); + /* Sets a reserved bit6 to reflect original FW configuration */ + ite_reg_write(GPIO_DEV, 0x2c, 0xc9); + ite_kill_watchdog(GPIO_DEV); + /* GP41 - PC Speaker configuration */ + ite_gpio_setup(GPIO_DEV, 41, + ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_CONTROL_DEFAULT); + ite_set_gpio_iobase(0xa00); + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/protectli/vault_adl_n/data.vbt b/src/mainboard/protectli/vault_adl_n/data.vbt new file mode 100644 index 00000000000..0ce74a433d9 Binary files /dev/null and b/src/mainboard/protectli/vault_adl_n/data.vbt differ diff --git a/src/mainboard/protectli/vault_adl_n/devicetree.cb b/src/mainboard/protectli/vault_adl_n/devicetree.cb new file mode 100644 index 00000000000..46d177214c7 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/devicetree.cb @@ -0,0 +1,251 @@ +chip soc/intel/alderlake + # FSP configuration + + register "eist_enable" = "1" + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + register "RMT" = "0" + register "enable_c6dram" = "1" + + register "tcc_offset" = "20" # TCC of 80C + + register "common_soc_config" = "{ + // JNTP + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + // USB-PD + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + + device cpu_cluster 0 on end + device domain 0 on + device pci 05.0 off end # IPU + device pci 08.0 off end # GNA + device pci 09.0 off end # Intel Trace Hub + device pci 14.1 off end # USB xDCI (OTG) + subsystemid 0x8086 0x7270 inherit + + device ref igpu on + register "ddi_portA_config" = "1" # HDMI on port A + register "ddi_portB_config" = "1" # DP on port B + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, + }" + end + + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB Type-C no TBT + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB Type-C no TBT + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # Bits (4,5) allocated for TCSS Port3 configuration and Bits (6,7)for TCSS Port4. + # Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0x05" + # Do not configure these pads in coreboot, otherwise Type-C display won't work + # It seems coreboot attempts to program it too late. + #register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + #register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A14, .pad_auxn_dc = GPP_A15}" + + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1 (USB1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # 5G + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 USB2 + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # FUSB1 + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 USB2 + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C no TBT + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C no TBT + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # FUSB1 + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # WiFi slot + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 5G + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 5G (KEY_B_5G)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2 (COM_USB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 (FUSB1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1 (COM_USB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port4 on end + end + + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 (FUSB1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WiFi/Bluetooth (KEY_E_WIFI)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 LTE/5G (KEY_B_5G)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on end + end + end + end + end + + device ref heci1 on end + + device ref emmc on + register "emmc_enable_hs400_mode" = "true" + end + + device ref i2c0 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + end + + device ref i2c4 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + end + + device ref pch_espi on + # LPC generic I/O ranges + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c0081" + + chip superio/ite/it8659e + register "TMPIN1.mode" = "THERMAL_PECI" + register "TMPIN1.offset" = "100" + register "ec.vin_mask" = "VIN0 | VIN2 | VIN3 | VIN7" + + # FAN1 is CPU fan (connector on board) + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = " 1" + register "FAN1.smart.tmp_off" = "40" + register "FAN1.smart.tmp_start" = "50" + register "FAN1.smart.tmp_full" = "85" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + register "FAN1.smart.tmp_delta" = "2" + + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0xf1 = 0x52 # IRQ low level + end + device pnp 2e.2 on # COM 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 0x52 # IRQ low level + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa20 + io 0x62 = 0xa10 + irq 0x70 = 0 # Don't use IRQ + irq 0xf0 = 0x80 # Clear 3VSB off status + irq 0xf4 = 0x60 # Use SB to control AC power loss + irq 0xfa = 0x02 # Enable 5VSB_CTRL# + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa08 + io 0x62 = 0xa00 + end + device pnp 2e.a off end # CIR + end + + chip drivers/pc80/tpm + device pnp 0.0 on end + end + + end + device ref p2sb hidden end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "true" + end + device ref smbus on end + end +end diff --git a/src/mainboard/protectli/vault_adl_n/die.c b/src/mainboard/protectli/vault_adl_n/die.c new file mode 100644 index 00000000000..5214e616d7d --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/die.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void die_notify(void) +{ + uint8_t beep_count = 0; + + if (ENV_POSTCAR) + return; + + /* Beep 12 times at most, constant beeps may be annoying */ + for ( ; beep_count < 12; beep_count++) { + beep(800, 300); + mdelay(200); + if (beep_count % 4 == 3) + delay(2); + } +} diff --git a/src/mainboard/protectli/vault_adl_n/dsdt.asl b/src/mainboard/protectli/vault_adl_n/dsdt.asl new file mode 100644 index 00000000000..47c0c8f6be1 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/dsdt.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + #include + } + + Scope (\_SB.PCI0.LPCB) + { + #include "acpi/superio.asl" + } + + #include + + #include "acpi/usb_pd.asl" +} diff --git a/src/mainboard/protectli/vault_adl_n/hda_verb.c b/src/mainboard/protectli/vault_adl_n/hda_verb.c new file mode 100644 index 00000000000..a8a40ed595a --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Alderlake-P HDMI */ + 0x8086281c, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 7, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault_adl_n/include/variant/gpio.h b/src/mainboard/protectli/vault_adl_n/include/variant/gpio.h new file mode 100644 index 00000000000..c54657be7b8 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +const struct pad_config *board_gpio_table(size_t *num); + +#endif /* VARIANT_GPIO_H */ diff --git a/src/mainboard/protectli/vault_adl_n/mainboard.c b/src/mainboard/protectli/vault_adl_n/mainboard.c new file mode 100644 index 00000000000..df7f9811d21 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/mainboard.c @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +const char *smbios_mainboard_product_name(void) +{ + if (CONFIG(BOARD_PROTECTLI_VP2430)) + return "VP2430"; + + if (CONFIG(BOARD_PROTECTLI_VP2440)) + return "VP2440"; + + u32 tmp[13]; + const char *str = "Unknown Processor Name"; + + if (cpu_have_cpuid()) { + int i; + struct cpuid_result res; + if (cpu_cpuid_extended_level() >= 0x80000004) { + int j = 0; + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + tmp[j++] = res.eax; + tmp[j++] = res.ebx; + tmp[j++] = res.ecx; + tmp[j++] = res.edx; + } + tmp[12] = 0; + str = (const char *)tmp; + } + } + + if (strstr(str, "N100") != NULL) + return "VP3210"; + else if (strstr(str, "N305") != NULL) + return "VP3230"; + else + return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; +} + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm)); + memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating)); + memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating)); + memset(params->CpuPcieRpPmSci, 0, sizeof(params->CpuPcieRpPmSci)); + + // Max payload 256B + memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload)); + + if (CONFIG(BOARD_PROTECTLI_VP32XX)) { + /* + * CLKREQs connected only to RP3 and RP7, but other CLKREQs are + * pulled to GND, So it should be fine to enable CPM on all RPs. + */ + params->PcieRpEnableCpm[0] = 1; + params->PcieRpEnableCpm[2] = 1; + params->PcieRpEnableCpm[4] = 1; + params->PcieRpEnableCpm[6] = 1; + params->PcieRpEnableCpm[9] = 1; + } + + if (CONFIG(BOARD_PROTECTLI_VP2440)) { + /* + * All PCIe ports have an exclusive CLKREQ. + */ + params->PcieRpEnableCpm[0] = 1; + params->PcieRpEnableCpm[6] = 1; + params->PcieRpEnableCpm[8] = 1; + /* + * Some WiFi cards do not get detected if CPM is enabled. + * params->PcieRpEnableCpm[10] = 1; + */ + params->PcieRpEnableCpm[11] = 1; + } + + // Enable port reset message on Type-C ports + params->PortResetMessageEnable[4] = 1; + params->PortResetMessageEnable[5] = 1; + + /* + * Configure AUX bias pads in FPS-S, because coreboot would do it too + * late and cause the Type-C displays to not work. + */ + params->IomTypeCPortPadCfg[0] = 0x09020016; // GPP_A22 + params->IomTypeCPortPadCfg[1] = 0x09020015; // GPP_A21 + + if (!CONFIG(BOARD_PROTECTLI_VP2440)) { + params->IomTypeCPortPadCfg[2] = 0x0902000F; // GPP_A15 + params->IomTypeCPortPadCfg[3] = 0x0902000E; // GPP_A14 + } + + // PMC-PD controller + params->PmcPdEnable = 1; + + // IOM USB config + params->PchUsbOverCurrentEnable = 0; + + if (CONFIG(BOARD_PROTECTLI_VP2440)) { + /* + * Second Type-C port used as regular USB3.x for LTE. + * Remap it to PCH xHCI first port. + */ + params->EnableTcssCovTypeA[1] = 1; + params->MappingPchXhciUsbA[1] = 6; + } +} + +static void mainboard_final(void *chip_info) +{ + if (CONFIG(BEEP_ON_BOOT)) + beep(1500, 100); +} + +static void set_fan_curve(struct ite_ec_fan_config *fan, uint8_t fan_curve) +{ + switch (fan_curve) { + case FAN_CURVE_OPTION_OFF: + fan->mode = FAN_MODE_OFF; + break; + case FAN_CURVE_OPTION_PERFORMANCE: + fan->smart.pwm_start += 20; + fan->smart.tmp_full -= 10; + fan->smart.tmp_off -= 10; + fan->smart.tmp_start -= 10; + break; + case FAN_CURVE_OPTION_SILENT: + /* Do nothing, it is the default */ + default: + break; + } +} + +static void mainboard_enable(struct device *dev) +{ + struct superio_ite_it8659e_config *ite_cfg; + struct device *ite_ec = dev_find_slot_pnp(0x2e, IT8659E_EC); + uint8_t fan_curve = get_fan_curve_option(); + + if (ite_ec && ite_ec->chip_info) { + ite_cfg = (struct superio_ite_it8659e_config *)ite_ec->chip_info; + set_fan_curve(&ite_cfg->ec.fan[0], fan_curve); + if (CONFIG(BOARD_PROTECTLI_VP32XX)) + set_fan_curve(&ite_cfg->ec.fan[1], fan_curve); + } +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, + .enable_dev = mainboard_enable +}; diff --git a/src/mainboard/protectli/vault_adl_n/romstage_fsp_params.c b/src/mainboard/protectli/vault_adl_n/romstage_fsp_params.c new file mode 100644 index 00000000000..e60c79443f9 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/romstage_fsp_params.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + .ect = true, /* Early Command Training */ + .UserBd = BOARD_TYPE_MOBILE, + .LpDdrDqDqsReTraining = 1, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct pad_config *pads; + size_t num; + + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); + + pads = board_gpio_table(&num); + gpio_configure_pads(pads, num); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + memupd->FspmConfig.DmiMaxLinkSpeed = 4; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; +} diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c b/src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c new file mode 100644 index 00000000000..b02b2c4a884 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c @@ -0,0 +1,802 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + + /* GPP_B3 - GPIO */ + PAD_NC(GPP_B3, NONE), + + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + PAD_NC(GPP_B8, NONE), + + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + + /* GPP_B15 - GPIO */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_CFG_GPO(GPP_B18, 0, DEEP), + + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + + /* GPP_A6 - GPIO */ + PAD_NC(GPP_A6, NONE), + + /* GPP_A7 - GPIO */ + PAD_NC(GPP_A7, NONE), + + /* GPP_A8 - GPIO */ + PAD_NC(GPP_A8, NONE), + + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - GPIO */ + PAD_NC(GPP_A12, NONE), + + /* GPP_A13 - GPIO */ + PAD_NC(GPP_A13, NONE), + + /* GPP_A14 - USB_C_GPP_A14 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF6), + + /* GPP_A15 - USB_C_GPP_A15 */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF6), + + /* GPP_A16 - USB_OC3# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPP_A17 - GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + + /* GPP_A20 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + + /* GPP_A21 - USB_C_GPP_A21 */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + + /* GPP_A22 - USB_C_GPP_A22 */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + + /* GPP_A23 - ESPI_CS1# */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), + + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_S ------- */ + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - GPIO */ + PAD_NC(GPP_I0, NONE), + + /* GPP_I1 - GPIO */ + PAD_NC(GPP_I1, NONE), + + /* GPP_I2 - GPIO */ + PAD_NC(GPP_I2, NONE), + + /* GPP_I3 - GPIO */ + PAD_NC(GPP_I3, NONE), + + /* GPP_I4 - GPIO */ + PAD_NC(GPP_I4, NONE), + + /* GPP_I5 - GPIO */ + PAD_NC(GPP_I5, NONE), + + /* GPP_I6 - GPIO */ + PAD_NC(GPP_I6, NONE), + + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* GPP_I19 - GPIO */ + PAD_NC(GPP_I19, NONE), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + + /* GPP_H1 - GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), + + /* GPP_H2 - GPIO */ + PAD_CFG_GPO(GPP_H2, 0, DEEP), + + /* GPP_H3 - GPIO */ + PAD_NC(GPP_H3, NONE), + + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* GPP_H6 - GPIO */ + PAD_NC(GPP_H6, NONE), + + /* GPP_H7 - GPIO */ + PAD_NC(GPP_H7, NONE), + + /* GPP_H8 - I2C4_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + + /* GPP_H9 - I2C4_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* GPP_H10 - GPIO */ + PAD_NC(GPP_H10, NONE), + + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11, NONE), + + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12, NONE), + + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16, NONE), + + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - SRCCLKREQ4# */ + PAD_NC(GPP_H19, NONE), + + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + PAD_NC(GPP_D0, NONE), + + /* GPP_D1 - GPIO */ + PAD_NC(GPP_D1, NONE), + + /* GPP_D2 - GPIO */ + PAD_NC(GPP_D2, NONE), + + /* GPP_D3 - GPIO */ + PAD_NC(GPP_D3, NONE), + + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - SRCCLKREQ0# */ + PAD_NC(GPP_D5, NONE), + + /* GPP_D6 - SRCCLKREQ1# */ + PAD_NC(GPP_D6, NONE), + + /* GPP_D7 - SRCCLKREQ2# */ + PAD_NC(GPP_D7, NONE), + + /* GPP_D8 - SRCCLKREQ3# */ + PAD_NC(GPP_D8, NONE), + + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D12 - GPIO */ + PAD_NC(GPP_D12, NONE), + + /* GPP_D13 - GPIO */ + PAD_NC(GPP_D13, NONE), + + /* GPP_D14 - GPIO */ + PAD_NC(GPP_D14, NONE), + + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + /* ------- GPIO Group GPP_GPD ------- */ + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + + /* GPD7 - GPIO */ + PAD_CFG_GPO(GPD7, 0, PWROK), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - GPIO */ + PAD_CFG_GPO(GPD9, 0, PWROK), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + + /* GPD11 - GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), + + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + /* GPP_F2 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* GPP_F5 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - GPIO */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), + + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + + /* GPP_F11 - GPIO */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - TYPE_C_PD_IRQ */ + PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST), + + /* GPP_F14 - GPIO */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + PAD_NC(GPP_F17, NONE), + + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - Reserved */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - Reserved */ + PAD_NC(GPP_F21, NONE), + + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + /* GPP_L_BKLTEN - n/a */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + + /* GPP_L_BKLTCTL - n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + + /* GPP_L_VDDEN - n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + PAD_NC(GPP_E1, NONE), + + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + + /* GPP_E3 - GPIO */ + PAD_NC(GPP_E3, NONE), + + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E5 - GPIO */ + PAD_NC(GPP_E5, NONE), + + /* GPP_E6 - GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), + + /* GPP_E7 - GPIO */ + PAD_NC(GPP_E7, NONE), + + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_NC(GPP_E15, NONE), + + /* GPP_E16 - GPIO */ + PAD_NC(GPP_E16, NONE), + + /* GPP_E17 - GPIO */ + PAD_NC(GPP_E17, NONE), + + /* GPP_E18 - GPIO */ + PAD_NC(GPP_E18, NATIVE), + + /* GPP_E19 - GPIO */ + PAD_NC(GPP_E19, NATIVE), + + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NATIVE), + + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NATIVE), + + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_R ------- */ + /* GPP_R0 - GPIO */ + PAD_NC(GPP_R0, NONE), + + /* GPP_R1 - GPIO */ + PAD_NC(GPP_R1, NONE), + + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - GPIO */ + PAD_NC(GPP_R3, NONE), + + /* GPP_R4 - GPIO */ + PAD_NC(GPP_R4, NONE), + + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb new file mode 100644 index 00000000000..ec883940e4f --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb @@ -0,0 +1,78 @@ +chip soc/intel/alderlake + # FSP configuration + + device domain 0 on + device ref sata on + register "sata_ports_enable[0]" = "1" + end + + # LAN1 + device ref pcie_rp2 on + register "pch_pcie_rp[PCH_RP(2)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 0, + }" + end + # LAN2 + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 1, + }" + end + # LAN 3 + device ref pcie_rp4 on + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 2, + }" + end + # LAN4 + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 3, + }" + end + # WIFI + device ref pcie_rp12 on + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 4, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end + # NVMe x2 link + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 0, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_NVME2X)" "SlotDataBusWidth2X" + end + + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port6 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + end +end diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2440/gpio.c b/src/mainboard/protectli/vault_adl_n/variants/vp2440/gpio.c new file mode 100644 index 00000000000..91a3a607ad8 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp2440/gpio.c @@ -0,0 +1,806 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + + /* GPP_B3 - GPIO */ + PAD_NC(GPP_B3, NONE), + + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + PAD_NC(GPP_B8, NONE), + + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + + /* GPP_B15 - GPIO */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_CFG_GPO(GPP_B18, 0, DEEP), + + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + + /* GPP_A6 - GPIO */ + PAD_NC(GPP_A6, NONE), + + /* GPP_A7 - GPIO */ + PAD_NC(GPP_A7, NONE), + + /* GPP_A8 - GPIO */ + PAD_NC(GPP_A8, NONE), + + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + + /* GPP_A13 - GPIO */ + PAD_NC(GPP_A13, NONE), + + /* GPP_A14 - GPIO */ + PAD_NC(GPP_A14, NONE), + + /* GPP_A15 - GPIO */ + PAD_NC(GPP_A15, NONE), + + /* GPP_A16 - USB_OC3# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPP_A17 - GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + + /* GPP_A20 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + + /* GPP_A21 - USB_C_GPP_A21 */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + + /* GPP_A22 - USB_C_GPP_A22 */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + + /* GPP_A23 - ESPI_CS1# */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), + + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_S ------- */ + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - GPIO */ + PAD_NC(GPP_I0, NONE), + + /* GPP_I1 - GPIO */ + PAD_NC(GPP_I1, NONE), + + /* GPP_I2 - GPIO */ + PAD_NC(GPP_I2, NONE), + + /* GPP_I3 - GPIO */ + PAD_NC(GPP_I3, NONE), + + /* GPP_I4 - GPIO */ + PAD_NC(GPP_I4, NONE), + + /* GPP_I5 - GPIO */ + PAD_NC(GPP_I5, NONE), + + /* GPP_I6 - GPIO */ + PAD_NC(GPP_I6, NONE), + + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* GPP_I19 - GPIO */ + PAD_NC(GPP_I19, NONE), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + + /* GPP_H1 - GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), + + /* GPP_H2 - GPIO */ + PAD_CFG_GPO(GPP_H2, 0, DEEP), + + /* GPP_H3 - GPIO */ + PAD_NC(GPP_H3, NONE), + + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* GPP_H6 - GPIO */ + PAD_NC(GPP_H6, NONE), + + /* GPP_H7 - GPIO */ + PAD_NC(GPP_H7, NONE), + + /* GPP_H8 - I2C4_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + + /* GPP_H9 - I2C4_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* GPP_H10 - GPIO */ + PAD_NC(GPP_H10, NONE), + + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11, NONE), + + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12, NONE), + + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16, NONE), + + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - SRCCLKREQ4# */ + /* + * Some WiFi cards do not get detected if CPM is enabled. + * PAD_CFG_NF(GPP_H19, UP_20K, DEEP, NF1), + */ + PAD_NC(GPP_H19, NONE), + + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + PAD_NC(GPP_D0, NONE), + + /* GPP_D1 - GPIO */ + PAD_NC(GPP_D1, NONE), + + /* GPP_D2 - GPIO */ + PAD_NC(GPP_D2, NONE), + + /* GPP_D3 - GPIO */ + PAD_NC(GPP_D3, NONE), + + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D5, UP_20K, DEEP, NF1), + + /* GPP_D6 - SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D6, UP_20K, DEEP, NF1), + + /* GPP_D7 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D7, UP_20K, DEEP, NF1), + + /* GPP_D8 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D8, UP_20K, DEEP, NF1), + + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D12 - GPIO */ + PAD_NC(GPP_D12, NONE), + + /* GPP_D13 - GPIO */ + PAD_NC(GPP_D13, NONE), + + /* GPP_D14 - GPIO */ + PAD_NC(GPP_D14, NONE), + + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + /* ------- GPIO Group GPP_GPD ------- */ + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + + /* GPD7 - GPIO */ + PAD_CFG_GPO(GPD7, 0, PWROK), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - GPIO */ + PAD_CFG_GPO(GPD9, 0, PWROK), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + + /* GPD11 - GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), + + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + /* GPP_F2 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* GPP_F5 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF2), + + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - GPIO */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), + + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + + /* GPP_F11 - GPIO */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - TYPE_C_PD_IRQ */ + PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST), + + /* GPP_F14 - GPIO */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + PAD_NC(GPP_F17, NONE), + + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - Reserved */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - Reserved */ + PAD_NC(GPP_F21, NONE), + + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + /* GPP_L_BKLTEN - n/a */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + + /* GPP_L_BKLTCTL - n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + + /* GPP_L_VDDEN - n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + PAD_NC(GPP_E1, NONE), + + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + + /* GPP_E3 - GPIO */ + PAD_NC(GPP_E3, NONE), + + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E5 - GPIO */ + PAD_NC(GPP_E5, NONE), + + /* GPP_E6 - GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), + + /* GPP_E7 - GPIO */ + PAD_NC(GPP_E7, NONE), + + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_NC(GPP_E15, NONE), + + /* GPP_E16 - GPIO */ + PAD_NC(GPP_E16, NONE), + + /* GPP_E17 - GPIO */ + PAD_NC(GPP_E17, NONE), + + /* GPP_E18 - GPIO */ + PAD_NC(GPP_E18, NATIVE), + + /* GPP_E19 - GPIO */ + PAD_NC(GPP_E19, NATIVE), + + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NATIVE), + + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NATIVE), + + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_R ------- */ + /* GPP_R0 - GPIO */ + PAD_NC(GPP_R0, NONE), + + /* GPP_R1 - GPIO */ + PAD_NC(GPP_R1, NONE), + + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - GPIO */ + PAD_NC(GPP_R3, NONE), + + /* GPP_R4 - GPIO */ + PAD_NC(GPP_R4, NONE), + + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2440/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp2440/overridetree.cb new file mode 100644 index 00000000000..e5298567cdb --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp2440/overridetree.cb @@ -0,0 +1,111 @@ +chip soc/intel/alderlake + # FSP configuration + + device domain 0 on + device ref igpu on + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + }" + end + + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 LTE/5G (KEY_B_5G)"" + register "type" = "UPC_TYPE_INTERNAL" + register "use_custom_pld" = "false" + device ref tcss_usb3_port2 on end + end + end + end + end + + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # 5G/LTE + register "usb3_ports[1]" = "USB3_PORT_EMPTY" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + device ref usb2_port1 off end + end + chip drivers/usb/acpi + register "desc" = ""USB2 5G (KEY_B_5G)"" + register "type" = "UPC_TYPE_INTERNAL" + register "use_custom_pld" = "false" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + device ref usb3_port2 off end + end + end + end + end + + device ref sata on + register "sata_ports_enable[1]" = "1" + end + + # X710 SFP 1x4 + device ref pcie_rp1 on + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 2, + .clk_req = 2, + }" + end + + # LAN1 + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 0, + .clk_req = 0, + }" + end + + # PCIe Controller 3 is configured as 1x2,2x1 with lane reversal + + # M.2 NVMe x2 + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 3, + .clk_req = 3, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (KEY_E_WIFI)" "SlotDataBusWidth2X" + end + + # M.2 WIFI (uses CLKREQ4#, but some cards might not get detected) + device ref pcie_rp11 on + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 4, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/M 2242 (KEY_E_WIFI)" "SlotDataBusWidth1X" + end + + # LAN2 + device ref pcie_rp12 on + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 1, + .clk_req = 1, + }" + end + + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp32xx/gpio.c b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/gpio.c new file mode 100644 index 00000000000..f2b71091549 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/gpio.c @@ -0,0 +1,454 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* PAD configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_CFG_GPO(GPP_B18, 0, DEEP), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + /* GPP_A14 - USB_C_GPP_A14 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF6), + /* GPP_A15 - USB_C_GPP_A15 */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF6), + /* GPP_A16 - USB_OC3# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* GPP_A17 - GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* GPP_A20 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* GPP_A21 - USB_C_GPP_A21 */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + /* GPP_A22 - USB_C_GPP_A22 */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + /* GPP_A23 - ESPI_CS1# */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + + PAD_NC(GPP_I0, NONE), + PAD_NC(GPP_I1, NONE), + PAD_NC(GPP_I2, NONE), + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + PAD_NC(GPP_I19, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + /* GPP_H1 - GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), + /* GPP_H2 - GPIO */ + PAD_CFG_GPO(GPP_H2, 0, DEEP), + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + /* GPP_H8 - I2C4_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 - I2C4_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + PAD_NC(GPP_H16, NONE), + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* GPP_H19 - SRCCLKREQ4# */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + /* ------- GPIO Group GPP_D ------- */ + + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + /* GPP_D5 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D6 - SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPP_D7 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D8 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + /* GPD7 - GPIO */ + PAD_CFG_GPO(GPD7, 0, PWROK), + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + /* GPD9 - GPIO */ + PAD_CFG_GPO(GPD9, 0, PWROK), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + /* GPD11 - GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* GPP_C5 - GPIO */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPO(GPP_F7, 0, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + /* GPP_F15 - GPIO (5G Power_On_Off)*/ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + /* GPP_F20 - Reserved */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* GPP_F21 - Reserved */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + /* GPP_L_BKLTCTL - n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + /* GPP_L_VDDEN - n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + /* GPP_E6 - GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + /* GPP_E13 - GPIO */ + PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NATIVE), + PAD_NC(GPP_E19, NATIVE), + PAD_NC(GPP_E20, NATIVE), + PAD_NC(GPP_E21, NATIVE), + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NATIVE), + PAD_NC(GPP_R2, NATIVE), + PAD_NC(GPP_R3, NATIVE), + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb new file mode 100644 index 00000000000..de27c4650be --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb @@ -0,0 +1,84 @@ +chip soc/intel/alderlake + # FSP configuration + + device domain 0 on + device ref i2c4 on # JNTP1 header + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + end + + # NVMe x1 link or ASMedia SATA Controller + device ref pcie_rp1 on + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 4, + .clk_req = 4, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_NVME1X)" "SlotDataBusWidth1X" + end + # LAN1 + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 2, + .clk_req = 2, + }" + end + # WIFI + device ref pcie_rp4 on + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 3, + .clk_req = 3, + }" + end + # LAN2 + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 1, + .clk_req = 1, + }" + end + + # NVMe x4 link + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 0, + .clk_req = 0, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_NVME4X)" "SlotDataBusWidth4X" + end + + device ref pch_espi on + chip superio/ite/it8659e + # FAN2 is CPU fan (connector on board) + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = " 1" + register "FAN2.smart.tmp_off" = "40" + register "FAN2.smart.tmp_start" = "50" + register "FAN2.smart.tmp_full" = "85" + register "FAN2.smart.pwm_start" = "20" + register "FAN2.smart.slope" = "32" + register "FAN2.smart.tmp_delta" = "2" + + # Chip scope needs at least one device. + # Otherwise it doesn't compile. + device pnp 2e.a off end # CIR + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port6 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + end +end diff --git a/src/mainboard/protectli/vault_adl_n/vboot-rwa.fmd b/src/mainboard/protectli/vault_adl_n/vboot-rwa.fmd new file mode 100644 index 00000000000..4607a27c15d --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/vboot-rwa.fmd @@ -0,0 +1,37 @@ +FLASH@0xff000000 16M { + SI_ALL { + SI_DESC 4K + SI_ME + } + SI_BIOS@0x500000 0xb00000 { + SMMSTORE(PRESERVE) 256K + + RW_MISC 288K { + UNIFIED_MRC_CACHE(PRESERVE) { + RECOVERY_MRC_CACHE 128K + RW_MRC_CACHE 128K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + + BOOTSPLASH(CBFS) 512K + + RW_SECTION_A { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + WP_RO 5M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 0x100 + RO_FRID_PAD 0x700 + GBB 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig b/src/mainboard/protectli/vault_adl_p/Kconfig index b7578ab91bf..aa8da560753 100644 --- a/src/mainboard/protectli/vault_adl_p/Kconfig +++ b/src/mainboard/protectli/vault_adl_p/Kconfig @@ -57,6 +57,8 @@ config VBOOT select VBOOT_NO_BOARD_SUPPORT select HAS_RECOVERY_MRC_CACHE select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_NO_TPM + select VBOOT_ENABLE_CBFS_FALLBACK config VBOOT_SLOTS_RW_A default y if VBOOT diff --git a/src/mainboard/protectli/vault_adl_p/bootblock.c b/src/mainboard/protectli/vault_adl_p/bootblock.c index becc634eb7b..dd0d5dd1eac 100644 --- a/src/mainboard/protectli/vault_adl_p/bootblock.c +++ b/src/mainboard/protectli/vault_adl_p/bootblock.c @@ -27,7 +27,7 @@ static void ite_set_gpio_iobase(u16 iobase) void bootblock_mainboard_early_init(void) { /* Internal VCC_OK */ - ite_reg_write(GPIO_DEV, 0x23, 0x40); + ite_reg_write(GPIO_DEV, 0x23, 0x00); /* Set pin native functions */ ite_reg_write(GPIO_DEV, 0x26, 0xc0); /* Pin28 as GP41 - PC speaker */ diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb index 0089a5fb463..9905a222121 100644 --- a/src/mainboard/protectli/vault_adl_p/devicetree.cb +++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb @@ -248,7 +248,7 @@ chip soc/intel/alderlake chip superio/ite/it8659e register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "0x56" + register "TMPIN1.offset" = "100" register "ec.vin_mask" = "VIN0 | VIN2 | VIN3 | VIN7" # FAN1 is CPU fan (connector on board) @@ -259,6 +259,8 @@ chip soc/intel/alderlake register "FAN1.smart.tmp_full" = "85" register "FAN1.smart.pwm_start" = "20" register "FAN1.smart.slope" = "32" + register "FAN1.smart.tmp_delta" = "2" + # FAN2 is CPU fan (connector on board) register "FAN2.mode" = "FAN_SMART_AUTOMATIC" register "FAN2.smart.tmpin" = " 1" @@ -267,6 +269,7 @@ chip soc/intel/alderlake register "FAN2.smart.tmp_full" = "85" register "FAN2.smart.pwm_start" = "20" register "FAN2.smart.slope" = "32" + register "FAN2.smart.tmp_delta" = "2" device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 @@ -282,8 +285,8 @@ chip soc/intel/alderlake io 0x60 = 0xa20 io 0x62 = 0xa10 irq 0x70 = 0 # Don't use IRQ - irq 0xf4 = 0x20 # PSON_N is inverted SUSB_N - irq 0xfa = 0x20 # Enable WDT output through PWRGD + irq 0xf4 = 0x60 # Use SB to control AC power loss + irq 0xfa = 0x02 # Enable 5VSB_CTRL# end device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse diff --git a/src/mainboard/protectli/vault_adl_p/mainboard.c b/src/mainboard/protectli/vault_adl_p/mainboard.c index eef2ff9a0ec..0c94a8b4f10 100644 --- a/src/mainboard/protectli/vault_adl_p/mainboard.c +++ b/src/mainboard/protectli/vault_adl_p/mainboard.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -11,6 +12,8 @@ #include #include #include +#include +#include #include "board_beep.h" @@ -93,6 +96,39 @@ static void mainboard_final(void *chip_info) do_beep(1500, 100); } +static void set_fan_curve(struct ite_ec_fan_config *fan, uint8_t fan_curve) +{ + switch (fan_curve) { + case FAN_CURVE_OPTION_OFF: + fan->mode = FAN_MODE_OFF; + break; + case FAN_CURVE_OPTION_PERFORMANCE: + fan->smart.pwm_start += 20; + fan->smart.tmp_full -= 10; + fan->smart.tmp_off -= 10; + fan->smart.tmp_start -= 10; + break; + case FAN_CURVE_OPTION_SILENT: + /* Do nothing, it is the default */ + default: + break; + } +} + +static void mainboard_enable(struct device *dev) +{ + struct superio_ite_it8659e_config *ite_cfg; + struct device *ite_ec = dev_find_slot_pnp(0x2e, IT8659E_EC); + uint8_t fan_curve = get_fan_curve_option(); + + if (ite_ec && ite_ec->chip_info) { + ite_cfg = (struct superio_ite_it8659e_config *)ite_ec->chip_info; + set_fan_curve(&ite_cfg->ec.fan[0], fan_curve); + set_fan_curve(&ite_cfg->ec.fan[1], fan_curve); + } +} + struct chip_operations mainboard_ops = { .final = mainboard_final, + .enable_dev = mainboard_enable }; diff --git a/src/mainboard/protectli/vault_cml/Kconfig b/src/mainboard/protectli/vault_cml/Kconfig index 87de08829a8..74adcec5438 100644 --- a/src/mainboard/protectli/vault_cml/Kconfig +++ b/src/mainboard/protectli/vault_cml/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT - select HAVE_INTEL_PTT select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT @@ -48,10 +47,21 @@ config VBOOT select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select VBOOT_ALWAYS_ENABLE_DISPLAY select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_NO_TPM + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE config VBOOT_SLOTS_RW_A default y if VBOOT +config VBOOT_VBNV_OFFSET + default 0x56 + +config PRERAM_CBMEM_CONSOLE_SIZE + default 0x1000 + config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/protectli/vault_cml/Makefile.mk b/src/mainboard/protectli/vault_cml/Makefile.mk index d308320b42c..4ddb0bd6bdc 100644 --- a/src/mainboard/protectli/vault_cml/Makefile.mk +++ b/src/mainboard/protectli/vault_cml/Makefile.mk @@ -10,5 +10,8 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c ramstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -all-y += die.c + +bootblock-y += die.c +romstage-y += die.c +ramstage-y += die.c smm-y += die.c diff --git a/src/mainboard/protectli/vault_cml/cmos.layout b/src/mainboard/protectli/vault_cml/cmos.layout index b2f8e319c82..390fee855df 100644 --- a/src/mainboard/protectli/vault_cml/cmos.layout +++ b/src/mainboard/protectli/vault_cml/cmos.layout @@ -10,6 +10,10 @@ entries 395 3 e 3 debug_level 398 1 e 4 me_state 400 4 h 0 me_state_counter + +# Vboot non-volatile data +800 128 r 0 vbnv + 984 16 h 0 check_sum @@ -37,4 +41,4 @@ enumerations checksums -checksum 392 983 984 +checksum 392 799 984 diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 01c5df7724d..75c0c68cd67 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -2,7 +2,7 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep register "eist_enable" = "true" - register "cpu_pl2_4_cfg" = "baseline" + register "cpu_pl2_4_cfg" = "performance" register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x007c0a01" @@ -49,6 +49,7 @@ chip soc/intel/cannonlake register "enable_c6dram" = "1" + register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" @@ -60,6 +61,9 @@ chip soc/intel/cannonlake register "PcieRpEnable[9]" = "1" # LAN6 register "PcieRpEnable[11]" = "1" # M.2 WiFi register "PcieRpEnable[12]" = "1" # M.2 NVMe x4 + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" # Enable Advanced Error Reporting for RP 5-10, 12, 13 register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -70,6 +74,9 @@ chip soc/intel/cannonlake register "PcieRpAdvancedErrorReporting[9]" = "1" register "PcieRpAdvancedErrorReporting[11]" = "1" register "PcieRpAdvancedErrorReporting[12]" = "1" + register "PcieRpAdvancedErrorReporting[13]" = "1" + register "PcieRpAdvancedErrorReporting[14]" = "1" + register "PcieRpAdvancedErrorReporting[15]" = "1" # Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13 register "PcieRpLtrEnable[4]" = "1" @@ -80,6 +87,9 @@ chip soc/intel/cannonlake register "PcieRpLtrEnable[9]" = "1" register "PcieRpLtrEnable[11]" = "1" register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" @@ -140,7 +150,11 @@ chip soc/intel/cannonlake }" device domain 0 on - device ref igpu on end + subsystemid 0x8086 0x7270 inherit + device ref system_agent on end + device ref igpu on + subsystemid 0x8086 0x2212 + end device ref dptf on end device ref thermal on end device ref xhci on end @@ -159,6 +173,9 @@ chip soc/intel/cannonlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J1)" "SlotDataBusWidth4X" end + device ref pcie_rp14 on end + device ref pcie_rp15 on end + device ref pcie_rp16 on end device ref lpc_espi on chip superio/ite/it8784e register "TMPIN1.mode" = "THERMAL_RESISTOR" @@ -177,13 +194,13 @@ chip soc/intel/cannonlake register "FAN1.smart.tmp_delta" = " 2" register "FAN1.smart.pwm_start" = "20" register "FAN1.smart.slope" = "24" - register "FAN2.mode" = "FAN_MODE_OFF" - register "FAN3.mode" = "FAN_MODE_OFF" + register "FAN2.mode" = "FAN_MODE_OFF" + register "FAN3.mode" = "FAN_MODE_OFF" device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on end # COM 2 + device pnp 2e.2 off end # COM 2 device pnp 2e.3 off end # Printer Port device pnp 2e.4 on # Environment Controller io 0x60 = 0xa40 diff --git a/src/mainboard/protectli/vault_cml/die.c b/src/mainboard/protectli/vault_cml/die.c index 34fa75b1a3a..7a8f0bd5b16 100644 --- a/src/mainboard/protectli/vault_cml/die.c +++ b/src/mainboard/protectli/vault_cml/die.c @@ -8,7 +8,7 @@ static void beep_and_blink(void) { static uint8_t blink = 0; - static uint8_t beep_count = 0; + static uint8_t beep_count = 0;; gpio_set(GPP_E8, blink); /* Beep 12 times at most, constant beeps may be annoying */ diff --git a/src/mainboard/protectli/vault_cml/mainboard.c b/src/mainboard/protectli/vault_cml/mainboard.c index 1e06fc5feee..5bcc921533c 100644 --- a/src/mainboard/protectli/vault_cml/mainboard.c +++ b/src/mainboard/protectli/vault_cml/mainboard.c @@ -1,41 +1,51 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include -#include +#include +#include #include -#include -#include +#include +#include +#include #include -#include +#include +#include #include -#include +#include #include +#include +#include #include -static bool need_global_reset = false; - -/* Flash Master 1 : HOST/BIOS */ -#define FLMSTR1 0x80 - -#define FLASH_SIGNATURE_OFFSET 0x10 -#define FLMSTR_WR_SHIFT_V2 20 -#define FLASH_SIGNATURE_VAL 0x0FF0A55A - -#define SI_DESC_SIZE (4 * KiB) -#define SI_DESC_REGION "SI_DESC" +#include "gpio.h" const char *smbios_mainboard_product_name(void) { - char processor_name[49]; - - fill_processor_name(processor_name); + u32 tmp[13]; + const char *str = "Unknown Processor Name"; + + if (cpu_have_cpuid()) { + int i; + struct cpuid_result res = cpuid(0x80000000); + if (res.eax >= 0x80000004) { + int j = 0; + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + tmp[j++] = res.eax; + tmp[j++] = res.ebx; + tmp[j++] = res.ecx; + tmp[j++] = res.edx; + } + tmp[12] = 0; + str = (const char *)tmp; + } + } - if (strstr(processor_name, "i3-10110U") != NULL) + if (strstr(str, "i3-10110U") != NULL) return "VP4630"; - else if (strstr(processor_name, "i5-10210U") != NULL) + else if (strstr(str, "i5-10210U") != NULL) return "VP4650"; - else if (strstr(processor_name, "i7-10810U") != NULL) + else if (strstr(str, "i7-10810U") != NULL) return "VP4670"; else return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; @@ -43,85 +53,49 @@ const char *smbios_mainboard_product_name(void) static void mainboard_final(void *unused) { + if (CONFIG(BEEP_ON_BOOT)) beep(1500, 100); } -/* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */ -static bool is_descriptor_writeable(uint8_t *desc) -{ - /* Check flash has valid signature */ - if (read32((void *)(desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) { - printk(BIOS_ERR, "Flash Descriptor is not valid\n"); - printk(BIOS_ERR, "Descriptor needs to be fixed to ensure proper operation\n"); - return false; - } - - /* Check host has write access to the Descriptor Region */ - if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { - printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); - return false; - } - - return true; -} +struct chip_operations mainboard_ops = { + .final = mainboard_final, +}; -static void configure_descriptor_for_lpc_tpm(void) +void mainboard_silicon_init_params(FSPS_UPD *supd) { - uint8_t si_desc_buf[SI_DESC_SIZE]; - struct region_device desc_rdev; - - if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { - printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); - return; + struct soc_power_limits_config *soc_conf; + config_t *conf = config_of_soc(); + uint16_t sa_devid = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); + + soc_conf = &conf->power_limits_config; + + if (sa_devid == PCI_DID_INTEL_CML_ULT_2_2) { /* VP4630 */ + soc_conf->tdp_pl2_override = 35; + soc_conf->tdp_pl4 = 51; + soc_conf->psys_pmax = 60; + } else if (sa_devid == PCI_DID_INTEL_CML_ULT) { /* VP4650 */ + soc_conf->tdp_pl2_override = 64; + soc_conf->tdp_pl4 = 90; + soc_conf->psys_pmax = 100; + } else if (sa_devid == PCI_DID_INTEL_CML_ULT_6_2) { /* VP4670 */ + soc_conf->tdp_pl1_override = 25; + soc_conf->tdp_pl2_override = 85; + soc_conf->tdp_pl4 = 90; + soc_conf->psys_pmax = 100; } - if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { - printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); - return; - } - - if (!is_descriptor_writeable(si_desc_buf)) - return; - - /* Disable SPI TPM if necessary */ - if ((si_desc_buf[0x1f0] & 0xfe) == si_desc_buf[0x1f0]) { - printk(BIOS_DEBUG, "Update of Descriptor is not required!\n"); - return; - } - - si_desc_buf[0x1f0] &= 0xfe; - - if (rdev_eraseat(&desc_rdev, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { - printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); - return; - } - - if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { - printk(BIOS_ERR, "Failed to update Descriptor Region\n"); - return; - } - - printk(BIOS_DEBUG, "Update of Descriptor successful\n"); - need_global_reset = true; + supd->FspsTestConfig.PkgCStateLimit = 0; + supd->FspsTestConfig.PkgCStateDemotion = 0; + supd->FspsTestConfig.PkgCStateUnDemotion = 0; + supd->FspsTestConfig.C1StateAutoDemotion = 0; + supd->FspsTestConfig.C1StateUnDemotion = 0; + supd->FspsTestConfig.C3StateAutoDemotion = 0; + supd->FspsTestConfig.C3StateUnDemotion = 0; + supd->FspsTestConfig.PowerLimit3Lock = 0; + supd->FspsTestConfig.PowerLimit3 = 0; + supd->FspsTestConfig.PowerLimit3Time = 0; + supd->FspsTestConfig.PowerLimit3DutyCycle = 0; + + supd->FspsConfig.TxtEnable = CONFIG(INTEL_TXT); } - -void mainboard_silicon_init_params(FSPS_UPD *supd) -{ - /* Call it right before Silicon Init, so that we avoid EOP */ - configure_descriptor_for_lpc_tpm(); - cse_enable_ptt(false); - /* - * We wait with global reset after descriptor update until PTT state change to avoid - * double global reset. In case PTT was already disabled or cse_enable_ptt will fail - * for some reason, but descriptor has been updated we need to do global reset here, - * otherwise cse_enable_ptt will do the global reset and the branch below won't be - * reached. - */ - if (need_global_reset) - do_global_reset(); -} - -struct chip_operations mainboard_ops = { - .final = mainboard_final, -}; diff --git a/src/mainboard/protectli/vault_cml/romstage.c b/src/mainboard/protectli/vault_cml/romstage.c index 453566234a8..34a0bd6476c 100644 --- a/src/mainboard/protectli/vault_cml/romstage.c +++ b/src/mainboard/protectli/vault_cml/romstage.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include #include +#include static const struct cnl_mb_cfg board_memcfg_cfg = { /* Access memory info through SMBUS. */ @@ -41,4 +45,24 @@ static const struct cnl_mb_cfg board_memcfg_cfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { cannonlake_memcfg_init(&memupd->FspmConfig, &board_memcfg_cfg); + +/* Use pre-processor because CONFIG_INTEL_TXT_CBFS_BIOS_ACM is not defined otherwise */ +#if CONFIG(INTEL_TXT) + size_t acm_size = 0; + uintptr_t acm_base; + + intel_txt_log_bios_acm_error(); + + acm_base = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, &acm_size); + + memupd->FspmConfig.TxtImplemented = 1; + memupd->FspmConfig.Txt = 1; + memupd->FspmConfig.SinitMemorySize = CONFIG_INTEL_TXT_SINIT_SIZE; + memupd->FspmConfig.TxtHeapMemorySize = CONFIG_INTEL_TXT_HEAP_SIZE; + memupd->FspmConfig.TxtDprMemorySize = CONFIG_INTEL_TXT_DPR_SIZE << 20; + memupd->FspmConfig.TxtDprMemoryBase = 1; // Set to non-zero, FSP will update it + memupd->FspmConfig.BiosAcmBase = acm_base; + memupd->FspmConfig.BiosAcmSize = acm_size; + memupd->FspmConfig.ApStartupBase = 1; // Set to non-zero, FSP does NULL check +#endif } diff --git a/src/mainboard/protectli/vault_cml/vboot-rwa.fmd b/src/mainboard/protectli/vault_cml/vboot-rwa.fmd index b5c233f3832..8ae286e5d07 100644 --- a/src/mainboard/protectli/vault_cml/vboot-rwa.fmd +++ b/src/mainboard/protectli/vault_cml/vboot-rwa.fmd @@ -17,24 +17,22 @@ FLASH@0xff000000 0x1000000 { RW_NVRAM(PRESERVE) 24K } - CONSOLE 0x20000 + BOOTSPLASH(CBFS) 512K RW_SECTION_A { VBLOCK_A 0x2000 FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + RW_FWID_A 0x100 } - # T/B = 0 - # BP3 = 0 BP2 = 1 BP1 = 1 BP0 = 1 - WP_RO@0xC00000 0x400000 { + WP_RO 0x480000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { + RO_SECTION@0x4000 { FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + RO_FRID@0x800 0x100 + RO_FRID_PAD@0x900 0x700 GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 + COREBOOT(CBFS)@0x4000 } } } diff --git a/src/mainboard/protectli/vault_ehl/Kconfig b/src/mainboard/protectli/vault_ehl/Kconfig index 5f283eed32d..e5b0f669444 100644 --- a/src/mainboard/protectli/vault_ehl/Kconfig +++ b/src/mainboard/protectli/vault_ehl/Kconfig @@ -32,6 +32,9 @@ config CBFS_SIZE config DIMM_MAX default 1 +config DIMM_SPD_SIZE + default 512 + config VBOOT select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_FWMP @@ -39,9 +42,12 @@ config VBOOT select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select VBOOT_ALWAYS_ENABLE_DISPLAY select VBOOT_NO_BOARD_SUPPORT + select VBOOT_NO_TPM select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - select VBOOT_SEPARATE_VERSTAGE + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE config VBOOT_SLOTS_RW_A default y if VBOOT @@ -49,4 +55,11 @@ config VBOOT_SLOTS_RW_A config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 5 + +endif + endif # BOARD_PROTECTLI_VP2420 diff --git a/src/mainboard/protectli/vault_ehl/acpi/superio.asl b/src/mainboard/protectli/vault_ehl/acpi/superio.asl new file mode 100644 index 00000000000..7127793fe44 --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/acpi/superio.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8613E_SHOW_UARTA +#undef IT8613E_SHOW_KBC +#undef IT8613E_SHOW_PS2M +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8613E_SHOW_UARTA 1 + +#include diff --git a/src/mainboard/protectli/vault_ehl/bootblock.c b/src/mainboard/protectli/vault_ehl/bootblock.c index 11bd669f0b6..e45fb8bfa03 100644 --- a/src/mainboard/protectli/vault_ehl/bootblock.c +++ b/src/mainboard/protectli/vault_ehl/bootblock.c @@ -11,7 +11,10 @@ void bootblock_mainboard_early_init(void) { ite_reg_write(GPIO_DEV, 0x29, 0xc1); + ite_reg_write(GPIO_DEV, 0x2a, 0x00); /* Disable FAN_CTL4 */ ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK=25MHz */ + ite_kill_watchdog(GPIO_DEV); ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index 10782b265d1..e71a9d72e7b 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -1,3 +1,4 @@ + chip soc/intel/elkhartlake #register "enable_vtd" = "1" @@ -82,7 +83,7 @@ chip soc/intel/elkhartlake register "DdiPortADdc" = "1" register "DdiPortBDdc" = "1" - device cpu_cluster 0 on end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -182,13 +183,24 @@ chip soc/intel/elkhartlake device pci 1e.7 off end # IOAPIC device pci 1f.0 on # eSPI interface + # LPC generic I/O ranges + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c0081" + chip superio/ite/it8613e - device pnp 2e.0 off end - device pnp 2e.1 on # COM 1 + device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 irq 0x70 = 4 + irq 0xf0 = 1 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa20 + io 0x62 = 0xa10 + irq 0x70 = 0 # Don't use IRQ + irq 0xf0 = 0x80 # Clear 3VSB off status + irq 0xf4 = 0x60 # Use SB to control AC power loss end - device pnp 2e.4 off end # Environment Controller device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse device pnp 2e.7 off end # GPIO diff --git a/src/mainboard/protectli/vault_ehl/die.c b/src/mainboard/protectli/vault_ehl/die.c index 00366dcad96..4d38a280eb2 100644 --- a/src/mainboard/protectli/vault_ehl/die.c +++ b/src/mainboard/protectli/vault_ehl/die.c @@ -2,6 +2,7 @@ #include #include +#include #include #include diff --git a/src/mainboard/protectli/vault_ehl/dsdt.asl b/src/mainboard/protectli/vault_ehl/dsdt.asl index b60f57b2380..f0603388229 100644 --- a/src/mainboard/protectli/vault_ehl/dsdt.asl +++ b/src/mainboard/protectli/vault_ehl/dsdt.asl @@ -24,5 +24,9 @@ DefinitionBlock( } } + Scope (\_SB.PCI0.LPCB) { + #include "acpi/superio.asl" + } + #include } diff --git a/src/mainboard/protectli/vault_ehl/mainboard.c b/src/mainboard/protectli/vault_ehl/mainboard.c index 388a4e40fc8..9163984edf2 100644 --- a/src/mainboard/protectli/vault_ehl/mainboard.c +++ b/src/mainboard/protectli/vault_ehl/mainboard.c @@ -10,9 +10,16 @@ static void mainboard_final(void *chip_info) beep(1500, 200); } - void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) { + /* + * HWP is too aggressive in power savings and does not let using full + * bandwidth of Ethernet controllers without additional stressing of + * the CPUs (2Gb/s vs 2.35Gb/s with stressing, measured with iperf3). + * Let the Linux use acpi-cpufreq governor driver instead of + * intel_pstate by disabling HWP. + */ + silconfig->Hwp = 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/protectli/vault_ehl/romstage.c b/src/mainboard/protectli/vault_ehl/romstage.c index 7bd1aaffe23..d4e5d04a20e 100644 --- a/src/mainboard/protectli/vault_ehl/romstage.c +++ b/src/mainboard/protectli/vault_ehl/romstage.c @@ -28,7 +28,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); get_spd_smbus(&blk); - dump_spd_info(&blk); if (blk.spd_array[0] == NULL) die("No memory detected. Insert DIMM module"); diff --git a/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd b/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd index 3d5a61c62ab..f1f7679a4ac 100644 --- a/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd +++ b/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd @@ -19,18 +19,20 @@ FLASH 16M { CONSOLE 0x20000 + BOOTSPLASH(CBFS) 1M + RW_SECTION_A { VBLOCK_A 0x2000 FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + RW_FWID_A 0x100 } WP_RO@0xC00000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + RO_FRID@0x800 0x100 + RO_FRID_PAD@0x900 0x700 GBB@0x1000 0x3000 COREBOOT(CBFS)@0x4000 0x3f8000 } diff --git a/src/mainboard/protectli/vault_glk/Kconfig b/src/mainboard/protectli/vault_glk/Kconfig new file mode 100644 index 00000000000..fb37ae42666 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/Kconfig @@ -0,0 +1,68 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_PROTECTLI_VP2410 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_GEMINILAKE + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MEMORY_MAPPED_TPM + select SUPERIO_ITE_IT8613E + select SPI_FLASH_MACRONIX + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select NEED_IFWI + +config MAINBOARD_DIR + string + default "protectli/vault_glk" + +config DEVICETREE + string + default "devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "VP2410" + +config MAINBOARD_FAMILY + default "Vault Pro" + +config DIMM_MAX + default 1 + +config DIMM_SPD_SIZE + default 512 + +config MAX_CPUS + default 4 + +config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + default y + +config USE_LEGACY_8254_TIMER + default y + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" if !VBOOT + +config BEEP_ON_BOOT + bool "Beep on successful boot" + default y + help + Make the platform beep using the PC speaker in final coreboot phase. + May serve as a useful indicator in headless mode that platform is + properly booting. + +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 5 + +endif + +endif # BOARD_PROTECTLI_VP2410 diff --git a/src/mainboard/protectli/vault_glk/Kconfig.name b/src/mainboard/protectli/vault_glk/Kconfig.name new file mode 100644 index 00000000000..f246bcb4dfd --- /dev/null +++ b/src/mainboard/protectli/vault_glk/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_PROTECTLI_VP2410 + bool "VP2410" diff --git a/src/mainboard/protectli/vault_glk/Makefile.mk b/src/mainboard/protectli/vault_glk/Makefile.mk new file mode 100644 index 00000000000..9680cbeeef2 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/Makefile.mk @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c + +bootblock-y += die.c +romstage-y += die.c +ramstage-y += die.c +smm-y += die.c diff --git a/src/mainboard/protectli/vault_glk/acpi/superio.asl b/src/mainboard/protectli/vault_glk/acpi/superio.asl new file mode 100644 index 00000000000..7127793fe44 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/acpi/superio.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8613E_SHOW_UARTA +#undef IT8613E_SHOW_KBC +#undef IT8613E_SHOW_PS2M +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8613E_SHOW_UARTA 1 + +#include diff --git a/src/mainboard/protectli/vault_glk/board.fmd b/src/mainboard/protectli/vault_glk/board.fmd new file mode 100644 index 00000000000..b7d4c8328af --- /dev/null +++ b/src/mainboard/protectli/vault_glk/board.fmd @@ -0,0 +1,24 @@ +FLASH 8M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0x6fe000 { + IFWI@0x0 0x2ff000 + OBB@0x2ff000 0x3ff000 { + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + BOOTSPLASH(CBFS) 0x80000 + WP_RO { + FMAP 0x1000 + COREBOOT(CBFS) + } + SMMSTORE(PRESERVE) 0x40000 + BIOS_UNUSABLE 0x40000 + } + } + SI_DEVICEEXT@0x6ff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/mainboard/protectli/vault_glk/board_info.txt b/src/mainboard/protectli/vault_glk/board_info.txt new file mode 100644 index 00000000000..c06641a55e3 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: VP2410 +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault_glk/bootblock.c b/src/mainboard/protectli/vault_glk/bootblock.c new file mode 100644 index 00000000000..f90ed342e04 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/bootblock.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x25, 0x05); /* PCIRST1# and PCIRST3# as GPIO */ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */ + + ite_reg_write(GPIO_DEV, 0xc0, 0x05); /* PCIRST3# and 5VSB_CTRL GPIO Simple I/O */ + ite_reg_write(GPIO_DEV, 0xc1, 0x02); /* GP22 GPIO Simple I/O */ + ite_reg_write(GPIO_DEV, 0xc9, 0x02); /* GP22 GPIO output */ + + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/protectli/vault_glk/data.vbt b/src/mainboard/protectli/vault_glk/data.vbt new file mode 100644 index 00000000000..e9aaa197bcf Binary files /dev/null and b/src/mainboard/protectli/vault_glk/data.vbt differ diff --git a/src/mainboard/protectli/vault_glk/devicetree.cb b/src/mainboard/protectli/vault_glk/devicetree.cb new file mode 100644 index 00000000000..2869a88e0f9 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/devicetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/apollolake + # Assign first CLKREQ numbers to the used ports, rest don't care. + # FSP sets the CLKREQ despite passing PcieRpClkReqSupported as disabled + # So we must use the only 4 CLKREQ pins we have for the used ports + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "0" + register "pcie_rp_clkreq_pin[3]" = "1" + register "pcie_rp_clkreq_pin[4]" = "2" + register "pcie_rp_clkreq_pin[5]" = "3" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C3A" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28272929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x003B263B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + register "emmc_rx_strobe_cntl" = "0x0a0a" + register "emmc_tx_cmd_cntl" = "0x1305" + + register "enable_vtd" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 15, + }" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_SCC_63_32" + register "gpe0_dw2" = "PMC_GPE_N_31_0" + register "gpe0_dw3" = "PMC_GPE_SCC_31_0" + + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + register "pnp_settings" = "PNP_PERF_POWER" + register "tcc_offset" = "5" # TCC of 95C + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # USB configuration + register "usb_config_override" = "1" + register "disable_compliance_mode" = "1" + register "disable_xhci_lfps_pm" = "0" + register "mod_phy_if_value" = "0x16" + + register "usb2_port[0]" = "PORT_EN(OC_SKIP)" # USB3.0 Type A + register "usb2_port[1]" = "PORT_EN(OC_SKIP)" # USB3.0 Type A + register "usb2_port[2]" = "PORT_EN(OC_SKIP)" # USB3.0 Type C + register "usb2_port[3]" = "PORT_EN(OC_SKIP)" # M.2 WiFi + register "usb2_port[4]" = "PORT_EN(OC_SKIP)" # mPCIe LTE + register "usb2_port[5]" = "PORT_DIS" + register "usb2_port[6]" = "PORT_DIS" + register "usb2_port[7]" = "PORT_DIS" + + register "usb3_port[0]" = "PORT_EN(OC_SKIP)" # USB3.0 Type A + register "usb3_port[1]" = "PORT_EN(OC_SKIP)" # USB3.0 Type A + register "usb3_port[2]" = "PORT_EN(OC_SKIP)" # USB3.0 Type C + register "usb3_port[3]" = "PORT_DIS" + register "usb3_port[4]" = "PORT_DIS" + register "usb3_port[5]" = "PORT_DIS" + + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" + register "sata_ports_ssd[0]" = "1" + + device cpu_cluster 0 on end + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen + device pci 0c.0 off end # - CNVi + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - Heci1 + device pci 0f.1 off end # - Heci2 + device pci 0f.2 off end # - Heci3 + device pci 11.0 off end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 LAN1 + device pci 13.1 on end # - PCIe-A 1 LAN2 + device pci 13.2 on end # - PCIe-A 2 ASMedia Switch: LAN3/WiFi + device pci 13.3 on end # - PCIe-A 3 LAN4 + device pci 14.0 off end # - PCIe-B 0 + device pci 14.1 off end # - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 off end # - I2C 0 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 + device pci 18.0 off end # - UART 0 + device pci 18.1 off end # - UART 1 + device pci 18.2 off end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 9 + irq 0xf0 = 0x80 # Clear 3VSB + irq 0xf1 = 0x80 # Clear AVCC3 + irq 0xf4 = 0x60 # Use SB to control AC power loss + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa10 + io 0x62 = 0xa00 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/protectli/vault_glk/die.c b/src/mainboard/protectli/vault_glk/die.c new file mode 100644 index 00000000000..f46c6f9a9a4 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/die.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void beep_and_blink(void) +{ + static uint8_t blink = 0; + static uint8_t beep_count = 0; + + gpio_set(GPIO_142, blink); + /* Beep 12 times at most, constant beeps may be annoying */ + if (beep_count < 12) { + beep(800, 300); + mdelay(200); + beep_count++; + } else { + mdelay(500); + } + + blink ^= 1; +} + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink and use PC SPKR */ + gpio_output(GPIO_142, 0); + + while (1) { + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + delay(2); + } +} diff --git a/src/mainboard/protectli/vault_glk/dsdt.asl b/src/mainboard/protectli/vault_glk/dsdt.asl new file mode 100644 index 00000000000..0ff068f43a0 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + /* global NVS and variables */ + #include + + /* CPU */ + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + #include + } + } + + #include +} diff --git a/src/mainboard/protectli/vault_glk/gpio.h b/src/mainboard/protectli/vault_glk/gpio.h new file mode 100644 index 00000000000..7058ae51bf9 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/gpio.h @@ -0,0 +1,483 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include + +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT_IOS +#define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#endif + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ----- GPIO Community NorthWest ----- */ + + /* ------- GPIO Group NorthWest ------- */ + + /* GPIO_0 - JTAG_TCK */ + PAD_CFG_NF(GPIO_0, DN_20K, DEEP, NF1), + /* GPIO_1 - JTAG_TRST_N */ + PAD_CFG_NF(GPIO_1, DN_20K, DEEP, NF1), + /* GPIO_2 - JTAG_TMS */ + PAD_CFG_NF(GPIO_2, UP_20K, DEEP, NF1), + /* GPIO_3 - JTAG_TDI */ + PAD_CFG_NF(GPIO_3, UP_20K, DEEP, NF1), + /* GPIO_4 - JTAG_TDO */ + PAD_CFG_NF(GPIO_4, UP_20K, DEEP, NF1), + /* GPIO_5 - JTAGX */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_6 - JTAG_PREQ_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_7 - JTAG_PRDY_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_8 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_9 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_10 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_11 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_12 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_13 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, ENPD), + /* GPIO_14 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, ENPD), + /* GPIO_15 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, ENPD), + /* GPIO_16 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, ENPD), + /* GPIO_17 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_17, 0, DEEP, UP_20K, TxDRxE, ENPU), + /* GPIO_18 - GPIO */ + PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, ENPU), + /* GPIO_19 - GPIO */ + PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, ENPU), + /* GPIO_20 - GPIO */ + PAD_CFG_GPI_APIC_IOS(GPIO_20, NONE, DEEP, LEVEL, NONE, IGNORE, SAME), + /* GPIO_21 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_21, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_22 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_22, 1, DEEP, UP_20K, TxDRxE, ENPU), + /* GPIO_23 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_23, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_24 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_24, UP_20K, DEEP, OFF, TxLASTRxE, ENPU, ACPI), + /* GPIO_25 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_26 - GPIO */ + PAD_CFG_GPI_SCI_IOS(GPIO_26, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, ENPU), + /* GPIO_27 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD), + /* GPIO_28 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_29 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx1, DISPUPD), + /* GPIO_30 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_31 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_32 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_33 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_34 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_35 - SPKR */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, UP_20K, DEEP, NF4, IGNORE, ENPU), + /* GPIO_36 - BSSB_DI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, UP_20K, DEEP, NF6, IGNORE, ENPU), + /* GPIO_37 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_38 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_39 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_40 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_40, UP_20K, DEEP, IGNORE, ENPU), + /* GPIO_41 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_42 - MDSI_A_TE */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_43 - MDSI_C_TE */ + PAD_CFG_NF(GPIO_43, NONE, DEEP, NF1), + /* GPIO_44 - USB2_OC0_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_45 - USB2_OC1_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_46 - MIPI_I2C_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, NONE, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_47 - MIPI_I2C_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, NONE, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_48 - PMC_I2C_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, UP_1K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_49 - PMC_I2C_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_1K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_50 - SIO_I2C0_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_51 - SIO_I2C0_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_52 - SIO_I2C1_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_53 - SIO_I2C1_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_54 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_54, UP_1K, DEEP, HIZCRx1, ENPU), + /* GPIO_55 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_55, UP_1K, DEEP, HIZCRx1, ENPU), + /* GPIO_56 - SIO_I2C3_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_57 - SIO_I2C3_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_58 - SIO_I2C4_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_59 - SIO_I2C4_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_60 - SIO_UART0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_61 - SIO_UART0_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_62 - SIO_UART0_RTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_62, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_63 - SIO_UART0_CTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_63, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_64 - SIO_UART2_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_65 - SIO_UART2_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_66 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_67 - SIO_UART2_CTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_67, NONE, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_68 - PMC_SPI_FS0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_68, UP_20K, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_69 - PMC_SPI_FS1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_69, NONE, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_70 - PMC_SPI_FS2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_70, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_71 - PMC_SPI_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_71, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_72 - PMC_SPI_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_72, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_73 - PMC_SPI_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_73, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_74 - THERMTRIP_N */ + PAD_CFG_NF(GPIO_74, UP_20K, DEEP, NF1), + /* GPIO_75 - PROCHOT_N */ + PAD_CFG_NF(GPIO_75, UP_20K, DEEP, NF1), + /* GPIO_211 - RESERVED */ + /* GPIO_212 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_212, UP_20K, DEEP, OFF, HIZCRx0, ENPU, ACPI), + /* GPIO_213 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 1, DEEP, UP_20K, HIZCRx0, ENPU), + /* GPIO_214 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_214, 1, DEEP, NONE, IGNORE, SAME), + + /* --- GPIO Community North --- */ + + /* ----- GPIO Group North ----- */ + + /* GPIO_76 - SVID0_ALERT_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_76, NONE, DEEP, NF1), + /* GPIO_77 - SVID0_DATA */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_77, NONE, DEEP, NF1), + /* GPIO_78 - SVID0_CLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_78, NONE, DEEP, NF1), + /* GPIO_79 - SIO_SPI_0_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_80 - SIO_SPI_0_FS0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_81 - FST_SPI_CS2_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_81, NONE, DEEP, NF3), + /* GPIO_82 - SIO_SPI_0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_82, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_83 - SIO_SPI_0_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_83, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_84 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_84, DN_20K, DEEP, OFF, ACPI), + /* GPIO_85 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_85, DN_20K, DEEP, TxLASTRxE, SAME), + /* GPIO_86 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_86, DN_20K, DEEP, TxLASTRxE, SAME), + /* GPIO_87 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_87, DN_20K, DEEP, TxLASTRxE, SAME), + /* GPIO_88 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_88, DN_20K, DEEP, OFF, ACPI), + /* GPIO_89 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_89, DN_20K, DEEP, OFF, ACPI), + /* GPIO_90 - FST_SPI_CS0_N */ + PAD_CFG_NF(GPIO_90, NATIVE, DEEP, NF1), + /* GPIO_91 - FST_SPI_CS1_N */ + PAD_CFG_NF(GPIO_91, NATIVE, DEEP, NF1), + /* GPIO_92 - FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_92, NATIVE, DEEP, NF1), + /* GPIO_93 - FST_SPI_MISO_IO1 */ + PAD_CFG_NF(GPIO_93, NATIVE, DEEP, NF1), + /* GPIO_94 - FST_SPI_IO2 */ + PAD_CFG_NF(GPIO_94, NATIVE, DEEP, NF1), + /* GPIO_95 - FST_SPI_IO3 */ + PAD_CFG_NF(GPIO_95, NATIVE, DEEP, NF1), + /* GPIO_96 - FST_SPI_CLK */ + PAD_CFG_NF(GPIO_96, NATIVE, DEEP, NF1), + /* GPIO_97 - FST_SPI_CLK_FB */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + /* GPIO_98 - PMU_PLTRST_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1), + /* GPIO_99 - PMU_PWRBTN_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_100 - PMU_SLP_S0_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1), + /* GPIO_101 - PMU_SLP_S3_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1), + /* GPIO_102 - PMU_SLP_S4_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1), + /* GPIO_103 - SUSPWRDNACK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1), + /* GPIO_104 - EMMC_PWR_EN_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_105 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_106 - PMU_BATLOW_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_107 - PMU_RSTBTN_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_108 - PMU_SUSCLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1), + /* GPIO_109 - SUS_STAT_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1), + /* GPIO_110 - ISH_I2C0_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_1K, DEEP, NF2, IGNORE, ENPU), + /* GPIO_111 - ISH_I2C0_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, UP_1K, DEEP, NF2, IGNORE, ENPU), + /* GPIO_112 - ISH_I2C1_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, UP_1K, DEEP, NF2, IGNORE, ENPU), + /* GPIO_113 - ISH_I2C1_ScL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, UP_1K, DEEP, NF2, IGNORE, ENPU), + /* GPIO_114 - SIO_I2C7_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_115 - SIO_I2C7_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_116 - PCIE_WAKE0_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_116, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_117 - PCIE_WAKE1_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_118 - PCIE_WAKE2_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_118, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_119 - PCIE_WAKE3_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_120 - PCIE_CLKREQ0_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_121 - PCIE_CLKREQ1_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_122 - PCIE_CLKREQ2_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_123 - PCIE_CLKREQ3_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_124 - DDI0_DDC_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, NONE, DEEP, NF1, HIZCRx0, ENPU), + /* GPIO_125 - DDI0_DDC_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, NONE, DEEP, NF1, HIZCRx0, ENPU), + /* GPIO_126 - DDI1_DDC_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0, ENPU), + /* GPIO_127 - DDI1_DDC_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0, ENPU), + /* GPIO_128 - PNL0_VDDEN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, DN_20K, DEEP, NF1, Tx0RxDCRx0, ENPD), + /* GPIO_129 - PNL0_BKLTEN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, DN_20K, DEEP, NF1, Tx0RxDCRx0, ENPD), + /* GPIO_130 - PNL0_BKLCTL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, DN_20K, DEEP, NF1, Tx0RxDCRx0, ENPD), + /* GPIO_131 - DDI0_HPD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_20K, DEEP, NF1, TxDRxE, ENPU), + /* GPIO_132 - DDI1_HPD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_20K, DEEP, NF1, TxDRxE, ENPU), + /* GPIO_133 - DDI2_HPD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, TxDRxE, ENPU), + /* GPIO_134 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_135 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_136 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 0, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_137 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_138 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_138, 1, DEEP, NONE, TxLASTRxE, ENPU), + /* GPIO_139 - SATA_GP1 */ + PAD_CFG_NF(GPIO_139, NONE, DEEP, NF5), + /* GPIO_140 - SATA_DEVSLP0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_140, DN_20K, DEEP, NF5, TxLASTRxE, ENPD), + /* GPIO_141 - GPIO */ + PAD_CFG_GPIO_BIDIRECT_IOS(GPIO_141, 0, NONE, DEEP, OFF, HIZCRx1, ENPU, ACPI), + /* GPIO_142 - SATA_LEDN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1, ENPU), + /* GPIO_143 - GPIO */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_143, NONE, DEEP, OFF, HIZCRx1, ACPI), + /* GPIO_144 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_144, 0, DEEP, DN_20K, HIZCRx1, ENPD), + /* GPIO_145 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_145, 0, DEEP, DN_20K, HIZCRx1, ENPD), + /* GPIO_146 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1, ENPU), + /* GPIO_147 - LPC_SERIRQ */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_147, UP_20K, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_148 - LPC_CLKOUT0 */ + PAD_CFG_NF_IOSSTATE(GPIO_148, NONE, DEEP, NF1, HIZCRx1), + /* GPIO_149 - LPC_CLKOUT1 */ + PAD_CFG_NF_IOSSTATE(GPIO_149, NONE, DEEP, NF1, HIZCRx1), + /* GPIO_150 - LPC_AD0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_151 - LPC_AD1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_152 - LPC_AD2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_153 - LPC_AD3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_154 - LPC_CLKRUN_N */ + PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1), + /* GPIO_155 - LPC_FRAME_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + + /* --- GPIO Community Audio --- */ + + /* ----- GPIO Group Audio ----- */ + + /* GPIO_156 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_156, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_157 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_157, DN_20K, DEEP, OFF, IGNORE, ENPD, ACPI), + /* GPIO_158 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, ENPD), + /* GPIO_159 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, UP_20K, TxDRxE, DISPUPD), + /* GPIO_160 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 0, DEEP, DN_20K, IGNORE, ENPD), + /* GPIO_161 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_162 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_162, UP_20K, DEEP, IGNORE, ENPU), + /* GPIO_163 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_163, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_164 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, UP_5K, TxDRxE, ENPU), + /* GPIO_165 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_165, DN_20K, DEEP, OFF, IGNORE, ENPD, ACPI), + /* GPIO_166 - AVS_HDA_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_167 - AVS_HDA_WS_SYNC */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_168 - AVS_HDA_SDI */ + PAD_CFG_NF_IOSSTATE(GPIO_168, NONE, DEEP, NF1, HIZCRx1), + /* GPIO_169 - AVS_HDA_SDO */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_170 - AVS_HDA_RST_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_171 - AVS_DMIC_CLK_A1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_171, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_172 - AVS_DMIC_CLK_B1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_173 - AVS_DMIC_DATA_1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_174 - AVS_DMIC_CLK_AB2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_175 - AVS_DMIC_DATA_2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + + /* --- GPIO Community SCC --- */ + + /* ----- GPIO Group SCC ----- */ + + /* GPIO_176 - SMB_ALERT_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_176, UP_20K, PWROK, NF1, IGNORE, ENPU), + /* GPIO_177 - SMB_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_177, UP_5K, PWROK, NF1, IGNORE, ENPU), + /* GPIO_178 - SMB_DATA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_5K, PWROK, NF1, IGNORE, ENPU), + /* GPIO_187 - SDCARD_LVL_WP */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_187, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_179 - SDCARD_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_179, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* GPIO_180 - SDCARD_CLK_FB */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_180, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_181 - SDCARD_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_181, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_182 - SDCARD_D1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_182, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_183 - SDCARD_D2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_183, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_184 - SDCARD_D3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_184, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_185 - SDCARD_CMD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_185, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_186 - GPIO */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_186, NONE, DEEP, EDGE_SINGLE, TxDRxE, ACPI), + /* GPIO_188 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_188, 0, DEEP, DN_20K, TxLASTRxE, ENPD), + /* GPIO_210 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 1, DEEP, UP_20K, HIZCRx0, ENPD), + /* GPIO_189 - OSC_CLK_OUT_0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* GPIO_190 - OSC_CLK_OUT_1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* GPIO_191 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_191, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_192 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_192, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_193 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_193, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_194 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_194, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_195 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_195, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_196 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_196, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_197 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_197, DN_20K, DEEP, NF2, TxLASTRxE, ENPD), + /* GPIO_198 - EMMC_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* GPIO_199 - EMMC_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_199, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_200 - EMMC_D1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_201 - EMMC_D2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_202 - EMMC_D3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_203 - EMMC_D4 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_204 - EMMC_D5 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_205 - EMMC_D6 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_206 - EMMC_D7 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_207 - EMMC_CMD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_208 - EMMC_RCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_209 - EMMC_RST_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPD) +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/protectli/vault_glk/hda_verb.c b/src/mainboard/protectli/vault_glk/hda_verb.c new file mode 100644 index 00000000000..9a7345b29ba --- /dev/null +++ b/src/mainboard/protectli/vault_glk/hda_verb.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* GeminiLake HDMI */ + 0x8086280d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010) +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault_glk/mainboard.c b/src/mainboard/protectli/vault_glk/mainboard.c new file mode 100644 index 00000000000..341ef0497a5 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/mainboard.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void mainboard_final(void *chip_info) +{ + if (CONFIG(BEEP_ON_BOOT)) + beep(1500, 100); +} + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + silconfig->C1e = 0x1; + silconfig->PkgCStateLimit = 0xFE; + silconfig->CStateAutoDemotion = 0x3; + silconfig->CStateUnDemotion = 0x3; + silconfig->PkgCStateDemotion = 0x1; + silconfig->PkgCStateUnDemotion = 0x1; + silconfig->Usb30Mode = 0x1; + silconfig->DspEnable = 0x0; + silconfig->UsbPdoProgramming = 0x1; + + silconfig->PcieRpHotPlug[0] = 0x0; + silconfig->PcieRpPmSci[0] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[0] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[0] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[0] = 0x1003; + silconfig->PcieRpClkReqSupported[0] = 0x0; + silconfig->AdvancedErrorReporting[0] = 0x1; + silconfig->PmeInterrupt[0] = 0x1; + + silconfig->PcieRpHotPlug[1] = 0x0; + silconfig->PcieRpPmSci[1] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[1] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[1] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[1] = 0x1003; + silconfig->PcieRpClkReqSupported[1] = 0x0; + silconfig->AdvancedErrorReporting[1] = 0x1; + silconfig->PmeInterrupt[1] = 0x1; + + silconfig->PcieRpHotPlug[2] = 0x0; + silconfig->PcieRpPmSci[2] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[2] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[2] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[2] = 0x1003; + silconfig->PcieRpClkReqSupported[2] = 0x0; + silconfig->AdvancedErrorReporting[2] = 0x1; + silconfig->PmeInterrupt[2] = 0x1; + + silconfig->PcieRpHotPlug[3] = 0x0; + silconfig->PcieRpPmSci[3] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[3] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[3] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[3] = 0x1003; + silconfig->PcieRpClkReqSupported[3] = 0x0; + silconfig->AdvancedErrorReporting[3] = 0x1; + silconfig->PmeInterrupt[3] = 0x1; + + silconfig->PcieRpHotPlug[4] = 0x0; + silconfig->PcieRpPmSci[4] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[4] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[4] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[4] = 0x1003; + silconfig->PcieRpClkReqSupported[4] = 0x0; + silconfig->AdvancedErrorReporting[4] = 0x1; + silconfig->PmeInterrupt[4] = 0x1; + + silconfig->PcieRpHotPlug[5] = 0x0; + silconfig->PcieRpPmSci[5] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; + silconfig->PcieRpClkReqSupported[5] = 0x0; + silconfig->AdvancedErrorReporting[5] = 0x1; + silconfig->PmeInterrupt[5] = 0x1; +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, +}; diff --git a/src/mainboard/protectli/vault_glk/romstage.c b/src/mainboard/protectli/vault_glk/romstage.c new file mode 100644 index 00000000000..5a1102bf195 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/romstage.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "gpio.h" + +/* DDR4 specific swizzling data start */ + +/* Channel 0 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch0_ddr4[] = { + 1, 0, 5, 7, 2, 3, 6, 4, 24, 29, 28, 26, 25, 30, 31, 27, + 19, 18, 23, 22, 17, 16, 21, 20, 8, 9, 12, 13, 10, 15, 11, 14, +}; + +/* Channel 1 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch1_ddr4[] = { + 5, 6, 0, 2, 4, 7, 3, 1, 12, 13, 10, 11, 15, 14, 9, 8, + 21, 22, 18, 16, 23, 19, 17, 20, 28, 30, 27, 26, 29, 24, 31, 25, +}; + +/* DDR4 specific swizzling data end */ + +static void fill_ddr4_params(FSP_M_CONFIG *cfg) +{ + cfg->Ch0_DeviceWidth = 0x00; /* Only for memory down */ + cfg->Ch0_DramDensity = 0x00; /* Only for memory down */ + cfg->Ch0_Mode2N = 0x00; /* Only for DDR3L */ + cfg->Ch0_OdtConfig = 0; + cfg->Ch0_OdtLevels = 0; /* ODT connected to SoC */ + /* bit0 Rank Select Interleaving Enable , + bit1 Bank Address Hashing enabled */ + cfg->Ch0_Option = 0x03; + /* bit0 enable rank 0, + * bit1 enable rank 1. + * This is allowed maximum, it may be trimmed down by FSP based on SPD data. + */ + cfg->Ch0_RankEnable = 0x03; + cfg->Ch0_TristateClk1 = 0x00; + + cfg->Ch1_DeviceWidth = 0x00; + cfg->Ch1_DramDensity = 0x00; + cfg->Ch1_Mode2N = 0x00; + cfg->Ch1_OdtConfig = 0; + cfg->Ch1_OdtLevels = 0; + cfg->Ch1_Option = 0x03; + cfg->Ch1_RankEnable = 0x03; + cfg->Ch1_TristateClk1 = 0x00; + + cfg->Ch2_DeviceWidth = 0x00; + cfg->Ch2_DramDensity = 0x00; + cfg->Ch2_Mode2N = 0x00; + cfg->Ch2_OdtConfig = 0; + cfg->Ch2_OdtLevels = 0; + cfg->Ch2_Option = 0x03; + cfg->Ch2_RankEnable = 0x03; + cfg->Ch2_TristateClk1 = 0x00; + + cfg->Ch3_DramDensity = 0x00; + cfg->Ch3_Mode2N = 0x00; + cfg->Ch3_OdtConfig = 0; + cfg->Ch3_OdtLevels = 0; + cfg->Ch3_Option = 0x03; + cfg->Ch3_RankEnable = 0x03; + cfg->Ch3_TristateClk1 = 0x00; + + cfg->ChannelHashMask = 0x00; + cfg->ChannelsSlicesEnable = 0x00; + cfg->DDR3LASR = 0x00; /* Only for memory down */ + cfg->DDR3LPageSize = 0x00; /* Only for memory down */ + cfg->DIMM0SPDAddress = 0xA0; + cfg->DIMM1SPDAddress = 0xA4; + cfg->DisableFastBoot = 0x00; /* Use saved training data if valid */ + cfg->DualRankSupportEnable = 0x01; + cfg->eMMCTraceLen = 0x0; + cfg->EnhancePort8xhDecoding = 1; + cfg->HighMemoryMaxValue = 0x00; + cfg->Igd = 0x01; + cfg->IgdApertureSize = 0x1; /* 128MB */ + cfg->IgdDvmt50PreAlloc = 0x02; /* 64MB */ + cfg->GttSize = 0x3; /* 8MB */ + cfg->InterleavedMode = 0x02; /* Enable = 0x2? */ + cfg->LowMemoryMaxValue = 0x0000; + cfg->MemoryDown = 0x0; + cfg->MemorySizeLimit = 0x0000; + cfg->MinRefRate2xEnable = 0x01; + cfg->MrcDataSaving = 0x01; + cfg->MrcFastBoot = 0x01; + cfg->MsgLevelMask = 0x00000000; + /* Specifies CA Mapping for all technologies. + * 0 - SODIMM(Default) + * 1 - BGA + * 2 - BGA mirrored (LPDDR3 only) + * 3 - SODIMM/UDIMM with Rank 1 Mirrored (DDR3L) + */ + cfg->Package = 0x00; + cfg->PreMemGpioTableEntryNum = 0; + cfg->PreMemGpioTablePinNum[0] = 0; + cfg->PreMemGpioTablePinNum[1] = 0; + cfg->PreMemGpioTablePinNum[2] = 0; + cfg->PreMemGpioTablePinNum[3] = 0; + cfg->PreMemGpioTablePtr = 0x00000000; + /* + * FSP headers say: 0x0:AUTO, 0x2:IGD, 0x3:PCI, but the Geminilake FSP + * code says: 0x0:IGD, 0x1:PCI + */ + cfg->PrimaryVideoAdaptor = 0x0; + /* + * Profiles: + * 0x01:LPDDR3_1333_10_12_12, + * 0x02:LPDDR3_1600_12_15_15, + * 0x03:LPDDR3_1866_14_17_17, + * 0x04:LPDDR4_1600_14_15_15, + * 0x05:LPDDR4_1866_20_17_17, + * 0x06:LPDDR4_2133_20_20_20, + * 0x07:LPDDR4_2400_24_22_22, + * 0x08:LPDDR4_2666_24_24_24, + * 0x09:LPDDR4_3200_28_29_29, + * 0x0A:DDR4_1600_10_10_10, + * 0x0B:DDR4_1600_11_11_11, + * 0x0C:DDR4_1600_12_12_12, + * 0x0D:DDR4_1866_12_12_12, + * 0x0E:DDR4_1866_13_13_13, + * 0x0F:DDR4_1866_14_14_14, + * 0x10:DDR4_2133_14_14_14, + * 0x11:DDR4_2133_15_15_15, + * 0x12:DDR4_2133_16_16_16, + * 0x13:DDR4_2400_15_15_15, + * 0x14:DDR4_2400_16_16_16, + * 0x15:DDR4_2400_17_17_17 (default), + * 0x16:DDR4_2400_18_18_18, + * 0x17:DDR4_2666_17_17_17, + * 0x18:DDR4_2666_18_18_18, + * 0x19:DDR4_2666_19_19_19, + * 0x1A:DDR4_2666_20_20_20 + */ + cfg->Profile = 0x15; + cfg->OemLoadingBase = 0; + /* Tolerance percentage o failing margins */ + cfg->RmtMarginCheckScaleHighThreshold = 0x0000; + cfg->RmtMode = 0x00; + cfg->ScramblerSupport = 0x01; + cfg->SerialDebugPortAddress = 0x000003f8; + cfg->SerialDebugPortDevice = 0x03; /* External device */ + cfg->SerialDebugPortStrideSize = 0x00; /* Stride 1 byte */ + cfg->SerialDebugPortType = 0x01; /* I/O */ + cfg->SliceHashMask = 0x00; + cfg->SpdWriteEnable = 0x00; + cfg->StartTimerTickerOfPfetAssert = 0x4E20; + + /* phy0 ch0 */ + memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_ddr4, sizeof(swizzling_ch0_ddr4)); + /* phy0 ch1 */ + memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_ddr4, sizeof(swizzling_ch1_ddr4)); + /* phy1 ch1 */ + memset(cfg->Ch2_Bit_swizzling, 0, sizeof(cfg->Ch2_Bit_swizzling)); + /* phy1 ch0 */ + memset(cfg->Ch3_Bit_swizzling, 0, sizeof(cfg->Ch3_Bit_swizzling)); +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *cfg = &memupd->FspmConfig; + fill_ddr4_params(cfg); + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +void mainboard_save_dimm_info(void) +{ + save_ddr4_dimm_info(); +} diff --git a/src/mainboard/protectli/vault_jsl/Kconfig b/src/mainboard/protectli/vault_jsl/Kconfig new file mode 100644 index 00000000000..563b97e8a2e --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/Kconfig @@ -0,0 +1,61 @@ +if BOARD_PROTECTLI_V1210 || BOARD_PROTECTLI_V1211 || BOARD_PROTECTLI_V1410 || BOARD_PROTECTLI_V1610 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_JASPERLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SUPERIO_ITE_IT8613E + select INTEL_GMA_HAVE_VBT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS + select USE_LPDDR4 + select CRB_TPM + select HAVE_INTEL_PTT + select MAINBOARD_HAS_TPM2 + +config MAX_CPUS + default 4 + +config MAINBOARD_DIR + string + default "protectli/vault_jsl" + +config OVERRIDE_DEVICETREE + default "override_v12xx.cb" if BOARD_PROTECTLI_V1210 || BOARD_PROTECTLI_V1211 + default "override_v1410.cb" if BOARD_PROTECTLI_V1410 + default "override_v1610.cb" if BOARD_PROTECTLI_V1610 + +config MAINBOARD_PART_NUMBER + string + default "V1210" if BOARD_PROTECTLI_V1210 + default "V1211" if BOARD_PROTECTLI_V1211 + default "V1410" if BOARD_PROTECTLI_V1410 + default "V1610" if BOARD_PROTECTLI_V1610 + +config MAINBOARD_FAMILY + string + default "Protectli Vault" + +config DIMM_MAX + default 2 + +config DIMM_SPD_SIZE + default 512 + +config CBFS_SIZE + default 0x800000 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config BEEP_ON_BOOT + bool "Beep on successful boot" + default y + help + Make the platform beep using the PC speaker in final coreboot phase. + May serve as a useful indicator in headless mode that platform is + properly booting. + +endif diff --git a/src/mainboard/protectli/vault_jsl/Kconfig.name b/src/mainboard/protectli/vault_jsl/Kconfig.name new file mode 100644 index 00000000000..caaa9f444ed --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/Kconfig.name @@ -0,0 +1,11 @@ +config BOARD_PROTECTLI_V1210 + bool "V1210" + +config BOARD_PROTECTLI_V1211 + bool "V1211" + +config BOARD_PROTECTLI_V1410 + bool "V1410" + +config BOARD_PROTECTLI_V1610 + bool "V1610" diff --git a/src/mainboard/protectli/vault_jsl/Makefile.mk b/src/mainboard/protectli/vault_jsl/Makefile.mk new file mode 100644 index 00000000000..1c840117da4 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/Makefile.mk @@ -0,0 +1,17 @@ + +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c + +bootblock-y += die.c +romstage-y += die.c +ramstage-y += die.c +smm-y += die.c + +#SPD_SOURCES = MT53E512M32D4NQ-053 # 2GBx4 (pre-production V1210) +SPD_SOURCES = MT53D512M64D4RQ-046 # 2GBx4 (production V1210) +SPD_SOURCES += MT53E1G32D2NP-046 # 4GBx4 diff --git a/src/mainboard/protectli/vault_jsl/acpi/superio.asl b/src/mainboard/protectli/vault_jsl/acpi/superio.asl new file mode 100644 index 00000000000..7127793fe44 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/acpi/superio.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8613E_SHOW_UARTA +#undef IT8613E_SHOW_KBC +#undef IT8613E_SHOW_PS2M +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8613E_SHOW_UARTA 1 + +#include diff --git a/src/mainboard/protectli/vault_jsl/board.fmd b/src/mainboard/protectli/vault_jsl/board.fmd new file mode 100644 index 00000000000..7b055e11707 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/board.fmd @@ -0,0 +1,15 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL 8M { + SI_DESC 4K + SI_ME + } + + SMMSTORE(PRESERVE) 256K + RW_MRC_CACHE 64K + CONSOLE 0x20000 + BOOTSPLASH(CBFS) 1M + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/protectli/vault_jsl/board_info.txt b/src/mainboard/protectli/vault_jsl/board_info.txt new file mode 100644 index 00000000000..257dc512e62 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: V1210/V1410/V1610 +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault_jsl/bootblock.c b/src/mainboard/protectli/vault_jsl/bootblock.c new file mode 100644 index 00000000000..2b925ee1f58 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/bootblock.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) + +static void ite_set_gpio_base(pnp_devfn_t dev, uint16_t iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(dev); +} + +void bootblock_mainboard_early_init(void) +{ + ite_kill_watchdog(GPIO_DEV); + ite_reg_write(GPIO_DEV, 0x26, 0xfb); /* Pin7 as GP23 */ + ite_reg_write(GPIO_DEV, 0x29, 0x00); + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */ + ite_reg_write(SERIAL1_DEV, 0xf0, 0x01); /* enable IRQ sharing */ + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); + + ite_reg_write(GPIO_DEV, 0xc1, 0x0a); /* GP21 and GP23 as simple I/O */ + ite_reg_write(GPIO_DEV, 0xc9, 0x0a); /* GP21 and GP23 as output */ + ite_set_gpio_base(GPIO_DEV, 0xa00); + + /* GP21 and GP23 to low to enable USB ports VBUS */ + outb(inb(0xa01) & ~0x0a, 0xa01); +} diff --git a/src/mainboard/protectli/vault_jsl/data.vbt b/src/mainboard/protectli/vault_jsl/data.vbt new file mode 100644 index 00000000000..5e399d752dd Binary files /dev/null and b/src/mainboard/protectli/vault_jsl/data.vbt differ diff --git a/src/mainboard/protectli/vault_jsl/devicetree.cb b/src/mainboard/protectli/vault_jsl/devicetree.cb new file mode 100644 index 00000000000..2567cac6dcc --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/devicetree.cb @@ -0,0 +1,155 @@ +chip soc/intel/jasperlake + + device cpu_cluster 0 on end + + register "eist_enable" = "1" + + register "enable_c6dram" = "1" + + register "tcc_offset" = "20" + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_G" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_R" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "ScsEmmcHs400Enabled" = "1" + + # Display related UPDs + + # Enable HPD for DDI port C + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI port C + register "DdiPortCDdc" = "1" + + register "SkipExtGfxScan" = "1" + + register "usb2_ports" = "{ + [1] = USB2_PORT_SHORT(OC_SKIP), // Type A port1 + [2] = USB2_PORT_SHORT(OC_SKIP), // M.2 LTE + [3] = USB2_PORT_SHORT(OC_SKIP), // WiFi slot BT + [4] = USB2_PORT_SHORT(OC_SKIP), // VIA VL817 hub + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type A Port1 + [1] = USB3_PORT_DEFAULT(OC_SKIP), // VIA VL817 hub + [5] = USB3_PORT_DEFAULT(OC_SKIP), // M.2 LTE + }" + + register "usb2_wake_enable_bitmap" = "0x0002" + register "usb3_wake_enable_bitmap" = "0x0001" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[1]" = "1" + + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x000c0081" + register "gen3_dec" = "0x00fc0201" + + # Skip the CPU replacement check + register "SkipCpuReplacementCheck" = "1" + + register "PchHdaAudioLinkHdaEnable" = "1" + + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # WiFi + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # M.2 NVMe + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" # LAN1 + register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" # LAN2 + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # clock buffer for LAN3-6 + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + + # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # Set xHCI LFPS period sampling off time, the default is 9ms. + register "xhci_lfps_sampling_offtime_ms" = "9" + + register "disable_external_bypass_vr" = "true" + + # Add PL1 and PL2 values + register "power_limits_config[JSL_N5105_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + register "power_limits_config[JSL_N6005_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # IPU + device pci 08.0 off end # GNA + device pci 09.0 off end # Intel Trace Hub + device pci 12.0 off end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI 2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # PMC SRAM + device pci 14.3 off end # CNVi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 16.0 on end # HECI 1 + device pci 16.1 off end # HECI 2 + device pci 16.4 off end # HECI 3 + device pci 16.5 off end # HECI 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C 4 + device pci 19.1 off end # I2C 5 + device pci 19.2 off end # UART 2 + device pci 1c.0 off end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 off end # PCI Express Root Port 5 + device pci 1c.5 off end # PCI Express Root Port 6 + device pci 1c.6 off end # PCI Express Root Port 7 + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1a.0 on end # eMMC + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 off end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1f.0 on # eSPI + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa10 + io 0x62 = 0xa00 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on end # Intel HDA/cAVS + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.7 off end # Intel Trace Hub + + chip drivers/crb + device mmio 0xfed40000 on end + end + end +end diff --git a/src/mainboard/protectli/vault_jsl/die.c b/src/mainboard/protectli/vault_jsl/die.c new file mode 100644 index 00000000000..3a48f4623a9 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/die.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void beep_and_blink(void) +{ + static uint8_t blink = 0; + static uint8_t beep_count = 0;; + + gpio_set(GPP_E5, blink); + /* Beep 12 times at most, constant beeps may be annoying */ + if (beep_count < 12) { + beep(800, 300); + mdelay(200); + beep_count++; + } else { + mdelay(500); + } + + blink ^= 1; +} + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink and use PC SPKR */ + gpio_output(GPP_E5, 0); + + while (1) { + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + delay(2); + } +} diff --git a/src/mainboard/protectli/vault_jsl/dsdt.asl b/src/mainboard/protectli/vault_jsl/dsdt.asl new file mode 100644 index 00000000000..7b548ca3b33 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + Scope (\_SB.PCI0.LPCB) { + #include "acpi/superio.asl" + } + + #include +} diff --git a/src/mainboard/protectli/vault_jsl/gpio.h b/src/mainboard/protectli/vault_jsl/gpio.h new file mode 100644 index 00000000000..b486a500388 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/gpio.h @@ -0,0 +1,446 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - GPIO */ + PAD_NC(GPP_G0, NONE), + /* GPP_G1 - GPIO */ + PAD_NC(GPP_G1, NONE), + /* GPP_G2 - GPIO */ + PAD_NC(GPP_G2, NONE), + /* GPP_G3 - GPIO */ + PAD_NC(GPP_G3, NONE), + /* GPP_G4 - GPIO */ + PAD_NC(GPP_G4, NONE), + /* GPP_G5 - GPIO */ + PAD_NC(GPP_G5, NONE), + /* GPP_G6 - GPIO */ + PAD_NC(GPP_G6, NONE), + /* GPP_G7 - GPIO */ + PAD_NC(GPP_G7, NONE), + + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + /* GPP_E1 - GPIO */ + PAD_NC(GPP_E1, NONE), + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + /* GPP_E3 - GPIO */ + PAD_NC(GPP_E3, NONE), + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + /* GPP_E5 - SATA_LED_N */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* GPP_E6 - GPIO */ + PAD_NC(GPP_E6, NONE), + /* GPP_E7 - GPIO */ + PAD_NC(GPP_E7, NONE), + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 - GPIO */ + PAD_NC(GPP_E13, NONE), + /* GPP_E14 - GPIO */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15 - DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), + /* GPP_E16 - DDI1_DDC_SDA */ + PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + /* GPP_E17 - DDI2_DDC_SCL */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* GPP_E18 - DDI2_DDC_SDA */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* GPP_E19 - GPIO */ + PAD_NC(GPP_E19, NONE), + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NONE), + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NONE), + /* GPP_E22 - GPIO */ + PAD_NC(GPP_E22, NONE), + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + /* GPD1 - PMC_ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7 - GPIO */ + PAD_NC(GPD7, NONE), + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_NC(GPP_H0, NONE), + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + /* GPP_H2 - GPIO */ + PAD_NC(GPP_H2,NONE), + /* GPP_H3 - GPIO */ + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - GPIO */ + PAD_NC(GPP_H4, NONE), + /* GPP_H5 - GPIO */ + PAD_NC(GPP_H5, NONE), + /* GPP_H6 - GPIO */ + PAD_NC(GPP_H6, NONE), + /* GPP_H7 - GPIO */ + PAD_NC(GPP_H7, NONE), + /* GPP_H8 - GPIO */ + PAD_NC(GPP_H8, NONE), + /* GPP_H9 - GPIO */ + PAD_NC(GPP_H9, NONE), + /* GPP_H10 - GPIO */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11,NONE), + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12,NONE), + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13,NONE), + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14,NONE), + /* GPP_H15 - GPIO */ + PAD_NC(GPP_H15, NONE), + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16,NONE), + /* GPP_H17 - GPIO */ + PAD_NC(GPP_H17, NONE), + /* GPP_H18 - GPIO */ + PAD_NC(GPP_H18,NONE), + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19,NONE), + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_NC(GPP_D0, NONE), + /* GPP_D1 - GPIO */ + PAD_NC(GPP_D1, NONE), + /* GPP_D2 - GPIO */ + PAD_NC(GPP_D2, NONE), + /* GPP_D3 - GPIO */ + PAD_NC(GPP_D3, NONE), + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + /* GPP_D5 - GPIO */ + PAD_NC(GPP_D5, NONE), + /* GPP_D6 - GPIO */ + PAD_NC(GPP_D6, NONE), + /* GPP_D7 - GPIO */ + PAD_NC(GPP_D7, NONE), + /* GPP_D8 - GPIO */ + PAD_NC(GPP_D8, NONE), + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NONE), + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NONE), + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NONE), + /* GPP_D12 - GPIO */ + PAD_NC(GPP_D12, NONE), + /* GPP_D13 - GPIO */ + PAD_NC(GPP_D13, NONE), + /* GPP_D14 - GPIO */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + /* GPP_D20 - GPIO */ + PAD_NC(GPP_D20, NONE), + /* GPP_D21 - GPIO */ + PAD_NC(GPP_D21, NONE), + /* GPP_D22 - GPIO */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23 - GPIO */ + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - GPIO */ + PAD_NC(GPP_C0, NONE), + /* GPP_C1 - GPIO */ + PAD_NC(GPP_C1, NONE), + /* GPP_C2 - GPIO */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - GPIO */ + PAD_NC(GPP_C3, NONE), + /* GPP_C4 - GPIO */ + PAD_NC(GPP_C4, NONE), + /* GPP_C5 - GPIO */ + PAD_NC(GPP_C5, NONE), + /* GPP_C6 - M2_PEDET (NVME=1, SATA=0) */ + PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), + /* GPP_C7 - GPIO */ + PAD_NC(GPP_C7, NONE), + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - GPIO */ + PAD_NC(GPP_F0, NONE), + /* GPP_F1 - GPIO */ + PAD_NC(GPP_F1, NONE), + /* GPP_F2 - GPIO */ + PAD_NC(GPP_F2, NONE), + /* GPP_F3 - GPIO */ + PAD_NC(GPP_F3, NONE), + /* GPP_F4 - GPIO */ + PAD_NC(GPP_F4, NONE), + /* GPP_F5 - GPIO */ + PAD_NC(GPP_F5, NONE), + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + /* GPP_F7 - EMMC_CMD */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + /* GPP_F8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + /* GPP_F9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + /* GPP_F10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + /* GPP_F11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* GPP_F12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* GPP_F13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* GPP_F14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* GPP_F15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* GPP_F16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* GPP_F17 - EMMC_CLK */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* GPP_F18 - EMMC_RESET_N */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - PMC_CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1 - PMC_CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2 - GPIO */ + PAD_NC(GPP_B2, NONE), + /* GPP_B3 - GPIO */ + PAD_NC(GPP_B3, NONE), + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO */ + PAD_NC(GPP_B8, NONE), + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + /* GPP_B11 - GPIO */ + PAD_NC(GPP_B11, NONE), + /* GPP_B12 - PMC_SLP_S_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PMC_PLTRST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* GPP_B15 - GPIO */ + PAD_NC(GPP_B15, NONE), + /* GPP_B16 - GPIO */ + PAD_NC(GPP_B16, NONE), + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_NC(GPP_B18, NONE), + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + /* GPP_B23 - DDI2_HPD */ + PAD_CFG_NF(GPP_B23, NONE, PLTRST, NF1), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO_0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* GPP_A1 - ESPI_IO_1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* GPP_A2 - ESPI_IO_2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* GPP_A3 - ESPI_IO_3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* GPP_A4 - ESPI_CS_N */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* GPP_A5 - ESPI_CLK */ + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + /* GPP_A6 - ESPI_RESET_N */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + /* GPP_A7 - SMB_CLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* GPP_A8 - SMB_DATA */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* GPP_A9 - GPIO */ + PAD_NC(GPP_A9, NONE), + /* GPP_A10 - GPIO */ + PAD_NC(GPP_A10, NONE), + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + /* GPP_A12 - GPIO */ + PAD_NC(GPP_A12, NONE), + /* GPP_A13 - GPIO */ + PAD_NC(GPP_A13, NONE), + /* GPP_A14 - GPIO */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15 - GPIO */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16 - DDI1_HPD */ + PAD_CFG_NF(GPP_A16, NONE, PLTRST, NF1), + /* GPP_A17 - DDI0_HPD */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* GPP_A18 - GPIO */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 - GPIO */ + PAD_NC(GPP_A19, NONE), + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* GPP_R4 - HDA_RST_N */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/protectli/vault_jsl/hda_verb.c b/src/mainboard/protectli/vault_jsl/hda_verb.c new file mode 100644 index 00000000000..a25b2b669ef --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* JasperLake HDMI */ + 0x8086281a, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 8, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault_jsl/mainboard.c b/src/mainboard/protectli/vault_jsl/mainboard.c new file mode 100644 index 00000000000..3c1814480be --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/mainboard.c @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FSP_PCH_PCIE_ASPM_L1 2 + +#define IFD_FIA_COMBO_PORT0 0x189 +#define FIA_PCIE 5 +#define FIA_SATA 7 + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A +#define SI_DESC_SIZE 0x1000 +#define SI_DESC_REGION "SI_DESC" + +/* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */ +static bool is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_ERR, "Flash Descriptor is not valid\n"); + return 0; + } + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); + return 0; + } + return 1; +} + +static void descriptor_patch_pcie8_lane(int is_nvme) +{ + uint8_t *si_desc_buf; + struct region_device desc_rdev; + uint8_t state = is_nvme ? FIA_PCIE : FIA_SATA; + + si_desc_buf = (uint8_t *)malloc(SI_DESC_SIZE); + + if (!si_desc_buf) { + printk(BIOS_ERR, "Failed to allocate buffer for %s\n", SI_DESC_REGION); + return; + } + + if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + free(si_desc_buf); + return; + } + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + free(si_desc_buf); + return; + } + if (!is_descriptor_writeable(si_desc_buf)) { + free(si_desc_buf); + return; + } + + /* + * Offset 0x189 bits [0:3]: 5=PCIe, 7=SATA. + * Not patching the descriptor will result in SATA or NVMe not working. + */ + if ((si_desc_buf[IFD_FIA_COMBO_PORT0] & 0xf) == state) { + printk(BIOS_DEBUG, "Update of Descriptor is not required!\n"); + free(si_desc_buf); + return; + } + + si_desc_buf[IFD_FIA_COMBO_PORT0] &= 0xf0; + si_desc_buf[IFD_FIA_COMBO_PORT0] |= state; + + /* FIT als sets reserved offset 0x1a4 bits [0:3]: 5=PCIe, 1=SATA */ + if (state == FIA_PCIE) { + si_desc_buf[0x1a4] &= 0xf0; + si_desc_buf[0x1a4] |= 5; + } else { + si_desc_buf[0x1a4] &= 0xf0; + si_desc_buf[0x1a4] |= 1; + } + + if (rdev_eraseat(&desc_rdev, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + free(si_desc_buf); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + free(si_desc_buf); + return; + } + + printk(BIOS_DEBUG, "Update of Descriptor successful\n"); + free(si_desc_buf); + do_global_reset(); +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_LOW_PROFILE_DESKTOP; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +const char *smbios_system_sku(void) +{ + return CONFIG_MAINBOARD_PART_NUMBER "-01"; +} + +const char *smbios_chassis_sku(void) +{ + return CONFIG_MAINBOARD_PART_NUMBER "-001"; +} + +const char *smbios_chassis_version(void) +{ + return "1.2"; +} + +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + len += smbios_write_type41( + current, handle, + "Onboard - USB Controller", /* name */ + 0, /* instance */ + 0, /* segment */ + 0, /* bus */ + PCH_DEV_SLOT_XHCI, /* device */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ + + len += smbios_write_type41( + current, handle, + "Onboard - HECI", /* name */ + 0, /* instance */ + 0, /* segment */ + 0, /* bus */ + PCH_DEV_SLOT_CSE, /* device */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ + + len += smbios_write_type41( + current, handle, + "Onboard - eMMC", /* name */ + 0, /* instance */ + 0, /* segment */ + 0, /* bus */ + PCH_DEV_SLOT_STORAGE, /* device */ + 0, /* function */ + SMBIOS_DEVICE_TYPE_OTHER); /* device type */ + + return len; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_data = mainboard_smbios_data; +} + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->UsbPdoProgramming = 0; + + for (uint8_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + params->PcieRpAcsEnabled[i] = 1; + params->PcieRpAdvancedErrorReporting[i] = 1; + params->PcieRpLtrEnable[i] = 1; + params->PcieRpMaxPayload[i] = 1; // 256B + params->PcieRpSlotImplemented[i] = 1; + } + + if (CONFIG(BOARD_PROTECTLI_V1610)) { + /* Read GPP_C6 (M2_PEDET) to check for disk type: 1=NVME, 0=SATA */ + gpio_input_pullup(GPP_C6); + /* + * Patch the descriptor accordingly, by default the lanes 7 and 8 + * are in 1x2 mode. Lane 8 can be statically assigned to either + * PCIe or SATA + */ + descriptor_patch_pcie8_lane(gpio_get(GPP_C6)); + } + + /* + * Enable only L1 for WiFi, L0s doesn't work reliably for Atheros QCA6174. + * On V1610, WiFi is connected to different root port through PCIe switch + * (ASMedia ASM1806), but the switch doesn't support L0s on upstream port + * so this workaround isn't needed there. + */ + if (!CONFIG(BOARD_PROTECTLI_V1610)) + params->PcieRpAspm[4] = FSP_PCH_PCIE_ASPM_L1; + + /* + * HWP is too aggressive in power savings and does not let using full + * bandwidth of Ethernet controllers without additional stressing of + * the CPUs (2Gb/s vs 2.35Gb/s with stressing, measured with iperf3). + * Let the Linux use acpi-cpufreq governor driver instead of + * intel_pstate by disabling HWP. + */ + params->Hwp = 0; + + /* + * Skip PCI Subsystem IDs programming to match proprietary FW. + * It also makes some Windows default drivers to probe successfully, e.g. audio. + */ + params->SiSkipSsidProgramming = 1; +} + +static void mainboard_final(void *unused) +{ + if (CONFIG(BEEP_ON_BOOT)) + beep(1500, 100); +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/protectli/vault_jsl/override_v12xx.cb b/src/mainboard/protectli/vault_jsl/override_v12xx.cb new file mode 100644 index 00000000000..9d3c66f7c04 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/override_v12xx.cb @@ -0,0 +1,23 @@ +chip soc/intel/jasperlake + device domain 0 on + # Using x2 link on PCIe 5/6 to avoid switching to SATA + device pci 1c.0 on # PCI Express Root Port 1 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (NVMe)" "SlotDataBusWidth2X" + end + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 on # PCI Express Root Port 5 + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (WIFI)" "SlotDataBusWidth1X" + end + device pci 1c.5 on # PCI Express Root Port 6 (LAN1) + smbios_dev_info 1 + end + device pci 1c.6 on # PCI Express Root Port 7 (LAN2) + smbios_dev_info 2 + end + device pci 1c.7 off end # PCI Express Root Port 8 + end +end diff --git a/src/mainboard/protectli/vault_jsl/override_v1410.cb b/src/mainboard/protectli/vault_jsl/override_v1410.cb new file mode 100644 index 00000000000..46260f8f560 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/override_v1410.cb @@ -0,0 +1,28 @@ +chip soc/intel/jasperlake + device domain 0 on + device pci 1c.0 on # PCI Express Root Port 1 (LAN1) + smbios_dev_info 1 + end + device pci 1c.1 on # PCI Express Root Port 2 (LAN2) + smbios_dev_info 2 + end + # NVMe x1 link, making it x2 link with lane reversal + # would mess up the LAN port order + device pci 1c.2 on # PCI Express Root Port 3 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (NVMe)" "SlotDataBusWidth1X" + end + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 on # PCI Express Root Port 5 + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (WIFI)" "SlotDataBusWidth1X" + end + device pci 1c.5 on # PCI Express Root Port 6 (LAN3) + smbios_dev_info 3 + end + device pci 1c.6 on # PCI Express Root Port 7 (LAN4) + smbios_dev_info 4 + end + device pci 1c.7 off end # PCI Express Root Port 8 + end +end diff --git a/src/mainboard/protectli/vault_jsl/override_v1610.cb b/src/mainboard/protectli/vault_jsl/override_v1610.cb new file mode 100644 index 00000000000..aa3af93cf60 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/override_v1610.cb @@ -0,0 +1,24 @@ +chip soc/intel/jasperlake + device domain 0 on + # ASMedia PCIe switch with x2 link to 4x1 ports (3 LANs and WiFi) + device pci 1c.0 on end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + # NVMe with x2 link, lane 8 switchable to SATA + device pci 1c.2 on # PCI Express Root Port 3 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (NVMe)" "SlotDataBusWidth2X" + end + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 on # PCI Express Root Port 5 + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (WIFI)" "SlotDataBusWidth1X" + end + device pci 1c.5 on + smbios_dev_info 3 + end # PCI Express Root Port 6 (LAN3) + device pci 1c.6 on + smbios_dev_info 4 + end # PCI Express Root Port 7 (LAN4) + device pci 1c.7 off end # PCI Express Root Port 8 + end +end diff --git a/src/mainboard/protectli/vault_jsl/romstage.c b/src/mainboard/protectli/vault_jsl/romstage.c new file mode 100644 index 00000000000..c27610d836c --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/romstage.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +#include "gpio.h" + +static const struct mb_cfg memcfg_cfg = { + + /* Static array from the worksheet */ + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* Copied from the worksheet after filling DQS map */ + .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7}, + + /* Copied from the worksheet for JSL LPDDR4X */ + .rcomp_resistor = {100, 100, 100}, + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* Enable Early Command Training */ + .ect = 1, + + /* User Board Type */ + .UserBd = BOARD_TYPE_ULT_ULX, +}; + +static int get_spd_index(void) +{ + return (CONFIG(BOARD_PROTECTLI_V1410) || CONFIG(BOARD_PROTECTLI_V1610)); +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct spd_info board_spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = get_spd_index(), + }; + + memcfg_init(&memupd->FspmConfig, &memcfg_cfg, &board_spd_info, false); + + /* + * V1210 and V1410 populate only channel 1. + * V1211 and V1610 populate both channels. + */ + if (CONFIG(BOARD_PROTECTLI_V1210) || CONFIG(BOARD_PROTECTLI_V1410)) + memupd->FspmConfig.MemorySpdPtr00 = 0; + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/protectli/vault_jsl/spd/MT53D512M64D4RQ-046.spd.hex b/src/mainboard/protectli/vault_jsl/spd/MT53D512M64D4RQ-046.spd.hex new file mode 100644 index 00000000000..303192f84a6 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/spd/MT53D512M64D4RQ-046.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 A7 77 46 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 4D 54 35 33 44 35 31 +32 4D 36 34 44 34 52 51 2D 30 34 36 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/protectli/vault_jsl/spd/MT53E1G32D2NP-046.spd.hex b/src/mainboard/protectli/vault_jsl/spd/MT53E1G32D2NP-046.spd.hex new file mode 100644 index 00000000000..ab961ca9aa2 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/spd/MT53E1G32D2NP-046.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 90 08 00 40 00 00 02 22 00 00 +00 00 05 0F 92 54 01 00 8a 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 a7 77 46 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 4D 54 35 33 44 35 31 +32 4D 36 34 44 34 52 51 2D 30 34 36 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/protectli/vault_jsl/spd/MT53E512M32D4NQ-053.spd.hex b/src/mainboard/protectli/vault_jsl/spd/MT53E512M32D4NQ-053.spd.hex new file mode 100644 index 00000000000..82617e0759b --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/spd/MT53E512M32D4NQ-053.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 14 21 B0 08 00 40 00 00 0A 22 00 00 +00 00 05 0F 92 54 01 00 8a 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 a7 77 46 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 4D 54 35 33 44 35 31 +32 4D 36 34 44 34 52 51 2D 30 34 36 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 10f8c400b71..23229d386df 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -47,4 +47,11 @@ config CBFS_SIZE config USE_PM_ACPI_TIMER default n +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 5 + +endif + endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 55074435abd..465d72acf78 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -551,6 +551,11 @@ static void fam16_finalize(void *chip_info) if (dev != NULL) { pci_and_config32(dev, 0x60, ~(1 << 11)); } + + /* Enable access to PSP MMIO BARs. This is needed for CCP. */ + dev = pcidev_on_root(8, 0); + if (dev != NULL) + pci_update_config8(dev, 0x48, 0xff, 0x3d); } struct hw_mem_hole_info { @@ -660,9 +665,9 @@ struct device_operations amd_fam16_mod30_pci_domain_ops = { void mp_init_cpus(struct bus *cpu_bus) { - extern const struct mp_ops amd_mp_ops_no_smm; + extern const struct mp_ops amd_mp_ops_with_smm; /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &amd_mp_ops_no_smm); + mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm); /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index a05e9e04e81..38ed0916fce 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -10,6 +10,7 @@ #include #include #include +#include void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { @@ -18,6 +19,9 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) { Early->GnbConfig.PsppPolicy = PsppDisabled; + + /* Init Reset reconfigures ROM address registers */ + hudson_enable_lpc_rom(); } void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) @@ -33,9 +37,9 @@ void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) * UMA may or may not be cacheable, so Sub4GCacheTop could be * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ if (Post->MemConfig.UmaBase) - backup_top_of_low_cacheable(Post->MemConfig.UmaBase << 16); + backup_top_of_low_cacheable((Post->MemConfig.UmaBase << 16) - CONFIG_SMM_TSEG_SIZE); else - backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop - CONFIG_SMM_TSEG_SIZE); } void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 973eed8bbd4..42c61e5940e 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -8,6 +8,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select INTEL_GMA_ACPI select NEED_SMALL_2MB_PAGE_TABLES select USE_DDR3 + select UDK_2017_BINDING if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index 65b71d1cc34..e99053342d2 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -12,12 +12,15 @@ Device (PEGP) Device (DEV0) { Name(_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } Method (_PRT) { Return (\_SB.PCI0.IRQM (1)) } + + Name (_PRW, Package() { 9, 4 }) } Device (PEG1) @@ -32,12 +35,15 @@ Device (PEG1) Device (DEV0) { Name(_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } Method (_PRT) { Return (\_SB.PCI0.IRQM (2)) } + + Name (_PRW, Package() { 9, 4 }) } Device (PEG2) @@ -52,12 +58,15 @@ Device (PEG2) Device (DEV0) { Name(_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } Method (_PRT) { Return (\_SB.PCI0.IRQM (3)) } + + Name (_PRW, Package() { 9, 4 }) } Device (PEG6) @@ -72,10 +81,13 @@ Device (PEG6) Device (DEV0) { Name(_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } Method (_PRT) { Return (\_SB.PCI0.IRQM (4)) } + + Name (_PRW, Package() { 9, 4 }) } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 3db90865f76..1325556dd45 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -267,17 +267,17 @@ static void disable_peg(void) reg = pci_read_config32(dev, DEVEN); dev = pcidev_on_root(1, 2); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || !dev_is_active_bridge(dev)) { printk(BIOS_DEBUG, "Disabling PEG12.\n"); reg &= ~DEVEN_PEG12; } dev = pcidev_on_root(1, 1); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || !dev_is_active_bridge(dev)) { printk(BIOS_DEBUG, "Disabling PEG11.\n"); reg &= ~DEVEN_PEG11; } dev = pcidev_on_root(1, 0); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || !dev_is_active_bridge(dev)) { printk(BIOS_DEBUG, "Disabling PEG10.\n"); reg &= ~DEVEN_PEG10; } @@ -292,7 +292,7 @@ static void disable_peg(void) reg &= ~DEVEN_D4EN; } dev = pcidev_on_root(6, 0); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || !dev_is_active_bridge(dev)) { printk(BIOS_DEBUG, "Disabling PEG60.\n"); reg &= ~DEVEN_PEG60; } diff --git a/src/security/intel/cbnt/Kconfig b/src/security/intel/cbnt/Kconfig index c430123fcb1..c7323aeb412 100644 --- a/src/security/intel/cbnt/Kconfig +++ b/src/security/intel/cbnt/Kconfig @@ -8,6 +8,7 @@ config INTEL_CBNT_SUPPORT select INTEL_TXT # With CBnT the bootblock is set up as a CBnT IBB and needs a fixed size select TPM_MEASURED_BOOT_INIT_BOOTBLOCK if TPM_MEASURED_BOOT + select TPM_STARTUP_IGNORE_POSTINIT help Enables Intel Converged Bootguard and Trusted Execution Technology Support. This will enable one to add a Key Manifest (KM) and a Boot diff --git a/src/security/intel/cbnt/Makefile.mk b/src/security/intel/cbnt/Makefile.mk index e912bf0726d..19f75fdeaf5 100644 --- a/src/security/intel/cbnt/Makefile.mk +++ b/src/security/intel/cbnt/Makefile.mk @@ -5,6 +5,8 @@ ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y) all-y += logging.c ramstage-y += cmos.c +bootblock-$(CONFIG_TPM_MEASURED_BOOT) += measurement.c + # As specified in Intel Trusted Execution Technology and Boot Guard Server BIOS # Specification, document number # 558294 PK_HASH_ALG_SHA1:=4 @@ -91,7 +93,7 @@ $(obj)/bpm.bin: $(obj)/bpm_unsigned.bin $(CBNT_PROV) $(call strip_quotes, $(CONF $(call add_intermediate, add_bpm, $(obj)/bpm.bin) printf " CBNT Adding BPM\n" -$(CBFSTOOL) $< remove -n boot_policy_manifest.bin 2>/dev/null - $(CBFSTOOL) $< add -f $(obj)/bpm.bin -n boot_policy_manifest.bin -a 0x10 -t raw + $(CBFSTOOL) $< add -f $(obj)/bpm.bin -n boot_policy_manifest.bin -a 0x40 -t raw $(call add_intermediate, fit_bpm, set_fit_ptr add_bpm $(IFITTOOL)) printf " IFITTOOL Adding BPM\n" @@ -102,10 +104,11 @@ endif # CONFIG_INTEL_CBNT_BPM_ONLY_UNSIGNED else # CONFIG_INTEL_CBNT_GENERATE_BPM ifneq ($(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY),"") + cbfs-files-y += boot_policy_manifest.bin boot_policy_manifest.bin-file := $(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY) boot_policy_manifest.bin-type := raw -boot_policy_manifest.bin-align := 0x10 +boot_policy_manifest.bin-align := 0x40 $(call add_intermediate, add_bpm_fit, $(IFITTOOL) set_fit_ptr) $(IFITTOOL) -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< @@ -155,7 +158,7 @@ else cbfs-files-y += key_manifest.bin key_manifest.bin-file := $(KM_FILE) key_manifest.bin-type := raw -key_manifest.bin-align := 0x10 +key_manifest.bin-align := 0x40 $(call add_intermediate, add_km_fit, $(IFITTOOL) set_fit_ptr) $(IFITTOOL) -r COREBOOT -a -n key_manifest.bin -t 11 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< diff --git a/src/security/intel/cbnt/cbnt.h b/src/security/intel/cbnt/cbnt.h index 08011f59655..c70848a8100 100644 --- a/src/security/intel/cbnt/cbnt.h +++ b/src/security/intel/cbnt/cbnt.h @@ -10,7 +10,56 @@ #define CBNT_ERRORCODE (CBNT_BASE_ADDRESS + 0x30) #define CBNT_BOOTSTATUS (CBNT_BASE_ADDRESS + 0xa0) #define CBNT_BIOSACM_ERRORCODE (CBNT_BASE_ADDRESS + 0x328) +#define CBNT_BIOSACM_POLICY_STS (CBNT_BASE_ADDRESS + 0x378) + +/* Measured Boot, if set Boot Guard ACM mesures IBB to TPM. */ +#define CBNT_BP_TYPE_M (1 << 0) +/* Verified Boot, Boot Guard ACM verifies IBB. */ +#define CBNT_BP_TYPE_V (1 << 1) +/* High Assurance Platform, the bit that is used to instruct ME to halt right after paltform + initialization. */ +#define CBNT_BP_TYPE_HAP (1 << 2) +/* TXT Supported. */ +#define CBNT_BP_TYPE_T (1 << 3) +#define CBNT_BP_RESERVED1 (1 << 4) +/* Disable CPU debugging, if set DCI JTAG that would tamper with ACM execution is disabled. */ +#define CBNT_BP_RSTR_DCD (1 << 5) +/* Disable BSP #INIT, means to block INIT signals to mitigate code refetch. */ +#define CBNT_BP_RSTR_DBI (1 << 6) +/* Protect BIOS Environment, means Boot Guard ACM copies IBB to cache. */ +#define CBNT_BP_RSTR_PBE (1 << 6) +#define CBNT_BP_RESERVED2 (1 << 8) + +#define CBNT_EVENT_LOG_MESSAGE "Boot Guard Measured S-CRTM" + +union cbnt_biosacm_policy { + struct { + uint64_t km_id : 4; + uint64_t bp : 9; /* See CBNT_BP_* constants. */ + uint64_t tpm_type : 2; + uint64_t tpm_success : 1; + uint64_t: 1; + uint64_t pfr : 1; + uint64_t bckup_act : 2; + uint64_t txt_profile : 5; + uint64_t scrub_policy : 2; + uint64_t: 2; + uint64_t dma_protection : 1; + uint64_t: 2; + uint64_t scrtm_status : 3; + uint64_t cpu_co_signing : 1; + uint64_t tpm_startup_locality : 1; + uint64_t: 27; + } status; + uint64_t raw; +}; +_Static_assert(sizeof(union cbnt_biosacm_policy) == sizeof(uint64_t), + "Wrong size of cbnt_biosacm_policy"); void intel_cbnt_log_registers(void); +int intel_cbnt_get_locality(void); + +void intel_cbnt_inject_ibg_measurements(void); + #endif diff --git a/src/security/intel/cbnt/logging.c b/src/security/intel/cbnt/logging.c index 90d138d7c24..a60b5a99f1b 100644 --- a/src/security/intel/cbnt/logging.c +++ b/src/security/intel/cbnt/logging.c @@ -23,8 +23,9 @@ union sacm_info { uint64_t : 24; uint64_t btg_cap : 1; uint64_t : 1; - uint64_t txt_cap : 1; - uint64_t : 29; + uint64_t txt_server_cap : 1; + uint64_t no_rst_secrets_prot : 1; + uint64_t : 28; }; msr_t msr; uint64_t raw; @@ -41,12 +42,20 @@ static const char *const tpm_type[] = { union cbnt_bootstatus { struct { - uint64_t : 59; + uint64_t : 30; + uint64_t txt_startup_success : 1; + uint64_t btg_startup_success : 1; + uint64_t block_boot_en : 1; + uint64_t pfr_startup_success : 1; + uint64_t : 13; + uint64_t mem_pwr_down : 1; + uint64_t btg_failed : 1; + uint64_t : 10; uint64_t bios_trusted : 1; uint64_t txt_dis_pol : 1; uint64_t btg_startup_err : 1; uint64_t txt_err : 1; - uint64_t type7 : 1; + uint64_t sacm_success : 1; }; uint64_t raw; }; @@ -102,7 +111,6 @@ union cbnt_biosacm_errorcode { _Static_assert(sizeof(union cbnt_biosacm_errorcode) == sizeof(uint32_t), "Wrong size of cbnt_biosacm_errorcode"); - static const char *decode_err_type(uint8_t type) { switch (type) { @@ -117,6 +125,36 @@ static const char *decode_err_type(uint8_t type) } } +static const char* backup_actions[] = { + "Memory Power Down", + "BtG Unbreakable Shutdown", + "PFR Recovery", + "Reserved", +}; + +static const char* scrub_policies[] = { + "Default - trust valid BIOS to scrub memory", + "BIOS action to scrub memory.", + "ACM action to scrub memory", + "Reserved", +}; + +static const char *decode_scrtm_status(uint8_t status) +{ + switch (status) { + case 0: + return "None"; + case 1: + return "Boot Guard established"; + case 2: + return "TXT established"; + case 4: + return "PFR established"; + default: + return "Reserved"; + } +} + void intel_cbnt_log_registers(void) { const union sacm_info acm_info = { .msr = rdmsr(MSR_BOOT_GUARD_SACM_INFO) }; @@ -129,17 +167,24 @@ void intel_cbnt_log_registers(void) LOG(" verified boot: %u\n", acm_info.verified_boot); LOG(" revoked: %u\n", acm_info.revoked); LOG(" BtG capable: %u\n", acm_info.btg_cap); - LOG(" TXT capable: %u\n", acm_info.txt_cap); + LOG(" Server TXT capable: %u\n", acm_info.txt_server_cap); + LOG(" RST Secrets Protection: %s\n", acm_info.no_rst_secrets_prot? "no" : "yes"); const union cbnt_bootstatus btsts = { .raw = read64p(CBNT_BOOTSTATUS), }; LOG("BOOTSTATUS (0xA0) raw: 0x%016llx\n", btsts.raw); + LOG(" TXT startup success: %u\n", btsts.bios_trusted); + LOG(" BtG startup success: %u\n", btsts.bios_trusted); + LOG(" Block boot: %s\n", btsts.block_boot_en ? "enabled" : "disabled"); + LOG(" PFR startup success: %u\n", btsts.bios_trusted); + LOG(" Memory power down: %sexecuted\n", btsts.mem_pwr_down ? "" : "not "); + LOG(" BtG failed: %s\n", btsts.btg_failed ? "yes" : "no"); LOG(" Bios trusted: %u\n", btsts.bios_trusted); LOG(" TXT disabled by policy: %u\n", btsts.txt_dis_pol); - LOG(" Bootguard startup error: %u\n", btsts.btg_startup_err); + LOG(" BtG startup error: %u\n", btsts.btg_startup_err); LOG(" TXT ucode or ACM error: %u\n", btsts.txt_err); - LOG(" TXT measurement type 7: %u\n", btsts.type7); + LOG(" S-ACM success: %s\n", btsts.sacm_success ? "yes" : "no"); const union cbnt_errorcode err = { .raw = read32p(CBNT_ERRORCODE), @@ -190,4 +235,37 @@ void intel_cbnt_log_registers(void) LOG(" KMID: 0x%x\n", biosacm_err.btg.km_id); LOG(" BootPolicies: 0x%x\n", biosacm_err.btg.bp); } + + const union cbnt_biosacm_policy biosacm_sts = { + .raw = read64p(CBNT_BIOSACM_POLICY_STS), + }; + + LOG("CBNT_BIOSACM_POLICY_STS (0x378) raw: 0x%016llx\n", biosacm_sts.raw); + LOG(" KMID: 0x%x\n", biosacm_sts.status.km_id); + LOG(" Boot policies : 0x%x\n", biosacm_sts.status.bp); + LOG(" TPM type: %s\n", tpm_type[biosacm_sts.status.tpm_type]); + LOG(" TPM success: %s\n", biosacm_sts.status.tpm_success ? "yes" : "no"); + LOG(" PFR supported: %s\n", biosacm_sts.status.pfr ? "yes" : "no"); + LOG(" Backup action: %s\n", backup_actions[biosacm_sts.status.bckup_act]); + + if (biosacm_sts.status.txt_profile == 1) + LOG(" TXT Profile: " + "B - BIOS is trusted to create alias-free memory topology\n"); + else if (biosacm_sts.status.txt_profile == 2) + LOG(" TXT Profile: " + "D - BIOS runs ACHECK to verify alias-free topology\n"); + else + LOG(" TXT Profile: Unknown\n"); + + LOG(" Memory scrubbing policy: %s\n", scrub_policies[biosacm_sts.status.scrub_policy]); + LOG(" IBB DMA protection: %s\n", biosacm_sts.status.dma_protection ? + "enabled" : "disabled"); + LOG(" S-CRTM status: %s\n", + decode_scrtm_status(biosacm_sts.status.scrtm_status)); + LOG(" CPU Co-signing: %s\n", biosacm_sts.status.cpu_co_signing ? + "enabled" : "disabled"); + LOG(" TPM Startup locality: %d\n", + biosacm_sts.status.tpm_startup_locality ? 0 : 3); + + } diff --git a/src/security/intel/cbnt/measurement.c b/src/security/intel/cbnt/measurement.c new file mode 100644 index 00000000000..2e9aa956dc8 --- /dev/null +++ b/src/security/intel/cbnt/measurement.c @@ -0,0 +1,831 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TPM_ALG_RSA 0x0001 +#define TPM_ALG_ECC 0x0023 + +#define TPM_ALG_RSASSA 0x0014 +#define TPM_ALG_RSAPSS 0x0016 +#define TPM_ALG_ECDSA 0x0018 +#define TPM_ALG_SM2 0x001b + +/* Bits of `struct bpm_ibbs::flags`. */ +#define BPM_IBBS_FLAG_RESERVED1 (1 << 0) /* must be set to 1 */ +#define BPM_IBBS_FLAG_RESERVED2 (1 << 1) /* must be set to 1 */ +#define BPM_IBBS_FLAG_AUTH_MEASURE (1 << 2) /* extend PCR-7 */ +#define BPM_IBBS_FLAG_CAP_PCRS_ON_TPM_FAIL (1 << 3) +#define BPM_IBBS_FLAG_TOP_SWAP_SUPPORTED (1 << 4) +#define BPM_IBBS_FLAG_FORCE_TME (1 << 5) +#define BPM_IBBS_FLAG_FORCE_IGN (1 << 6) +#define BPM_IBBS_FLAG_SRTM_AC (1 << 7) /* attestation control */ + +/* Mask applied to ACM_POLICY_STATUS when BPM_IBBS_FLAG_SRTM_AC is set. */ +#define SRTM_AC_MASK 0x20FFF + +/* Bits of `struct km_hash::usage` indicating to which public key the hash corresponds. */ +#define KM_HASH_USAGE_BPM (1 << 0) +#define KM_HASH_USAGE_FIT (1 << 1) +#define KM_HASH_USAGE_ACM (1 << 2) +#define KM_HASH_USAGE_SDEV (1 << 3) +#define KM_HASH_USAGE_PFR_CPLD (1 << 4) + +/* + * SRTM version is an upper-case hex dump of ACM's "Date" (offset 20) and "TXT SVN" (offset 28) + * fields as a NUL-terminated UTF16 string. + */ +#define SCRTM_VERSION_LENGTH 13 + +/* + * Definitions of the structures come from Intel document #575623 CBnT BWG v1.2.5 ("Intel + * Converged Boot Guard and Intel Trusted Execution Technology (Intel TXT) BIOS Specification"). + * + * Versions in structures could be different for other revisions of the document. + */ + +/* Header of the Boot Policy Manifest. */ +struct bpm_header { + char structure_id[8]; /* "__ACBP__" */ + uint8_t struct_ver; /* 0x24 */ + uint8_t hdr_struct_ver; /* 0x20 */ + uint16_t hdr_size; + uint16_t key_sig_offset; /* offset to KeySignature field of Policy Manifest Signature + Element (PMSE) */ + uint8_t bpm_revision; + uint8_t bpm_svn; + uint8_t acmsvn_auth; + uint8_t reserved; + uint16_t nem_data_stack; /* in 4 KiB pages */ + uint8_t se_element[]; +} __packed; + +/* Deprecated uses must be initialized as { .alg = TPM_ALG_NULL (0x10), .size = 0 } */ +struct hash_struct { + uint16_t alg; + uint16_t size; + uint8_t data[]; +} __packed; + +struct bpm_hash_list { + uint16_t size; + uint16_t count; + struct hash_struct hashes[]; +} __packed; + +/* IBB Segment Element (upper part) */ +struct bpm_ibbs { + char structure_id[8]; /* "__IBBS__" */ + uint8_t struct_ver; /* 0x21 */ + uint8_t reserved1; + uint16_t element_size; + uint8_t reserved2; + uint8_t set_number; /* 0 */ + uint8_t reserved3; + uint8_t pbet_value; + uint32_t flags; /* see BPM_IBBS_FLAG_* constants for values */ + uint64_t iommu_bar0; + uint64_t iommu_bar1; + uint32_t dma_prot_base0; + uint32_t dma_prot_limit0; + uint64_t dma_prot_base1; + uint64_t dma_prot_limit1; + struct hash_struct post_ibb_hash; /* deprecated since v1.2.0 of CBnT BWG */ + uint32_t ibb_entry_point; + struct bpm_hash_list digest_list; /* each entry is of variable size */ + /* struct bpm_ibbs_bottom bottom; */ +} __packed; + +/* IBB Segment Element (lower part) */ +struct bpm_ibbs_bottom { + struct hash_struct obb_hash; /* deprecated since v1.2.0 of CBnT BWG */ + uint8_t reserved4[3]; + uint8_t segment_count; + /* ibb_segments[segment_count]; */ +} __packed; + +/* KMHASH_STRUCT */ +struct km_hash { + uint64_t usage; /* see KM_HASH_USAGE_* constants for values */ + struct hash_struct hash; +} __packed; + +/* Key Manifest */ +struct km_header { + char structure_id[8]; /* "__KEYM__" */ + uint8_t struct_ver; /* 0x21 */ + uint8_t reserved1[3]; + uint16_t key_sig_offset; + uint8_t reserved2[3]; + uint8_t km_revision; + uint8_t km_svn; + uint8_t km_id; + uint16_t km_pub_key_hash_alg; + uint16_t key_count; + struct km_hash key_hash[]; /* of variable size */ + /* key_sig_offset points here where Key Manifest Signature data is one + of 2 Key Signature Structure formats: RSA or ECC / SM2. */ +} __packed; + +static const void *find_in_fit(uint8_t type, size_t *size) +{ + struct fit_entry *entry = fit_table_search(type); + if (entry == NULL) { + printk(BIOS_ERR, "CBnT: failed to find FIT entry: %#02x\n", type); + return NULL; + } + + void *addr = (void *)(uintptr_t)entry->address.u64; + + const struct acm_header_v0 *acm; + switch (type) { + case FIT_ENTRY_TYPE_SACM: + if (fit_entry_type(&entry[1]) == FIT_ENTRY_TYPE_SACM) { + /* A BIOS image can include more than Startup ACM, but this function + always returns the first one which might be wrong. */ + printk(BIOS_WARNING, "CBnT: picking SACM from FIT at random!\n"); + } + + /* All known versions of the header (up to v5.4) have compatible version and + size fields. */ + acm = (const struct acm_header_v0 *)addr; + if (acm->header_version[1] > 5 || acm->header_version[0] > 4) { + printk(BIOS_ERR, "CBnT: unsupported version of SACM: %d.%d\n", + acm->header_version[1], acm->header_version[0]); + return NULL; + } + + *size = acm->size * 4; + break; + case FIT_ENTRY_TYPE_KM: + if (fit_entry_type(&entry[1]) == FIT_ENTRY_TYPE_KM) { + /* A BIOS image can include more than one manifest, but this function + always returns the first one which might be wrong. */ + printk(BIOS_WARNING, + "CBnT: picking Key Manifest from FIT at random!\n"); + } + *size = fit_entry_size(entry); + break; + case FIT_ENTRY_TYPE_BPM: + *size = fit_entry_size(entry); + break; + + default: + printk(BIOS_ERR, "CBnT: unexpected FIT entry type: %#02x\n", type); + return NULL; + } + + return addr; +} + +static enum cb_err get_flags(bool *conventional_measurements, bool *auth_measure, + uint64_t *biosacm_sts_mask) +{ + size_t bpm_len; + const struct bpm_header *bpm = find_in_fit(FIT_ENTRY_TYPE_BPM, &bpm_len); + if (bpm == NULL) { + printk(BIOS_ERR, "CBnT: failed to find BPM\n"); + return CB_ERR; + } + + /* Meteor Lake seems to be the first generation with new (more TCG-like) style of + measurements. */ + *conventional_measurements = !CONFIG(SOC_INTEL_METEORLAKE) + && !CONFIG(SOC_INTEL_PANTHERLAKE_BASE); + + const struct bpm_ibbs *ibbs = (const void *)bpm->se_element; + *auth_measure = (ibbs->flags & BPM_IBBS_FLAG_AUTH_MEASURE) != 0; + *biosacm_sts_mask = + (ibbs->flags & BPM_IBBS_FLAG_SRTM_AC) != 0 ? SRTM_AC_MASK : ~(uint64_t)0; + + /* Auth data is measured only for TPM2. */ + if (*auth_measure && tlcl_get_family() != TPM_2) + *auth_measure = false; + + return CB_SUCCESS; +} + +static enum cb_err copy_acm_signature(struct obuf *ob) +{ + /* Not running any checks on the ACM like TXT code does, it must be correct if we got + here. */ + size_t acm_len; + const struct acm_header_v3 *acm = find_in_fit(FIT_ENTRY_TYPE_SACM, &acm_len); + if (acm == NULL) { + printk(BIOS_ERR, "CBnT: failed to find SACM\n"); + return CB_ERR; + } + + /* Versions v3.0 through v5.4 support CBnT and have this field in the same place. */ + int err = obuf_write(ob, acm->rsa3072_sig, sizeof(acm->rsa3072_sig)); + if (err) + printk(BIOS_ERR, "CBnT: failed to write ACM signature\n"); + + return err ? CB_ERR : CB_SUCCESS; +} + +static enum cb_err fill_pcr0_acm_fields(struct obuf *ob) +{ + /* Not running any checks on the ACM like TXT code does, it must be correct if we got + here. */ + size_t acm_len; + const struct acm_header_v3 *acm = find_in_fit(FIT_ENTRY_TYPE_SACM, &acm_len); + if (acm == NULL) { + printk(BIOS_ERR, "CBnT: failed to find SACM\n"); + return CB_ERR; + } + + /* + * ACM.Header.SVN (won't run out of space on this one). + * All known versions of the header (up to v5.4) have compatible txt_svn field. + */ + (void)obuf_write_le16(ob, acm->txt_svn); + + return copy_acm_signature(ob); +} + +static enum cb_err skip_signature_key(struct ibuf *ib, uint16_t *key_alg) +{ + if (ibuf_read_le16(ib, key_alg)) { + printk(BIOS_ERR, "CBnT: failed to read key algorithm\n"); + return CB_ERR; + } + if (*key_alg != TPM_ALG_RSA && *key_alg != TPM_ALG_ECC) { + printk(BIOS_ERR, "CBnT: unexpected public key algorithm: %#04x\n", *key_alg); + return CB_ERR; + } + + uint8_t key_version; + if (ibuf_read_le8(ib, &key_version)) { + printk(BIOS_ERR, "CBnT: failed to read public key version\n"); + return CB_ERR; + } + if (key_version != 0x10) { + printk(BIOS_ERR, "CBnT: unexpected version of public key: %#02x\n", + key_version); + return CB_ERR; + } + + uint16_t key_size; + if (ibuf_read_le16(ib, &key_size)) { + printk(BIOS_ERR, "CBnT: failed to read public key size\n"); + return CB_ERR; + } + + if (*key_alg == TPM_ALG_RSA) { + (void)ibuf_oob_drain(ib, 4); /* public exponent */ + (void)ibuf_oob_drain(ib, key_size / 8); /* the public key */ + } else if (*key_alg == TPM_ALG_ECC) { + (void)ibuf_oob_drain(ib, key_size / 8); /* Qx */ + (void)ibuf_oob_drain(ib, key_size / 8); /* Qy */ + } + + return CB_SUCCESS; +} + +/* Copies a signature after parsing "RSA Key Signature Structure Format" or + "ECC / SM2 Key Signature Structure Format". */ +static enum cb_err copy_signature(struct ibuf ib, struct obuf *ob) +{ + uint8_t key_version; + if (ibuf_read_le8(&ib, &key_version)) { + printk(BIOS_ERR, "CBnT: failed to read key signature version\n"); + return CB_ERR; + } + if (key_version != 0x10) { + printk(BIOS_ERR, "CBnT: unexpected key signature version: %#02x\n", + key_version); + return CB_ERR; + } + + uint16_t key_alg; + if (skip_signature_key(&ib, &key_alg) != CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to skip signature key\n"); + return CB_ERR; + } + + uint16_t sig_scheme; + if (ibuf_read_le16(&ib, &sig_scheme)) { + printk(BIOS_ERR, "CBnT: failed to read signature scheme\n"); + return CB_ERR; + } + if (key_alg == TPM_ALG_RSA) { + if (sig_scheme != TPM_ALG_RSASSA && sig_scheme != TPM_ALG_RSAPSS) { + printk(BIOS_ERR, "CBnT: unexpected public signature scheme: %#04x\n", + sig_scheme); + return CB_ERR; + } + } else if (key_alg == TPM_ALG_ECC) { + if (sig_scheme != TPM_ALG_ECDSA && sig_scheme != TPM_ALG_SM2) { + printk(BIOS_ERR, "CBnT: unexpected public signature scheme: %#04x\n", + sig_scheme); + return CB_ERR; + } + } + + uint8_t version; + if (ibuf_read_le8(&ib, &version)) { + printk(BIOS_ERR, "CBnT: failed to read signature version\n"); + return CB_ERR; + } + if (version != 0x10) { + printk(BIOS_ERR, "CBnT: unexpected signature version: %#02x\n", version); + return CB_ERR; + } + + uint16_t size; + if (ibuf_read_le16(&ib, &size)) { + printk(BIOS_ERR, "CBnT: failed to read signature size\n"); + return CB_ERR; + } + + uint16_t hash_alg; + if (ibuf_read_le16(&ib, &hash_alg)) { + printk(BIOS_ERR, "CBnT: failed to read hash algorithm of signature\n"); + return CB_ERR; + } + + size_t sig_size = 0; + if (key_alg == TPM_ALG_RSA) { + sig_size += size / 8; /* the signature */ + } else if (key_alg == TPM_ALG_ECC) { + sig_size += size / 8; /* R */ + sig_size += size / 8; /* S */ + } + + const void *sig_data = ibuf_oob_drain(&ib, sig_size); + if (sig_data == NULL) { + printk(BIOS_ERR, "CBnT: failed to read signature\n"); + return CB_ERR; + } + + if (obuf_write(ob, sig_data, sig_size)) { + printk(BIOS_ERR, "CBnT: failed to write signature\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +static enum cb_err copy_km_signature(struct obuf *ob) +{ + size_t km_len; + const struct km_header *km = find_in_fit(FIT_ENTRY_TYPE_KM, &km_len); + if (km == NULL) { + printk(BIOS_ERR, "CBnT: failed to find KM\n"); + return CB_ERR; + } + + struct ibuf km_sig_ib; + ibuf_init(&km_sig_ib, (const uint8_t *)km + km->key_sig_offset, + km_len - km->key_sig_offset); + + /* KM.Signature[KM signature size] */ + enum cb_err err = copy_signature(km_sig_ib, ob); + if (err != CB_SUCCESS) + printk(BIOS_ERR, "CBnT: failed to copy KM signature\n"); + + return err; +} + +/* Finds public key used to sign Key Manifest and hashes it with the algorithm specified in the + header. */ +static enum cb_err hash_signature_key(const struct km_header *km, size_t km_len, + struct vb2_hash *hash) +{ + /* All safety checks are in skip_signature_key() which is always run for PCR-0, so not + bothering here for optional PCR-7 which is also computed after PCR-0. */ + struct ibuf sig_ib; + ibuf_init(&sig_ib, (uint8_t *)km + km->key_sig_offset, km_len - km->key_sig_offset); + + uint16_t key_alg; + (void)ibuf_read_le16(&sig_ib, &key_alg); + + (void)ibuf_oob_drain(&sig_ib, 1); /* key signature version */ + (void)ibuf_oob_drain(&sig_ib, 2); /* key algorithm */ + (void)ibuf_oob_drain(&sig_ib, 1); /* key version */ + + uint16_t key_size; + (void)ibuf_read_le16(&sig_ib, &key_size); + + size_t key_data_size = 0; + if (key_alg == TPM_ALG_RSA) + key_data_size = 4 + key_size / 8; /* public exponent and public key */ + else if (key_alg == TPM_ALG_ECC) + key_data_size = (key_size / 8) * 2; /* Qx + Qy */ + + if (vb2_hash_calculate(vboot_hwcrypto_allowed(), ibuf_oob_drain(&sig_ib, key_data_size), + key_data_size, tpm2_alg_to_vb2_hash(km->km_pub_key_hash_alg), + hash)) { + printk(BIOS_ERR, "CBnT: failed to hash PCR-0 measurement data\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +static enum cb_err fill_pcr7_km_fields(struct obuf *ob) +{ + size_t km_len; + const struct km_header *km = find_in_fit(FIT_ENTRY_TYPE_KM, &km_len); + + struct vb2_hash km_pubkey_hash; + if (hash_signature_key(km, km_len, &km_pubkey_hash) != CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to hash Key Manifest's signature key\n"); + return CB_ERR; + } + + /* BP.KEY (hash of public part of the key used to sign Key Manifest) */ + if (obuf_write(ob, km_pubkey_hash.raw, vb2_digest_size(km_pubkey_hash.algo))) { + printk(BIOS_ERR, + "CBnT: failed to write hash of Key Manifest's signature key\n"); + return CB_ERR; + } + + /* Find hash that corresponds to BPM. */ + const struct km_hash *key_hash = km->key_hash; + unsigned int i; + for (i = 0; i < km->key_count; ++i) { + if (key_hash->usage & KM_HASH_USAGE_BPM) + break; + key_hash = (const struct km_hash *)&key_hash->hash.data[key_hash->hash.size]; + } + if (i == km->key_count) { + printk(BIOS_ERR, "CBnT: failed to find hash of BPM pubkey in KM\n"); + return CB_ERR; + } + + /* KM.BPKey.hashBuffer[BPM pubkey digest size] */ + if (obuf_write(ob, key_hash->hash.data, key_hash->hash.size)) { + printk(BIOS_ERR, "CBnT: failed to write ACM signature\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +static enum cb_err copy_ibb_hash(struct obuf *ob, uint16_t tpm2_alg) +{ + size_t bpm_len; + const struct bpm_header *bpm = find_in_fit(FIT_ENTRY_TYPE_BPM, &bpm_len); + if (bpm == NULL) { + printk(BIOS_ERR, "CBnT: failed to find BPM\n"); + return CB_ERR; + } + + unsigned int i; + const struct bpm_ibbs *ibbs = (const void *)bpm->se_element; + const struct hash_struct *ibb_hash = ibbs->digest_list.hashes; + for (i = 0; i < ibbs->digest_list.count; ++i) { + if (ibb_hash->alg == tpm2_alg) + break; + ibb_hash = (const void *)&ibb_hash->data[ibb_hash->size]; + } + + if (i == ibbs->digest_list.count) { + printk(BIOS_ERR, "CBnT: failed to find matching IBB digest\n"); + return CB_ERR; + } + + /* IBB.Digest[IBB digest size] */ + if (obuf_write(ob, ibb_hash->data, ibb_hash->size)) { + printk(BIOS_ERR, "CBnT: failed to write IBB digest\n"); + return CB_ERR; + } + + return CB_SUCCESS; +} + +static enum cb_err copy_bpm_signature(struct obuf *ob) +{ + size_t bpm_len; + const struct bpm_header *bpm = find_in_fit(FIT_ENTRY_TYPE_BPM, &bpm_len); + if (bpm == NULL) { + printk(BIOS_ERR, "CBnT: failed to find BPM\n"); + return CB_ERR; + } + + struct ibuf bpm_sig_ib; + ibuf_init(&bpm_sig_ib, (const uint8_t *)bpm + bpm->key_sig_offset, + bpm_len - bpm->key_sig_offset); + + /* BPM.Signature[BPM signature size] */ + if (copy_signature(bpm_sig_ib, ob) != CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to copy BPM signature\n"); + return CB_ERR; + } + + return copy_ibb_hash(ob, tpm2_alg_from_vb2_hash(tpm_log_alg())); +} + +/* + * Pseudo-code of the data to be measured into PCR-7 for TigerLake and newer (older hardware + * isn't supported): + * + * struct { + * uint64_t ACM_POLICY_STATUS; + * uint16_t ACM.Header.SVN; + * uint8_t ACM.KeyHash[32]; + * uint8_t BP.KEY[32 or 48]; // Hash of the public key from Key Manifest's signature. + * uint8_t KM.BPKey.hashBuffer[BPM pubkey digest size]; + * } PCR7_DATA + * + * Applies only for TPM2.0. + * + * Returns true and initializes *hash on success. + */ +static bool make_pcr7_hash(struct obuf *ob, struct vb2_hash *hash) +{ + /* + * ACM.KeyHash[32] + * + * BTG BWG says to use TXT.PUBLIC.KEY, but TXT SDG (#315168-017.4) and CBnT BWG say + * that it doesn't contain anything useful on modern platforms utilizing SGX and + * suggests to use MSRs 0x20::0x23. + */ + (void)obuf_write_le64(ob, rdmsr(MSR_ACM_CPU_KEY_HASH_0).raw); + (void)obuf_write_le64(ob, rdmsr(MSR_ACM_CPU_KEY_HASH_1).raw); + (void)obuf_write_le64(ob, rdmsr(MSR_ACM_CPU_KEY_HASH_2).raw); + (void)obuf_write_le64(ob, rdmsr(MSR_ACM_CPU_KEY_HASH_3).raw); + + if (fill_pcr7_km_fields(ob) != CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to fill KM fields of PCR-7 measurement data\n"); + return false; + } + + size_t size; + const void *data = obuf_contents(ob, &size); + if (vb2_hash_calculate(vboot_hwcrypto_allowed(), data, size, tpm_log_alg(), hash)) { + printk(BIOS_ERR, "CBnT: failed to hash PCR-7 measurement data\n"); + return false; + } + + return true; +} + +int intel_cbnt_get_locality(void) +{ + /* Startup locality is always 0 for TPM 1.2. */ + if (tlcl_get_family() == TPM_1) + return 0; + + union cbnt_biosacm_policy biosacm_sts = { + .raw = read64p(CBNT_BIOSACM_POLICY_STS), + }; + + /* It's 0 without active CBnT. */ + if (biosacm_sts.status.scrtm_status == 0) + return 0; + + return biosacm_sts.status.tpm_startup_locality == 0 ? 3 : 0; +} + +static enum cb_err cap_pcrs(union cbnt_biosacm_policy biosacm_sts) +{ + /* TODO: when adding support of all active PCR banks to Measured Boot, implement + capping those PCRs for which there is no corresponding IBB digest in BPM. */ + + /* Nothing to do if there was no TPM failure. */ + if (biosacm_sts.status.tpm_success) + return CB_SUCCESS; + + size_t bpm_len; + const struct bpm_header *bpm = find_in_fit(FIT_ENTRY_TYPE_BPM, &bpm_len); + if (bpm == NULL) { + printk(BIOS_ERR, "CBnT: failed to find BPM\n"); + return CB_ERR; + } + + const struct bpm_ibbs *ibbs = (const void *)bpm->se_element; + + /* Alternative to capping is disabling the TPM which requires no event log entries. */ + if (!(ibbs->flags & BPM_IBBS_FLAG_CAP_PCRS_ON_TPM_FAIL)) + return CB_SUCCESS; + + const uint32_t separator = 0x00000001; + struct vb2_hash hash; + if (vb2_hash_calculate(vboot_hwcrypto_allowed(), &separator, sizeof(separator), + tpm_log_alg(), &hash)) { + printk(BIOS_ERR, "CBnT: failed to hash PCR separator\n"); + return CB_ERR; + } + + for (int pcr = 0; pcr < 8; pcr++) { + tpm_log_add_table_entry("CBnT hit TPM failure during boot", pcr, hash.algo, + hash.raw, vb2_digest_size(hash.algo)); + printk(BIOS_INFO, "CBnT: capped PCR-%d\n", pcr); + } + return CB_SUCCESS; +} + +static char hex_digit(int nibble) +{ + if (nibble < 10) + return '0' + nibble; + return 'A' + nibble - 10; +} + +void intel_cbnt_inject_ibg_measurements(void) +{ + const union cbnt_biosacm_policy biosacm_sts = { + .raw = read64p(CBNT_BIOSACM_POLICY_STS), + }; + + /* Do nothing if BootGuard wasn't involved in the boot process. */ + if (biosacm_sts.status.scrtm_status == 0) + return; + + /* Do nothing if BootGuard doesn't measure anything. */ + if (!(biosacm_sts.status.bp & CBNT_BP_TYPE_M)) + return; + + if (cap_pcrs(biosacm_sts) != CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to cap PCRs\n"); + return; + } + + /* cap_pcrs() must have logged that PCRs were capped, nothing else to do on TPM + error. */ + if (!biosacm_sts.status.tpm_success) { + printk(BIOS_ERR, "CBnT: TPM failure detected\n"); + return; + } + + bool conventional_measurements; + bool auth_measure; + uint64_t biosacm_sts_mask; + if (get_flags(&conventional_measurements, &auth_measure, &biosacm_sts_mask) != + CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to obtain IBBS flags from BPM\n"); + return; + } + + /* + * Allow for 4 8192-bit digests in PCR-0 measurements which is an unlikely situation, + * so this buffer should be enough to not run out of space (data measured into PCR-7 is + * smaller). + */ + uint8_t data[sizeof(uint64_t) + sizeof(uint16_t) + 4 * KiB]; + struct obuf data_ob; + obuf_init(&data_ob, data, sizeof(data)); + + if (conventional_measurements) { + /* + * Making and hashing PCR-0 data. + * + * Pseudo-code of the data to be measured into PCR-0 for TigerLake and newer + * (older hardware isn't supported yet): + * + * struct { + * uint64_t ACM_POLICY_STATUS; + * uint16_t ACM.Header.SVN; + * uint8_t ACM.Signature[ACM signature size]; + * uint8_t KM.Signature[KM signature size]; + * uint8_t BPM.Signature[BPM signature size]; + * uint8_t IBB.Digest[IBB digest size]; + * } PCR0_DATA; + */ + + /* ACM_POLICY_STATUS (won't run out of space on this one) */ + (void)obuf_write_le64(&data_ob, biosacm_sts.raw & biosacm_sts_mask); + + if (fill_pcr0_acm_fields(&data_ob) != CB_SUCCESS) { + printk(BIOS_ERR, + "CBnT: failed to fill ACM fields of PCR-0 measurement data\n"); + return; + } + + if (copy_km_signature(&data_ob) != CB_SUCCESS) { + printk(BIOS_ERR, + "CBnT: failed to copy KM signature for PCR-0 measurement\n"); + return; + } + + if (copy_bpm_signature(&data_ob) != CB_SUCCESS) { + printk(BIOS_ERR, + "CBnT: failed to copy BPM signature for PCR-0 measurement\n"); + return; + } + + struct vb2_hash hash; + if (vb2_hash_calculate(vboot_hwcrypto_allowed(), data, + obuf_nr_written(&data_ob), tpm_log_alg(), &hash)) { + printk(BIOS_ERR, "CBnT: failed to hash PCR-0 measurement data\n"); + return; + } + + /* Per BWG this should be logged with EV_S_CRTM_CONTENTS type. */ + tpm_log_add_table_entry(CBNT_EVENT_LOG_MESSAGE, 0, hash.algo, hash.raw, + vb2_digest_size(hash.algo)); + + /* Optionally making and hashing PCR-7 data (not supported since MTL). */ + if (auth_measure) { + /* Reuse the first 2 fields of PCR-0 data which are identical in both + cases. */ + obuf_init(&data_ob, data, sizeof(data)); + (void)obuf_oob_fill(&data_ob, sizeof(uint64_t) + sizeof(uint16_t)); + + if (!make_pcr7_hash(&data_ob, &hash)) { + printk(BIOS_ERR, + "CBnT: failed to build and hash PCR-7 measurement data\n"); + return; + } + + /* Per BWG this should be logged with EV_EFI_VARIABLE_DRIVER_CONFIG type + and event name should be a Unicode string. */ + tpm_log_add_table_entry(CBNT_EVENT_LOG_MESSAGE, 7, hash.algo, hash.raw, + vb2_digest_size(hash.algo)); + printk(BIOS_INFO, "CBnT: reconstructed PCR-7 measurement\n"); + } + + } else { + size_t acm_len; + const struct acm_header_v3 *acm = find_in_fit(FIT_ENTRY_TYPE_SACM, &acm_len); + if (acm == NULL) { + printk(BIOS_ERR, "CBnT: failed to find SACM\n"); + return; + } + + uint8_t crtm_version[6]; + memcpy(&crtm_version[0], &acm->date, 4); + memcpy(&crtm_version[4], &acm->txt_svn, 2); + + char crtm_version_str[SCRTM_VERSION_LENGTH] = {0}; + uint16_t crtm_version_utf16[SCRTM_VERSION_LENGTH] = {0}; + for (int i = 0; i < sizeof(crtm_version); ++i) { + crtm_version_str[i*2 + 0] = hex_digit(crtm_version[i] >> 4); + crtm_version_str[i*2 + 1] = hex_digit(crtm_version[i] & 0xf); + + crtm_version_utf16[i*2 + 0] = crtm_version_str[i*2 + 0]; + crtm_version_utf16[i*2 + 1] = crtm_version_str[i*2 + 1]; + } + + struct vb2_hash hash; + if (vb2_hash_calculate(vboot_hwcrypto_allowed(), crtm_version_utf16, + sizeof(crtm_version_utf16), tpm_log_alg(), &hash)) { + printk(BIOS_ERR, "CBnT: failed to hash CRTM version\n"); + return; + } + /* Per BWG this should be logged with EV_S_CRTM_VERSION type. */ + tpm_log_add_table_entry(crtm_version_str, 0, hash.algo, hash.raw, + vb2_digest_size(hash.algo)); + + if (copy_ibb_hash(&data_ob, tpm2_alg_from_vb2_hash(tpm_log_alg())) != + CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to obtain IBB digest\n"); + return; + } + /* Per BWG this should be logged with EV_POST_CODE type. */ + tpm_log_add_table_entry("Boot Guard Measured IBB", 0, tpm_log_alg(), data, + obuf_nr_written(&data_ob)); + + /* + * struct { + * uint64_t ACM_POLICY_STATUS; + * uint8_t KM.Signature[KM signature size]; + * uint8_t BPM.Signature[BPM signature size]; + * } POLICY_DATA; + */ + obuf_init(&data_ob, data, sizeof(data)); + + /* ACM_POLICY_STATUS (won't run out of space on this one) */ + (void)obuf_write_le64(&data_ob, biosacm_sts.raw & biosacm_sts_mask); + if (copy_acm_signature(&data_ob) != CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to copy ACM signature\n"); + return; + } + if (copy_km_signature(&data_ob) != CB_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to copy KM signature\n"); + return; + } + if (copy_bpm_signature(&data_ob) != CB_SUCCESS) { + printk(BIOS_ERR, + "CBnT: failed to copy BPM signature for PCR-0 measurement\n"); + return; + } + if (vb2_hash_calculate(vboot_hwcrypto_allowed(), data, + obuf_nr_written(&data_ob), tpm_log_alg(), &hash)) { + printk(BIOS_ERR, "CBnT: failed to hash POLICY_DATA\n"); + return; + } + /* Per BWG this should be logged with EV_POST_CODE type. */ + if (tpm_extend_pcr(0, hash.algo, hash.raw, vb2_digest_size(hash.algo), + "BIOS Measured Boot Guard Policy") != TPM_SUCCESS) { + printk(BIOS_ERR, "CBnT: failed to extend POLICY_DATA\n"); + return; + } + } + + /* + * BWG suggests to Perform reconstruction at this point, but we are likely to continue + * the boot anyway as Measured Boot failures generally aren't fatal and incorrect hash + * will be caught later during the boot process. So not bothering. + */ +} diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 637a6a787b0..69ba95ae0bc 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -16,6 +16,7 @@ config INTEL_TXT select ENABLE_VMX if CPU_INTEL_COMMON select AP_IN_SIPI_WAIT select TPM_MEASURED_BOOT_INIT_BOOTBLOCK if TPM_MEASURED_BOOT + select TPM_STARTUP_IGNORE_POSTINIT depends on TPM depends on PLATFORM_HAS_DRAM_CLEAR depends on (SOC_INTEL_COMMON_BLOCK_SA || HAVE_CF9_RESET) diff --git a/src/security/intel/txt/Makefile.mk b/src/security/intel/txt/Makefile.mk index c1fc0c45271..bbaa5d9c74b 100644 --- a/src/security/intel/txt/Makefile.mk +++ b/src/security/intel/txt/Makefile.mk @@ -17,11 +17,21 @@ ramstage-y += getsec.c ramstage-y += getsec_enteraccs.S ramstage-y += ramstage.c +ifneq ($(CONFIG_INTEL_TXT_BIOSACM_FILE),"") cbfs-files-y += $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM)-file := $(CONFIG_INTEL_TXT_BIOSACM_FILE) $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM)-type := raw $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM)-align := $(CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT) +ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) +$(call add_intermediate, add_acm_fit, $(IFITTOOL) set_fit_ptr) + $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ + -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< + +endif # CPU_INTEL_FIRMWARE_INTERFACE_TABLE + +endif # INTEL_TXT_BIOSACM_FILE + ifneq ($(CONFIG_INTEL_TXT_SINITACM_FILE),"") cbfs-files-y += $(CONFIG_INTEL_TXT_CBFS_SINIT_ACM) $(CONFIG_INTEL_TXT_CBFS_SINIT_ACM)-file := $(CONFIG_INTEL_TXT_SINITACM_FILE) @@ -32,10 +42,6 @@ endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -$(call add_intermediate, add_acm_fit, $(IFITTOOL) set_fit_ptr) - $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ - -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< - # CBnT does not use FIT for IBB ifneq ($(CONFIG_INTEL_CBNT_SUPPORT),y) # Initial BootBlock files diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 6fba95850a8..76c36b26ea4 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -11,6 +11,7 @@ #include #include #include +#include #if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) #include @@ -82,12 +83,13 @@ int intel_txt_log_acm_error(const uint32_t acm_error) >> ACMERROR_TXT_PROGRESS_SHIFT; if (!minor) { - if (class == 0 && major == 0 && progress > 0) { + if (class == 0 && major == 0 && minor == 0) { printk(BIOS_ERR, " Execution successful\n"); printk(BIOS_ERR, " Progress code 0x%x\n", progress); } else { printk(BIOS_ERR, " Error Class: %x\n", class); - printk(BIOS_ERR, " Error: %x.%x\n", major, progress); + printk(BIOS_ERR, " Error: %x.%x\n", major, minor); + printk(BIOS_ERR, " Progress code 0x%x\n", progress); } } else { printk(BIOS_ERR, " ACM didn't start\n"); @@ -138,8 +140,13 @@ bool intel_txt_memory_has_secrets(void) if (!CONFIG(INTEL_TXT)) return false; - ret = (read8p(TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || - (read64p(TXT_E2STS) & TXT_E2STS_SECRET_STS); + if (!(cpuid_ecx(1) & CPUID_SMX)) { + printk(BIOS_CRIT, "TXT-STS: assuming no secrets as CPU doesn't support SMX\n"); + ret = false; + } else { + ret = (read8p(TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || + (read64p(TXT_E2STS) & TXT_E2STS_SECRET_STS); + } if (ret) printk(BIOS_CRIT, "TXT-STS: Secrets in memory!\n"); @@ -214,7 +221,7 @@ static int validate_acm(const void *ptr) struct acm_info_table *info = find_info_table(ptr); if (!info) return ACM_E_NO_INFO_TABLE; - if (info->chipset_acm_type != BIOS) + if (info->chipset_acm_type != BIOS_ACM) return ACM_E_NOT_BIOS_ACM; static const u8 acm_uuid[] = { @@ -359,19 +366,20 @@ int intel_txt_run_bios_acm(const u8 input_params) if (!acm_data) return -1; + printk(BIOS_INFO, "TEE-TXT: Running GETSEC[ENTERACCS] with input %d\n", input_params); /* Call into assembly which invokes the referenced ACM */ getsec_enteraccs(input_params, (uintptr_t)acm_data, acm_len); cbfs_unmap(acm_data); - const uint64_t acm_status = read64p(TXT_SPAD); - if (acm_status & ACMERROR_TXT_VALID) { + const uint64_t acm_error = read64p(TXT_BIOSACM_ERRORCODE); + if (acm_error & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "TEE-TXT: FATAL ACM launch error !\n"); /* * WARNING ! * To clear TXT.BIOSACM.ERRORCODE you must issue a cold reboot! */ - intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(acm_error); return -1; } @@ -385,6 +393,92 @@ static bool check_precondition(const int cond) return !cond; } +#if CONFIG(TPM2) +#define TXT_TPM2_AUX_INDEX (0x1c10102 - NV_INDEX_FIRST) +#define TXT_TPM2_PS_INDEX (0x1c10103 - NV_INDEX_FIRST) + +static const TPMA_NV txt_tpm2_aux_index_attributes = { + .TPMA_NV_POLICYWRITE = 1, + .TPMA_NV_POLICY_DELETE = 1, + .TPMA_NV_WRITE_STCLEAR = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_NO_DA = 1, + .TPMA_NV_PLATFORMCREATE = 1, +}; + +static const uint8_t txt_tpm2_aux_index_policy[VB2_SHA256_DIGEST_SIZE] = { + 0xef, 0x9a, 0x26, 0xfc, 0x22, 0xd1, 0xae, 0x8c, 0xec, 0xff, 0x59, 0xe9, + 0x48, 0x1a, 0xc1, 0xec, 0x53, 0x3d, 0xbe, 0x22, 0x8b, 0xec, 0x6d, 0x17, + 0x93, 0x0f, 0x4c, 0xb2, 0xcc, 0x5b, 0x97, 0x24 +}; + +static const TPMA_NV txt_tpm2_ps_index_attributes = { + .TPMA_NV_POLICYWRITE = 1, + .TPMA_NV_POLICY_DELETE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_NO_DA = 1, + .TPMA_NV_PLATFORMCREATE = 1, +}; + +/* Returns true if TPM indices are not in good condition. */ +static bool check_tpm2_indices(void) +{ + struct nv_read_public_response nvrp_resp; + + if (tlcl2_nv_read_public(TXT_TPM2_AUX_INDEX, &nvrp_resp) != TPM_SUCCESS) { + printk(BIOS_ERR, "TEE-TXT: Failed to read public data of TPM2 AUX index\n"); + return true; + } + + /* The index could have been written already, but we don't care. */ + nvrp_resp.nvPublic.t.nvPublic.attributes.TPMA_NV_WRITTEN = 0; + + if (memcmp(&nvrp_resp.nvPublic.t.nvPublic.attributes, &txt_tpm2_aux_index_attributes, + sizeof(TPMA_NV))) { + printk(BIOS_ERR, "TEE-TXT: Incorrect TPM2 AUX index attributes\n"); + return true; + } + + /* FIXME: Support other algorithms */ + if (nvrp_resp.nvPublic.t.nvPublic.nameAlg != TPM_ALG_SHA256) { + printk(BIOS_ERR, "TEE-TXT: Unsupported TPM2 AUX index auth hash algo (%02x)\n", + nvrp_resp.nvPublic.t.nvPublic.nameAlg); + return true; + } + + if (memcmp(nvrp_resp.nvPublic.t.nvPublic.authPolicy.t.buffer, + &txt_tpm2_aux_index_policy, + nvrp_resp.nvPublic.t.nvPublic.authPolicy.t.size)) { + printk(BIOS_ERR, "TEE-TXT: Incorrect TPM2 AUX index policy\n"); + return true; + } + + /* CBnT does not need PS/PO index */ + if (CONFIG(INTEL_CBNT_SUPPORT)) + return false; + + if (tlcl2_nv_read_public(TXT_TPM2_PS_INDEX, &nvrp_resp) != TPM_SUCCESS) { + printk(BIOS_ERR, "TEE-TXT: Failed to read public data of TPM2 PS/PO index\n"); + return true; + } + + /* The index could have been written already, but we don't care. */ + nvrp_resp.nvPublic.t.nvPublic.attributes.TPMA_NV_WRITTEN = 0; + + if (memcmp(&nvrp_resp.nvPublic.t.nvPublic.attributes, &txt_tpm2_ps_index_attributes, + sizeof(TPMA_NV))) { + printk(BIOS_ERR, "TEE-TXT: Incorrect TPM2 PS/PO index attributes\n"); + return true; + } + + /* + * We don't check the policy, as it may be any policy the platform + * owner/supplier sets. + */ + return false; +} +#endif + /* * Test all bits that are required for Intel TXT. * Enable SMX if available. @@ -514,7 +608,16 @@ bool intel_txt_prepare_txt_env(void) break; } } - +#if CONFIG(TPM2) + if (tlcl_get_family() == TPM_2) { + /* + * We can't do SCHECK without the mandatory TPM indices present, + * otherwise we will end up in reset loop + */ + if (check_tpm2_indices()) + return true; + } +#endif /* Need to park all APs. */ if (CONFIG(PARALLEL_MP_AP_WORK)) mp_park_aps(); diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index ff9db05f060..4127277156b 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include +#include + #include "getsec_mtrr_setup.inc" .macro PUSH_MSR x @@ -109,6 +112,22 @@ cond_push_var_mtrrs: orl $(CR0_CD | CR0_NW), %eax movl %eax, %cr0 + /* Check how the cache should be invalidated */ + movl 8(%ebp), %eax /* ACM function in eax */ + cmp $(ACMINPUT_SCLEAN), %eax + je invalidate_cache + cmp $(ACMINPUT_CLEAR_SECRETS), %eax + je invalidate_cache + cmp $(ACMINPUT_ACHECK), %eax + je invalidate_cache + + wbinvd /* writeback is necessary */ + jmp disable_mtrrs + +invalidate_cache: + invd + +disable_mtrrs: /* Disable all MTRRs */ movl $(MTRR_DEF_TYPE_MSR), %ecx xorl %eax, %eax @@ -211,11 +230,30 @@ cond_clear_var_mtrrs: orl $(CR0_NE), %eax movl %eax, %cr0 - /* Enable SMX and FXSTORE - for getsec */ + /* Enable SMX and FXSTORE - for getsec; make accesses of DR4/DR5 cause #UD (invalid opcode) */ movl %cr4, %eax - orl $(CR4_SMXE | CR4_OSFXSR), %eax + orl $(CR4_SMXE | CR4_DE | CR4_OSFXSR), %eax movl %eax, %cr4 +#if CONFIG(INTEL_CBNT_SUPPORT) + /* Clean all MCi_STATUS MSR registers */ + movl $(IA32_MCG_CAP), %ecx + rdmsr + movzx %al, %ebx /* ebx = MCR bank count */ + xorl %eax, %eax /* Write 0 into all MCi_STATUS registers */ + xorl %edx, %edx + movl $(IA32_MC0_STATUS), %ecx + +mca_clean_loop: + wrmsr + dec %ebx + jz mca_clean_done + addl $4, %ecx /* ecx = number of MSRs per bank */ + jmp mca_clean_loop + +mca_clean_done: +#endif + /* * Save GDT * Chapter A.1.2 @@ -269,6 +307,15 @@ cond_clear_var_mtrrs: movd %xmm2, %eax movl %eax, %gs + /* Check if we need a reset */ + movl 8(%ebp), %eax /* ACM function in eax */ + cmp $(ACMINPUT_SCLEAN), %eax + je reset_system + cmp $(ACMINPUT_CLEAR_SECRETS), %eax + je reset_system + cmp $(ACMINPUT_ACHECK), %eax + je reset_system + /* Disable cache */ movl %cr0, %eax orl $(CR0_CD | CR0_NW), %eax @@ -334,3 +381,17 @@ cond_pop_var_mtrrs: popl %ebp ret + +reset_system: + movw $0xcf9, %dx + movb $0, %al + outb %al, %dx + + movw $0xcf9, %dx + movb $0x0e, %al /* FULL_RST | RST_CPU | SYS_RST */ + outb %al, %dx + + cli +.halt_forever: + hlt + jmp .halt_forever diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index e1692cf283c..c5a1f706193 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -110,10 +110,12 @@ void txt_dump_acm_info(const struct acm_header_v0 *acm_header) if (acm_header->module_type == CHIPSET_ACM) printk(BIOS_INFO, " Type: Chipset ACM\n"); - if (acm_header->module_sub_type == 0) - printk(BIOS_INFO, " Subtype: undefined\n"); - else if (acm_header->module_sub_type == 1) - printk(BIOS_INFO, " Subtype: Run at reset\n"); + if (acm_header->module_sub_type == BIOS_ACM) + printk(BIOS_INFO, " Subtype: BIOS/SINIT\n"); + else if (acm_header->module_sub_type == STARTUP_ACM) + printk(BIOS_INFO, " Subtype: STARTUP\n"); + else if (acm_header->module_sub_type == BOOTGUARD_ACM) + printk(BIOS_INFO, " Subtype: BOOTGUARD\n"); printk(BIOS_INFO, " Header: v%u.%u\n", acm_header->header_version[0], acm_header->header_version[1]); diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 5c03da909a9..084e567eaac 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -6,7 +6,10 @@ #include #include #include +#include +#include #include +#include #include #include #include @@ -89,6 +92,7 @@ static void check_secrets_txt(void *unused) if (status & ACMSTS_TXT_DISABLED) return; + printk(BIOS_INFO, "TEE-TXT: Checking for secrets in memory...\n"); /* * Check if secrets bit needs to be reset. Only platforms that support * CONFIG(PLATFORM_HAS_DRAM_CLEAR) will be able to run this code. @@ -98,12 +102,25 @@ static void check_secrets_txt(void *unused) * TXT will issue a platform reset to come up sober. */ if (intel_txt_memory_has_secrets()) { + if (intel_txt_prepare_txt_env()) { + printk(BIOS_ERR, "TEE-TXT: Failed to prepare TXT environment\n"); + return; + } + + /* Check for fatal ACM error and TXT reset */ + if (get_wake_error_status()) { + /* Can't run ACMs with TXT_ESTS_WAKE_ERROR_STS set */ + printk(BIOS_ERR, "TEE-TXT: Fatal BIOS ACM error reported\n"); + return; + } printk(BIOS_INFO, "TEE-TXT: Wiping TEE...\n"); intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS); /* Should never reach this point ... */ intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); die("Waiting for platform reset...\n"); + } else { + printk(BIOS_INFO, "TEE-TXT: No secrets in memory\n"); } } @@ -164,6 +181,7 @@ static void init_intel_txt(void *unused) if (intel_txt_run_bios_acm(ACMINPUT_NOP) < 0) { printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM with NOP function.\n"); + restart_aps(); return; } } @@ -179,7 +197,12 @@ static void init_intel_txt(void *unused) if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) { printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM.\n"); return; + } else { + restart_aps(); } + } else { + /* Let coreboot sync MTRRs on APs */ + restart_aps(); } } @@ -199,6 +222,13 @@ static void push_sinit_heap(u8 **heap_ptr, void *data, size_t data_length) } } +static bool is_txt_server_capable(void) +{ + msr_t msr = rdmsr(MSR_BOOT_GUARD_SACM_INFO); + + return !!(msr.raw & B_BOOT_GUARD_SACM_INFO_TXT_CAPABILITY); +} + static void txt_heap_fill_common_bdr(struct txt_biosdataregion *bdr) { /* TPM2.0 requires version 6 of BDT */ @@ -219,7 +249,19 @@ static void txt_heap_fill_common_bdr(struct txt_biosdataregion *bdr) } bdr->support_acpi_ppi = 0; - bdr->platform_type = 0; + + if (CONFIG(INTEL_CBNT_SUPPORT)) { + if (is_txt_server_capable()) { + /* Server TXT - server SINIT is required */ + bdr->platform_type = 2; + } else { + /* Client TXT - client SINIT is required */ + bdr->platform_type = 1; + } + } else { + /* Legacy / auto - auto-detect based on platform segment */ + bdr->platform_type = 0; + } } static void txt_heap_fill_bios_spec(struct txt_bios_spec_ver_element *spec) @@ -384,16 +426,36 @@ static void lockdown_intel_txt(void *unused) if (!getsec_parameter(NULL, NULL, NULL, NULL, NULL, &txt_feature_flags)) return; - /* LockConfig only exists on Intel TXT for Servers */ - if (txt_feature_flags & GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT) { + /* LockConfig only exists on Intel TXT for Servers and CBnT */ + if ((txt_feature_flags & GETSEC_PARAMS_TXT_EXT_CRTM_SUPPORT) || + CONFIG(INTEL_CBNT_SUPPORT)) { + /* + * We have to ensure the TXT environment is prepared to run ACM. + * We may have restarted the APs to program MTRRs, etc. + */ + if (intel_txt_prepare_txt_env()) { + printk(BIOS_ERR, "TEE-TXT: Failed to prepare TXT environment\n"); + return; + } + + /* Check for fatal ACM error and TXT reset */ + if (get_wake_error_status()) { + /* Can't run ACMs with TXT_ESTS_WAKE_ERROR_STS set */ + printk(BIOS_ERR, "TEE-TXT: Fatal BIOS ACM error reported\n"); + restart_aps(); + return; + } + printk(BIOS_INFO, "TEE-TXT: Locking TEE...\n"); /* Lock TXT config, unlocks TXT_HEAP_BASE */ if (intel_txt_run_bios_acm(ACMINPUT_LOCK_CONFIG) < 0) { printk(BIOS_ERR, "TEE-TXT: Failed to lock registers.\n"); printk(BIOS_ERR, "TEE-TXT: SINIT won't be supported.\n"); + restart_aps(); return; } + restart_aps(); } /* diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index 643e7a90eba..74b8d76340a 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -1,11 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include +#if CONFIG(SOC_INTEL_COMMON_BLOCK_PMC) +#include +#endif +#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_PMBASE) #include +#include +#endif +#include #include #include "txt.h" @@ -82,8 +91,12 @@ void intel_txt_romstage_init(void) } /* FIXME: Clear SLP_TYP# */ - write_pmbase32(4, read_pmbase32(4) & ~(0x7 << 10)); - +#if CONFIG(SOC_INTEL_COMMON_BLOCK_PMC) + pmc_disable_pm1_control(SLP_TYP); +#endif +#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_PMBASE) + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) & ~SLP_TYP); +#endif intel_txt_run_sclean(); /* If running the BIOS ACM is impossible, manual intervention is required */ diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index a00084511fa..20f5121bb07 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -3,8 +3,6 @@ #ifndef SECURITY_INTEL_TXT_REGISTER_H_ #define SECURITY_INTEL_TXT_REGISTER_H_ -#include - /* * Document: 315168-016 * Intel Trusted Execution Technology (Intel TXT) @@ -23,8 +21,11 @@ #define TXT_ESTS_WAKE_ERROR_STS (1 << 6) #define TXT_ERROR (TXT_BASE + 0x30) -#define ACMERROR_TXT_VALID (1ul << 31) -#define ACMERROR_TXT_EXTERNAL (1ul << 30) +#define ACMERROR_TXT_VALID (1ul << 31) +#define ACMERROR_TXT_EXTERNAL (1ul << 30) +#define ACMERROR_SOURCE_MASK (1ul << 15) +#define ACMERROR_SOURCE_ACM (0ul << 15) +#define ACMERROR_SOURCE_MLE (1ul << 15) #define ACMERROR_TXT_PROGRESS_SHIFT 16 #define ACMERROR_TXT_MINOR_SHIFT 15 @@ -32,8 +33,8 @@ #define ACMERROR_TXT_CLASS_SHIFT 4 #define ACMERROR_TXT_TYPE_SHIFT 0 -#define ACMERROR_TXT_PROGRESS_CODE (0xffull << ACMERROR_TXT_PROGRESS_SHIFT) -#define ACMERROR_TXT_MINOR_CODE (0x01ull << ACMERROR_TXT_MINOR_SHIFT) +#define ACMERROR_TXT_PROGRESS_CODE (0x1ffull << ACMERROR_TXT_PROGRESS_SHIFT) +#define ACMERROR_TXT_MINOR_CODE (0xfffull << ACMERROR_TXT_MINOR_SHIFT) #define ACMERROR_TXT_MAJOR_CODE (0x1full << ACMERROR_TXT_MAJOR_SHIFT) #define ACMERROR_TXT_CLASS_CODE (0x3full << ACMERROR_TXT_CLASS_SHIFT) #define ACMERROR_TXT_TYPE_CODE (0x0full << ACMERROR_TXT_TYPE_SHIFT) @@ -54,6 +55,7 @@ #define ACMSTS_TXT_DISABLED (1ull << 60) /* disabled by FIT type 0xA record */ #define ACMSTS_BIOS_TRUSTED (1ull << 59) #define ACMSTS_MEM_CLEAR_POWER_DOWN (1ull << 47) +#define ACMSTS_BTG_STARTUP_SUCCESS (1ull << 31) #define ACMSTS_TXT_STARTUP_SUCCESS (1ull << 30) #define TXT_VER_FSBIF (TXT_BASE + 0x100) @@ -127,12 +129,13 @@ /* ESI flags for GETSEC[ENTERACCS] see Reference Number: 323372-017 */ #define ACMINPUT_SCLEAN 0 +#define ACMINPUT_RESET_TPM_ESTABLISHMENT 1 #define ACMINPUT_RESET_TPM_AUXILIARY_INDICIES 2 #define ACMINPUT_NOP 3 #define ACMINPUT_SCHECK 4 #define ACMINPUT_CLEAR_SECRETS 5 #define ACMINPUT_LOCK_CONFIG 6 - +#define ACMINPUT_ACHECK 7 /* * GetSec EAX value. * SAFER MODE EXTENSIONS REFERENCE. @@ -165,6 +168,10 @@ /* MSRs */ #define IA32_MCG_STATUS 0x17a +#ifndef __ASSEMBLER__ + +#include + /* DPR register layout, either in PCI config space or TXT MMIO space */ union dpr_register { struct { @@ -184,8 +191,9 @@ typedef enum { } acm_module_type; typedef enum { - BIOS = 0, - SINIT = 1, + BIOS_ACM = 0, + STARTUP_ACM = 1, + BOOTGUARD_ACM = 3, } acm_module_sub_type; /* @@ -221,6 +229,40 @@ struct __packed acm_header_v0 { uint8_t user_area[]; }; +/* + * ACM Header v3.0 without dynamic part + * Chapter A.1.1 + * Intel TXT Software Development Guide (Document: 315168-017.4) + * + * This version adds support for CBnT. + */ +struct __packed acm_header_v3 { + uint16_t module_type; + uint16_t module_sub_type; + uint32_t header_len; + uint16_t header_version[2]; + uint16_t chipset_id; + uint16_t flags; + uint32_t module_vendor; + uint32_t date; + uint32_t size; + uint16_t txt_svn; + uint16_t se_svn; + uint32_t code_control; + uint32_t error_entry_point; + uint32_t gdt_limit; + uint32_t gdt_ptr; + uint32_t seg_sel; + uint32_t entry_point; + uint8_t reserved2[64]; + uint32_t key_size; + uint32_t scratch_size; + uint8_t rsa3072_pubkey[384]; + uint8_t rsa3072_sig[384]; + uint32_t scratch[208]; + uint8_t user_area[]; +}; + struct __packed acm_info_table { uint8_t uuid[16]; uint8_t chipset_acm_type; @@ -298,4 +340,6 @@ void txt_dump_chipset_info(void); void txt_dump_acm_info(const struct acm_header_v0 *acm_header); void txt_dump_getsec_parameters(void); +#endif /*__ASSEMBLER__*/ + #endif /* SECURITY_INTEL_TXT_REGISTER_H_ */ diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index 8de7979904e..fac338017e4 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -62,7 +62,6 @@ config BOOTMEDIA_LOCK_WHOLE_NO_ACCESS config BOOTMEDIA_LOCK_WPRO_VBOOT_RO bool "Write-protect WP_RO FMAP region in boot medium" - depends on VBOOT help Select this if you want to write-protect the WP_RO region as specified in the VBOOT FMAP. You will be able to write every region outside @@ -76,7 +75,7 @@ config BOOTMEDIA_LOCK_WPRO_VBOOT_RO endchoice config BOOTMEDIA_LOCK_IN_VERSTAGE - depends on BOOTMEDIA_LOCK_WPRO_VBOOT_RO + depends on VBOOT bool "Lock boot media down in verstage" help Select this if you want to write-protect the WP_RO region as soon as diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c index c2e2ac35019..233968e955e 100644 --- a/src/security/lockdown/lockdown.c +++ b/src/security/lockdown/lockdown.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -15,6 +16,11 @@ void boot_device_security_lockdown(void) struct region_device dev; enum bootdev_prot_type lock_type; + if (!is_vboot_locking_permitted()) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Skipping enabling boot media protection\n"); + return; + } + printk(BIOS_DEBUG, "BM-LOCKDOWN: Enabling boot media protection scheme "); if (CONFIG(BOOTMEDIA_LOCK_CONTROLLER)) { diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index e747f4f3ce3..a7ffd13e9ad 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -62,7 +62,9 @@ static void clear_memory(void *unused) return; /* Process capsules before clearing memory and only if not waking up from S3. */ - efi_parse_capsules(); + uintptr_t capsules_base; + size_t capsules_size; + efi_parse_capsules(&capsules_base, &capsules_size); if (!security_clear_dram_request()) return; @@ -81,7 +83,9 @@ static void clear_memory(void *unused) void *baseptr; size_t size; - /* Only skip CBMEM, stage program, stack and heap are included there. */ + /* Only skip capsules and CBMEM. The latter includes stage program, stack and heap. */ + + memranges_insert(&mem, capsules_base, capsules_size, BM_MEM_RESERVED); if (cbmem_get_region(&baseptr, &size)) die("Could not find cbmem region"); diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 377d6dcb887..3ffbb8a8337 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -81,6 +81,7 @@ config TPM_MEASURED_BOOT choice prompt "TPM event log format" depends on TPM_MEASURED_BOOT + default TPM_LOG_TCG if TPM1 && TPM2 default TPM_LOG_TPM1 if TPM1 default TPM_LOG_TPM2 if TPM2 @@ -88,6 +89,10 @@ config TPM_LOG_CB bool "coreboot's custom format" help Custom coreboot-specific format of the log derived from TPM1 log format. +config TPM_LOG_TCG + bool "TPM 1.2 or TPM 2.0 format (matches detected TPM)" + help + Automatically select TCG log format depending on which TPM is present. config TPM_LOG_TPM1 bool "TPM 1.2 format" depends on TPM1 && !TPM2 @@ -105,7 +110,7 @@ endchoice choice prompt "TPM2 hashing algorithm" - depends on TPM_MEASURED_BOOT && TPM_LOG_TPM2 + depends on TPM_MEASURED_BOOT && (TPM_LOG_TCG || TPM_LOG_TPM2) default TPM_HASH_SHA1 if TPM1 default TPM_HASH_SHA256 if TPM2 @@ -122,7 +127,7 @@ endchoice config TPM_MEASURED_BOOT_INIT_BOOTBLOCK bool - depends on TPM_MEASURED_BOOT && !VBOOT + depends on TPM_MEASURED_BOOT help Initialize TPM inside the bootblock instead of ramstage. This is useful with some form of hardware assisted root of trust diff --git a/src/security/tpm/Makefile.mk b/src/security/tpm/Makefile.mk index fe16192ff67..ebecb32974a 100644 --- a/src/security/tpm/Makefile.mk +++ b/src/security/tpm/Makefile.mk @@ -70,16 +70,24 @@ verstage-$(CONFIG_TPM_LOG_CB) += tspi/log.c postcar-$(CONFIG_TPM_LOG_CB) += tspi/log.c bootblock-$(CONFIG_TPM_LOG_CB) += tspi/log.c -ramstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c -romstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c -verstage-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c -postcar-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c -bootblock-$(CONFIG_TPM_LOG_TPM1) += tspi/log-tpm1.c - -ramstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c -romstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c -verstage-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c -postcar-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c -bootblock-$(CONFIG_TPM_LOG_TPM2) += tspi/log-tpm2.c +ifeq ($(CONFIG_TPM_LOG_TCG)$(CONFIG_TPM_LOG_TPM1),y) + +ramstage-y += tspi/log-tpm1.c +romstage-y += tspi/log-tpm1.c +verstage-y += tspi/log-tpm1.c +postcar-y += tspi/log-tpm1.c +bootblock-y += tspi/log-tpm1.c + +endif # CONFIG_TPM_LOG_TCG or CONFIG_TPM_LOG_TPM1 + +ifeq ($(CONFIG_TPM_LOG_TCG)$(CONFIG_TPM_LOG_TPM2),y) + +ramstage-y += tspi/log-tpm2.c +romstage-y += tspi/log-tpm2.c +verstage-y += tspi/log-tpm2.c +postcar-y += tspi/log-tpm2.c +bootblock-y += tspi/log-tpm2.c + +endif # CONFIG_TPM_LOG_TCG or CONFIG_TPM_LOG_TPM2 endif # CONFIG_TPM_MEASURED_BOOT diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index 67ba911e03f..3555ef61a4b 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -53,18 +53,6 @@ enum tpm_family { typedef tpm_result_t (*tis_sendrecv_fn)(const u8 *sendbuf, size_t send_size, u8 *recvbuf, size_t *recv_len); -/* - * Probe for the TPM device and set it up for use within locality 0. - * - * @family - pointer which is set to TPM family of the device - * - * Returns pointer to send-receive function on success or NULL on failure. - * - * Do not call this explicitly, it's meant to be used exclusively by TSS - * implementation (tlcl_lib_init() function to be specific). - */ -typedef tis_sendrecv_fn (*tis_probe_fn)(enum tpm_family *family); - /* * tis_vendor_write() * diff --git a/src/security/tpm/tpm2_log_serialized.h b/src/security/tpm/tpm2_log_serialized.h index a11a2f6a7e5..aaaf576eca3 100644 --- a/src/security/tpm/tpm2_log_serialized.h +++ b/src/security/tpm/tpm2_log_serialized.h @@ -17,7 +17,7 @@ * varying number of digests and their sizes. However, it works as long as * we're only using single kind of digests. */ -#if CONFIG(TPM_LOG_TPM2) +#if CONFIG(TPM_LOG_TCG) || CONFIG(TPM_LOG_TPM2) # if CONFIG(TPM_HASH_SHA1) # define TPM_20_LOG_DIGEST_MAX_LENGTH SHA1_DIGEST_SIZE # endif diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index 3e7e5f10f56..f79b2cf043e 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -13,10 +13,60 @@ #define TPM_PCR_MAX_LEN 64 #define HASH_DATA_CHUNK_SIZE 1024 -#define MAX_TPM_LOG_ENTRIES 50 /* Assumption of 2K TCPA log size reserved for CAR/SRAM */ #define MAX_PRERAM_TPM_LOG_ENTRIES 15 +/** + * Checks whether TCG TPM1.2 log format should be used. + * When required, initializes TPM if it wasn't yet initialized. + */ +static inline bool tpm_log_use_tpm1_format(void) +{ + if (CONFIG(TPM_LOG_TPM1)) + return true; + if (CONFIG(TPM_LOG_TCG)) + return tlcl_lib_init() == TPM_SUCCESS && tlcl_get_family() == TPM_1; + return false; +} + +/** + * Checks whether TCG TPM2.0 log format should be used. + * When required, initializes TPM if it wasn't yet initialized. + */ +static inline bool tpm_log_use_tpm2_format(void) +{ + if (CONFIG(TPM_LOG_TPM2)) + return true; + if (CONFIG(TPM_LOG_TCG)) + return tlcl_lib_init() == TPM_SUCCESS && tlcl_get_family() == TPM_2; + return false; +} + +/** + * Retrieves hash algorithm used by TPM event log or VB2_HASH_INVALID. + */ +static inline enum vb2_hash_algorithm tpm_log_alg(void) +{ + if (CONFIG(TPM_LOG_CB)) + return (tlcl_get_family() == TPM_1 ? VB2_HASH_SHA1 : VB2_HASH_SHA256); + + if (tpm_log_use_tpm1_format()) + return VB2_HASH_SHA1; + + if (tpm_log_use_tpm2_format()) { + if (CONFIG(TPM_HASH_SHA1)) + return VB2_HASH_SHA1; + if (CONFIG(TPM_HASH_SHA256)) + return VB2_HASH_SHA256; + if (CONFIG(TPM_HASH_SHA384)) + return VB2_HASH_SHA384; + if (CONFIG(TPM_HASH_SHA512)) + return VB2_HASH_SHA512; + } + + return VB2_HASH_INVALID; +} + /** * Get the pointer to the single instance of global * TPM log data, and initialize it when necessary @@ -31,9 +81,9 @@ static inline void *tpm_log_cbmem_init(void) { if (CONFIG(TPM_LOG_CB)) return tpm_cb_log_cbmem_init(); - if (CONFIG(TPM_LOG_TPM1)) + if (tpm_log_use_tpm1_format()) return tpm1_log_cbmem_init(); - if (CONFIG(TPM_LOG_TPM2)) + if (tpm_log_use_tpm2_format()) return tpm2_log_cbmem_init(); return NULL; } @@ -46,9 +96,9 @@ static inline void tpm_preram_log_clear(void) { if (CONFIG(TPM_LOG_CB)) tpm_cb_preram_log_clear(); - else if (CONFIG(TPM_LOG_TPM1)) + else if (tpm_log_use_tpm1_format()) tpm1_preram_log_clear(); - else if (CONFIG(TPM_LOG_TPM2)) + else if (tpm_log_use_tpm2_format()) tpm2_preram_log_clear(); } @@ -59,9 +109,9 @@ static inline uint16_t tpm_log_get_size(const void *log_table) { if (CONFIG(TPM_LOG_CB)) return tpm_cb_log_get_size(log_table); - if (CONFIG(TPM_LOG_TPM1)) + if (tpm_log_use_tpm1_format()) return tpm1_log_get_size(log_table); - if (CONFIG(TPM_LOG_TPM2)) + if (tpm_log_use_tpm2_format()) return tpm2_log_get_size(log_table); return 0; } @@ -73,9 +123,9 @@ static inline void tpm_log_copy_entries(const void *from, void *to) { if (CONFIG(TPM_LOG_CB)) tpm_cb_log_copy_entries(from, to); - else if (CONFIG(TPM_LOG_TPM1)) + else if (tpm_log_use_tpm1_format()) tpm1_log_copy_entries(from, to); - else if (CONFIG(TPM_LOG_TPM2)) + else if (tpm_log_use_tpm2_format()) tpm2_log_copy_entries(from, to); } @@ -87,9 +137,9 @@ static inline int tpm_log_get(int entry_idx, int *pcr, const uint8_t **digest_da { if (CONFIG(TPM_LOG_CB)) return tpm_cb_log_get(entry_idx, pcr, digest_data, digest_algo, event_name); - if (CONFIG(TPM_LOG_TPM1)) + if (tpm_log_use_tpm1_format()) return tpm1_log_get(entry_idx, pcr, digest_data, digest_algo, event_name); - if (CONFIG(TPM_LOG_TPM2)) + if (tpm_log_use_tpm2_format()) return tpm2_log_get(entry_idx, pcr, digest_data, digest_algo, event_name); return 1; } @@ -109,12 +159,22 @@ static inline void tpm_log_add_table_entry(const char *name, const uint32_t pcr, { if (CONFIG(TPM_LOG_CB)) tpm_cb_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); - else if (CONFIG(TPM_LOG_TPM1)) + else if (tpm_log_use_tpm1_format()) tpm1_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); - else if (CONFIG(TPM_LOG_TPM2)) + else if (tpm_log_use_tpm2_format()) tpm2_log_add_table_entry(name, pcr, digest_algo, digest, digest_len); } +/** + * Record startup locality in the event log. + */ +static inline void tpm_log_startup_locality(int locality) +{ + /* Locality 0 is the default and doesn't need to be logged. */ + if (locality != 0 && tpm_log_use_tpm2_format()) + tpm2_log_startup_locality(locality); +} + /** * Dump TPM log entries on console */ @@ -122,9 +182,9 @@ static inline void tpm_log_dump(void *unused) { if (CONFIG(TPM_LOG_CB)) tpm_cb_log_dump(); - else if (CONFIG(TPM_LOG_TPM1)) + else if (tpm_log_use_tpm1_format()) tpm1_log_dump(); - else if (CONFIG(TPM_LOG_TPM2)) + else if (tpm_log_use_tpm2_format()) tpm2_log_dump(); } diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index 4e0a9b727ae..c870a90198e 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -8,37 +8,22 @@ #include "crtm.h" #include #include +#include static int tpm_log_initialized; -static inline int tpm_log_available(void) +bool tspi_tpm_log_available(void) { if (ENV_BOOTBLOCK) - return tpm_log_initialized; + return tpm_log_initialized != 0; - return 1; + return true; } -/* - * Initializes the Core Root of Trust for Measurements - * in coreboot. The initial code in a chain of trust must measure - * itself. - * - * Summary: - * + Measures the FMAP FMAP partition. - * + Measures bootblock in CBFS or BOOTBLOCK FMAP partition. - * + If vboot starts in romstage, it measures the romstage - * in CBFS. - * + Measure the verstage if it is compiled as separate - * stage. - * - * Takes the current vboot context as parameter for s3 checks. - * returns on success TPM_SUCCESS, else a TPM error. - */ -static tpm_result_t tspi_init_crtm(void) +tpm_result_t tspi_init_crtm(void) { tpm_result_t rc = TPM_SUCCESS; /* Initialize TPM PRERAM log. */ - if (!tpm_log_available()) { + if (!tspi_tpm_log_available()) { tpm_preram_log_clear(); tpm_log_initialized = 1; } else { @@ -46,6 +31,14 @@ static tpm_result_t tspi_init_crtm(void) return TPM_SUCCESS; } + if (CONFIG(INTEL_CBNT_SUPPORT)) { + /* No need to create Startup Locality Event without CBnT as Locality 0 should be + in use in that case and reporting it is optional. */ + tpm_log_startup_locality(intel_cbnt_get_locality()); + + intel_cbnt_inject_ibg_measurements(); + } + struct region_device fmap; if (fmap_locate_area_as_rdev("FMAP", &fmap) == 0) { rc = tpm_measure_region(&fmap, CONFIG_PCR_SRTM, "FMAP: FMAP"); @@ -115,19 +108,8 @@ static bool is_runtime_data(const char *name) tpm_result_t tspi_cbfs_measurement(const char *name, uint32_t type, const struct vb2_hash *hash) { uint32_t pcr_index; - tpm_result_t rc = TPM_SUCCESS; char tpm_log_metadata[TPM_CB_LOG_PCR_HASH_NAME]; - if (!tpm_log_available()) { - rc = tspi_init_crtm(); - if (rc) { - printk(BIOS_WARNING, - "Initializing CRTM failed!\n"); - return rc; - } - printk(BIOS_DEBUG, "CRTM initialized.\n"); - } - switch (type) { case CBFS_TYPE_MRC_CACHE: pcr_index = CONFIG_PCR_RUNTIME_DATA; @@ -185,7 +167,7 @@ tpm_result_t tspi_measure_cache_to_pcr(void) enum vb2_hash_algorithm digest_algo; /* This means the table is empty. */ - if (!tpm_log_available()) + if (!tspi_tpm_log_available()) return TPM_SUCCESS; if (tpm_log_init() == NULL) { @@ -196,6 +178,20 @@ tpm_result_t tspi_measure_cache_to_pcr(void) printk(BIOS_DEBUG, "TPM: Write digests cached in TPM log to PCR\n"); i = 0; while (!tpm_log_get(i++, &pcr, &digest_data, &digest_algo, &event_name)) { + /* + * Skip log entries that coreboot synthesized to account for PCR extends + * performed by hardware S-CRTM. + * + * With CONFIG(INTEL_CBNT_SUPPORT) implying + * CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK) tpm_setup() (and thus + * tspi_measure_cache_to_pcr()) should be invoked before CBNT measurements are + * created, in fact we shouldn't even reach here because the log is likely + * empty, but it seems more robust to have the check here. + */ + if (CONFIG(INTEL_CBNT_SUPPORT) && + strcmp(event_name, CBNT_EVENT_LOG_MESSAGE) == 0) + continue; + printk(BIOS_DEBUG, "TPM: Write digest for %s into PCR %d\n", event_name, pcr); tpm_result_t rc = tlcl_extend(pcr, digest_data, digest_algo); if (rc != TPM_SUCCESS) { diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index 69043e233a2..cd20e81b646 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -9,32 +9,24 @@ #include #include -#if CONFIG(TPM_LOG_CB) -# define TPM_MEASURE_ALGO (tlcl_get_family() == TPM_1 ? VB2_HASH_SHA1 : VB2_HASH_SHA256) -#elif CONFIG(TPM_LOG_TPM1) -# define TPM_MEASURE_ALGO VB2_HASH_SHA1 -#elif CONFIG(TPM_LOG_TPM2) -# if CONFIG(TPM_HASH_SHA1) -# define TPM_MEASURE_ALGO VB2_HASH_SHA1 -# endif -# if CONFIG(TPM_HASH_SHA256) -# define TPM_MEASURE_ALGO VB2_HASH_SHA256 -# endif -# if CONFIG(TPM_HASH_SHA384) -# define TPM_MEASURE_ALGO VB2_HASH_SHA384 -# endif -# if CONFIG(TPM_HASH_SHA512) -# define TPM_MEASURE_ALGO VB2_HASH_SHA512 -# endif -#endif - -#if !defined(TPM_MEASURE_ALGO) -# if !CONFIG(TPM_MEASURED_BOOT) -# define TPM_MEASURE_ALGO VB2_HASH_INVALID -# else -# error "Misconfiguration: failed to determine TPM hashing algorithm" -# endif -#endif +/** + * Checks whether TPM log was already initialized. + */ +bool tspi_tpm_log_available(void); + +/** + * Initializes the Core Root of Trust for Measurements in coreboot. The initial code in a + * chain of trust must measure itself. + * + * Summary: + * - measures the FMAP FMAP partition + * - measures bootblock in CBFS or BOOTBLOCK FMAP partition + * - if vboot starts in romstage, it measures the romstage in CBFS + * - measures the verstage if it is compiled as a separate stage + * + * On success returns TPM_SUCCESS, otherwise returns a TPM error. + */ +tpm_result_t tspi_init_crtm(void); /** * Measure digests cached in TPM log entries into PCRs diff --git a/src/security/tpm/tspi/log-tpm1.c b/src/security/tpm/tspi/log-tpm1.c index 481b569cd55..0fbfa5ab503 100644 --- a/src/security/tpm/tspi/log-tpm1.c +++ b/src/security/tpm/tspi/log-tpm1.c @@ -14,6 +14,10 @@ #include #include +#define TPM_LOG_SIZE (64 * KiB) +#define MAX_TPM_LOG_ENTRIES ((TPM_LOG_SIZE - sizeof(struct tpm_1_log_table)) / \ + sizeof(struct tpm_1_log_entry)) + void *tpm1_log_cbmem_init(void) { static struct tpm_1_log_table *tclt; @@ -21,19 +25,17 @@ void *tpm1_log_cbmem_init(void) return tclt; if (ENV_HAS_CBMEM) { - size_t tpm_log_len; struct spec_id_event_data *hdr; tclt = cbmem_find(CBMEM_ID_TCPA_TCG_LOG); if (tclt) return tclt; - tpm_log_len = sizeof(*tclt) + MAX_TPM_LOG_ENTRIES * sizeof(tclt->entries[0]); - tclt = cbmem_add(CBMEM_ID_TCPA_TCG_LOG, tpm_log_len); + tclt = cbmem_add(CBMEM_ID_TCPA_TCG_LOG, TPM_LOG_SIZE); if (!tclt) return NULL; - memset(tclt, 0, sizeof(*tclt)); + memset(tclt, 0, TPM_LOG_SIZE); hdr = &tclt->spec_id; /* Fill in first "header" entry. */ diff --git a/src/security/tpm/tspi/log-tpm2.c b/src/security/tpm/tspi/log-tpm2.c index 56799a7e948..3e26970a880 100644 --- a/src/security/tpm/tspi/log-tpm2.c +++ b/src/security/tpm/tspi/log-tpm2.c @@ -22,22 +22,14 @@ #include #include -static uint16_t tpmalg_from_vb2_hash(enum vb2_hash_algorithm hash_type) -{ - switch (hash_type) { - case VB2_HASH_SHA1: - return TPM2_ALG_SHA1; - case VB2_HASH_SHA256: - return TPM2_ALG_SHA256; - case VB2_HASH_SHA384: - return TPM2_ALG_SHA384; - case VB2_HASH_SHA512: - return TPM2_ALG_SHA512; - - default: - return 0xFF; - } -} +#define TPM_LOG_SIZE (64 * KiB) +#define MAX_TPM_LOG_ENTRIES ((TPM_LOG_SIZE - sizeof(struct tpm_2_log_table)) / \ + sizeof(struct tpm_2_log_entry)) + +struct startup_locality_event { + char signature[16]; /* "StartupLocality" (NUL-terminated) */ + uint8_t startup_locality; /* 0 or 3 */ +} __packed; void *tpm2_log_cbmem_init(void) { @@ -46,20 +38,17 @@ void *tpm2_log_cbmem_init(void) return tclt; if (ENV_HAS_CBMEM) { - size_t tpm_log_len; struct tcg_efi_spec_id_event *hdr; tclt = cbmem_find(CBMEM_ID_TPM2_TCG_LOG); if (tclt) return tclt; - tpm_log_len = sizeof(struct tpm_2_log_table) + - MAX_TPM_LOG_ENTRIES * sizeof(struct tpm_2_log_entry); - tclt = cbmem_add(CBMEM_ID_TPM2_TCG_LOG, tpm_log_len); + tclt = cbmem_add(CBMEM_ID_TPM2_TCG_LOG, TPM_LOG_SIZE); if (!tclt) return NULL; - memset(tclt, 0, tpm_log_len); + memset(tclt, 0, TPM_LOG_SIZE); hdr = &tclt->header; hdr->event_type = htole32(EV_NO_ACTION); @@ -71,8 +60,8 @@ void *tpm2_log_cbmem_init(void) hdr->spec_errata = 0x00; hdr->uintn_size = 0x02; // 64-bit UINT hdr->num_of_algorithms = htole32(1); - hdr->digest_sizes[0].alg_id = htole16(tpmalg_from_vb2_hash(TPM_MEASURE_ALGO)); - hdr->digest_sizes[0].digest_size = htole16(vb2_digest_size(TPM_MEASURE_ALGO)); + hdr->digest_sizes[0].alg_id = htole16(tpm2_alg_from_vb2_hash(tpm_log_alg())); + hdr->digest_sizes[0].digest_size = htole16(vb2_digest_size(tpm_log_alg())); tclt->vendor_info_size = sizeof(tclt->vendor); tclt->vendor.reserved = 0; @@ -98,8 +87,8 @@ void tpm2_log_dump(void) if (!tclt) return; - hash_size = vb2_digest_size(TPM_MEASURE_ALGO); - alg_name = vb2_get_hash_algorithm_name(TPM_MEASURE_ALGO); + hash_size = vb2_digest_size(tpm_log_alg()); + alg_name = vb2_get_hash_algorithm_name(tpm_log_alg()); printk(BIOS_INFO, "coreboot TPM 2.0 measurements:\n\n"); for (i = 0; i < le16toh(tclt->vendor.num_entries); i++) { @@ -134,13 +123,13 @@ void tpm2_log_add_table_entry(const char *name, const uint32_t pcr, return; } - if (digest_algo != TPM_MEASURE_ALGO) { + if (digest_algo != tpm_log_alg()) { printk(BIOS_WARNING, "TPM LOG: digest is of unsupported type: %s\n", vb2_get_hash_algorithm_name(digest_algo)); return; } - if (digest_len != vb2_digest_size(TPM_MEASURE_ALGO)) { + if (digest_len != vb2_digest_size(tpm_log_alg())) { printk(BIOS_WARNING, "TPM LOG: digest has invalid length: %d\n", (int)digest_len); return; @@ -158,14 +147,55 @@ void tpm2_log_add_table_entry(const char *name, const uint32_t pcr, tce->event_type = htole32(EV_ACTION); tce->digest_count = htole32(1); - tce->digest_type = htole16(tpmalg_from_vb2_hash(TPM_MEASURE_ALGO)); - memcpy(tce->digest, digest, vb2_digest_size(TPM_MEASURE_ALGO)); + tce->digest_type = htole16(tpm2_alg_from_vb2_hash(tpm_log_alg())); + memcpy(tce->digest, digest, vb2_digest_size(tpm_log_alg())); tce->data_length = htole32(sizeof(tce->data)); strncpy((char *)tce->data, name, sizeof(tce->data) - 1); tce->data[sizeof(tce->data) - 1] = '\0'; } +void tpm2_log_startup_locality(int locality) +{ + _Static_assert(sizeof(struct startup_locality_event) <= TPM_20_LOG_DATA_MAX_LENGTH, + "Data field of TCG log for TPM2 is too short for Startup Locality.\n"); + + struct tpm_2_log_table *tclt; + struct tpm_2_log_entry *tce; + struct startup_locality_event locality_event; + + tclt = tpm_log_init(); + if (!tclt) { + printk(BIOS_WARNING, "TPM LOG: non-existent!\n"); + return; + } + + if (le16toh(tclt->vendor.num_entries) >= le16toh(tclt->vendor.max_entries)) { + printk(BIOS_WARNING, "TPM LOG: log table is full\n"); + return; + } + + tce = &tclt->entries[le16toh(tclt->vendor.num_entries)]; + tclt->vendor.num_entries = htole16(le16toh(tclt->vendor.num_entries) + 1); + + /* EV_NO_ACTION events use PCR-0 by default. */ + tce->pcr = htole32(0); + tce->event_type = htole32(EV_NO_ACTION); + + /* EV_NO_ACTION events use zeroes for digest(s). */ + tce->digest_count = htole32(1); + tce->digest_type = htole16(tpm2_alg_from_vb2_hash(tpm_log_alg())); + memset(tce->digest, 0, vb2_digest_size(tpm_log_alg())); + + tce->data_length = htole32(sizeof(tce->data)); + + strcpy(locality_event.signature, "StartupLocality"); + locality_event.startup_locality = locality; + + memset(tce->data, 0, sizeof(tce->data)); + memcpy(tce->data, &locality_event, sizeof(locality_event)); +} + int tpm2_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, enum vb2_hash_algorithm *digest_algo, const char **event_name) { @@ -183,7 +213,7 @@ int tpm2_log_get(int entry_idx, int *pcr, const uint8_t **digest_data, *pcr = le32toh(tce->pcr); *digest_data = tce->digest; - *digest_algo = TPM_MEASURE_ALGO; /* We validate algorithm on addition */ + *digest_algo = tpm_log_alg(); /* We validate algorithm on addition */ *event_name = (char *)tce->data; return 0; } diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index ea4e9197a27..a04f4070bf9 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -9,6 +9,8 @@ #include #include +#define MAX_TPM_LOG_ENTRIES 50 + void *tpm_cb_log_cbmem_init(void) { static struct tpm_cb_log_table *tclt; diff --git a/src/security/tpm/tspi/logs.h b/src/security/tpm/tspi/logs.h index 2d802f0bc5f..3bfd0909175 100644 --- a/src/security/tpm/tspi/logs.h +++ b/src/security/tpm/tspi/logs.h @@ -3,6 +3,7 @@ #ifndef LOGS_H_ #define LOGS_H_ +#include #include #include @@ -49,6 +50,41 @@ void tpm2_log_add_table_entry(const char *name, const uint32_t pcr, enum vb2_hash_algorithm digest_algo, const uint8_t *digest, const size_t digest_len); +void tpm2_log_startup_locality(int locality); void tpm2_log_dump(void); +static inline uint16_t tpm2_alg_from_vb2_hash(enum vb2_hash_algorithm hash_type) +{ + switch (hash_type) { + case VB2_HASH_SHA1: + return TPM2_ALG_SHA1; + case VB2_HASH_SHA256: + return TPM2_ALG_SHA256; + case VB2_HASH_SHA384: + return TPM2_ALG_SHA384; + case VB2_HASH_SHA512: + return TPM2_ALG_SHA512; + + default: + return 0xFF; + } +} + +static inline enum vb2_hash_algorithm tpm2_alg_to_vb2_hash(uint16_t hash_type) +{ + switch (hash_type) { + case TPM2_ALG_SHA1: + return VB2_HASH_SHA1; + case TPM2_ALG_SHA256: + return VB2_HASH_SHA256; + case TPM2_ALG_SHA384: + return VB2_HASH_SHA384; + case TPM2_ALG_SHA512: + return VB2_HASH_SHA512; + + default: + return VB2_HASH_INVALID; + } +} + #endif /* LOGS_H_ */ diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 56b8fa8ede3..8c951506f29 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -99,7 +99,7 @@ static inline int tspi_tpm_is_setup(void) * need to check tpm_is_setup. Skip that check in all other stages so * this whole function can be evaluated at compile time. */ - if (CONFIG(VBOOT)) { + if (CONFIG(VBOOT) && !CONFIG(VBOOT_NO_TPM)) { if (verification_should_run()) return tpm_is_setup; return vboot_logic_executed(); @@ -227,6 +227,16 @@ tpm_result_t tpm_extend_pcr(int pcr, enum vb2_hash_algorithm digest_algo, if (!digest) return TPM_IOERROR; + if (!tspi_tpm_log_available()) { + rc = tspi_init_crtm(); + if (rc) { + printk(BIOS_WARNING, "Initializing CRTM failed!\n"); + return rc; + } + + printk(BIOS_DEBUG, "CRTM initialized.\n"); + } + if (tspi_tpm_is_setup()) { rc = tlcl_lib_init(); if (rc != TPM_SUCCESS) { @@ -265,9 +275,9 @@ tpm_result_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, if (!rdev || !rname) return TPM_CB_INVALID_ARG; - digest_len = vb2_digest_size(TPM_MEASURE_ALGO); + digest_len = vb2_digest_size(tpm_log_alg()); assert(digest_len <= sizeof(digest)); - if (vb2_digest_init(&ctx, vboot_hwcrypto_allowed(), TPM_MEASURE_ALGO, + if (vb2_digest_init(&ctx, vboot_hwcrypto_allowed(), tpm_log_alg(), region_device_sz(rdev))) { printk(BIOS_ERR, "TPM: Error initializing hash.\n"); return TPM_CB_HASH_ERROR; @@ -293,6 +303,6 @@ tpm_result_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, printk(BIOS_ERR, "TPM: Error finalizing hash.\n"); return TPM_CB_HASH_ERROR; } - return tpm_extend_pcr(pcr, TPM_MEASURE_ALGO, digest, digest_len, rname); + return tpm_extend_pcr(pcr, tpm_log_alg(), digest, digest_len, rname); } #endif /* VBOOT_LIB */ diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 282845e44c1..68d50f4f194 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -391,6 +391,34 @@ tpm_result_t tlcl2_define_space(uint32_t space_index, size_t space_size, } } +tpm_result_t tlcl2_nv_read_public(uint32_t space_index, + struct nv_read_public_response *nvrp_resp) +{ + struct tpm2_nv_read_public_cmd nvrp_cmd; + struct tpm2_response *response; + + /* Prepare the define space command structure. */ + memset(&nvrp_cmd, 0, sizeof(nvrp_cmd)); + + nvrp_cmd.nvIndex = HR_NV_INDEX + space_index; + + response = tlcl2_process_command(TPM2_NV_ReadPublic, &nvrp_cmd); + printk(BIOS_INFO, "%s: response is %x\n", __func__, + response ? response->hdr.tpm_code : -1); + + if (!response) + return TPM_CB_NO_DEVICE; + + /* Map TPM2 return codes into common vboot representation. */ + switch (response->hdr.tpm_code) { + case TPM2_RC_SUCCESS: + memcpy(nvrp_resp, &response->nvrp, sizeof(*nvrp_resp)); + return TPM_SUCCESS; + default: + return TPM_CB_INTERNAL_INCONSISTENCY; + } +} + uint16_t tlcl2_get_hash_size_from_algo(TPMI_ALG_HASH hash_algo) { uint16_t value; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 3039a8b8bae..5bf293e0723 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -197,6 +197,13 @@ static int marshal_nv_define_space(struct obuf *ob, return rc; } +static int marshal_nv_read_public(struct obuf *ob, + const struct tpm2_nv_read_public_cmd *nvrp_in) +{ + return obuf_write_be32(ob, nvrp_in->nvIndex); +} + + static int marshal_nv_setbits(struct obuf *ob, const struct tpm2_nv_setbits_cmd *command_body) { @@ -401,6 +408,10 @@ int tpm_marshal_command(TPM_CC command, const void *tpm_command_body, struct obu rc |= marshal_nv_define_space(ob, tpm_command_body); break; + case TPM2_NV_ReadPublic: + rc |= marshal_nv_read_public(ob, tpm_command_body); + break; + case TPM2_NV_SetBits: rc |= marshal_nv_setbits(ob, tpm_command_body); break; @@ -563,6 +574,80 @@ static int unmarshal_nv_read(struct ibuf *ib, struct nv_read_response *nvr) return 0; } +static int unmarshal_TPM2B_NV_PUBLIC(struct ibuf *ib, TPM2B_NV_PUBLIC *nv_public) +{ + int rc = 0; + + rc |= ibuf_read_be16(ib, &nv_public->t.size); + rc |= ibuf_read_be32(ib, &nv_public->t.nvPublic.nvIndex); + rc |= ibuf_read_be16(ib, &nv_public->t.nvPublic.nameAlg); + rc |= ibuf_read_be32(ib, (uint32_t *)&nv_public->t.nvPublic.attributes); + rc |= ibuf_read_be16(ib, &nv_public->t.nvPublic.authPolicy.t.size); + + nv_public->t.nvPublic.authPolicy.t.buffer = + ibuf_oob_drain(ib, nv_public->t.nvPublic.authPolicy.t.size); + + rc |= ibuf_read_be16(ib, &nv_public->t.nvPublic.dataSize); + + return rc; +} + +static int unmarshal_TPM2B_NAME(struct ibuf *ib, TPM2B_NAME *name) +{ + int rc = 0; + size_t digest_size; + + rc |= ibuf_read_be16(ib, &name->size); + + if (name->size == 0) + return rc; + + /* If size is 4 it is a handle, otherwise it should be a digest */ + if (name->size == 4) { + rc |= ibuf_read_be32(ib, &name->name.handle); + return rc; + } + + rc |= ibuf_read_be16(ib, &name->name.digest.hashAlg); + + switch(name->name.digest.hashAlg) { + case TPM_ALG_SHA1: + digest_size = SHA1_DIGEST_SIZE; + break; + case TPM_ALG_SHA256: + digest_size = SHA256_DIGEST_SIZE; + break; + case TPM_ALG_SHA384: + digest_size = SHA384_DIGEST_SIZE; + break; + case TPM_ALG_SHA512: + digest_size = SHA512_DIGEST_SIZE; + break; + case TPM_ALG_SM3_256: + digest_size = SM3_256_DIGEST_SIZE; + break; + default: + printk(BIOS_WARNING, "%s: Unknown hash algorithm (%02x)\n", + __func__, name->name.digest.hashAlg); + return 1; + } + + memcpy(&name->name.digest.digest, ibuf_oob_drain(ib, digest_size), digest_size); + + return rc; +} + + +static int unmarshal_nv_read_public(struct ibuf *ib, struct nv_read_public_response *nvrp) +{ + int rc = 0; + + rc |= unmarshal_TPM2B_NV_PUBLIC(ib, &nvrp->nvPublic); + rc |= unmarshal_TPM2B_NAME(ib, &nvrp->nvName); + + return rc; +} + static int unmarshal_vendor_command(struct ibuf *ib, struct vendor_command_response *vcr) { @@ -635,6 +720,10 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) rc |= unmarshal_nv_read(ib, &tpm2_static_resp.nvr); break; + case TPM2_NV_ReadPublic: + rc |= unmarshal_nv_read_public(ib, &tpm2_static_resp.nvrp); + break; + case TPM2_Hierarchy_Control: case TPM2_Clear: case TPM2_ClearControl: diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index f2682b18784..5893ffdb68d 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -88,6 +88,7 @@ struct tpm_header { #define TPM2_Startup ((TPM_CC)0x00000144) #define TPM2_Shutdown ((TPM_CC)0x00000145) #define TPM2_NV_Read ((TPM_CC)0x0000014E) +#define TPM2_NV_ReadPublic ((TPM_CC)0x00000169) #define TPM2_GetCapability ((TPM_CC)0x0000017A) #define TPM2_PCR_Extend ((TPM_CC)0x00000182) /* TPM2 specifies vendor commands need to have this bit set. Vendor command @@ -345,6 +346,21 @@ struct nv_read_response { TPM2B_MAX_NV_BUFFER buffer; }; +typedef union { + TPMT_HA digest; + TPM_HANDLE handle; +} TPMU_NAME; + +typedef struct { + uint16_t size; + TPMU_NAME name; +} TPM2B_NAME; + +struct nv_read_public_response { + TPM2B_NV_PUBLIC nvPublic; + TPM2B_NAME nvName; +}; + struct vendor_command_response { uint16_t vc_subcommand; union { @@ -391,6 +407,7 @@ struct tpm2_response { union { struct get_cap_response gc; struct nv_read_response nvr; + struct nv_read_public_response nvrp; struct tpm2_session_header def_space; struct vendor_command_response vcr; }; @@ -401,6 +418,10 @@ struct tpm2_nv_define_space_cmd { TPMS_NV_PUBLIC publicInfo; }; +struct tpm2_nv_read_public_cmd { + TPMI_RH_NV_INDEX nvIndex; +}; + struct tpm2_nv_write_cmd { TPMI_RH_NV_INDEX nvIndex; TPM2B_MAX_NV_BUFFER data; diff --git a/src/security/tpm/tss2.h b/src/security/tpm/tss2.h index 16ccf5db6fb..9bb562a2349 100644 --- a/src/security/tpm/tss2.h +++ b/src/security/tpm/tss2.h @@ -28,6 +28,13 @@ tpm_result_t tlcl2_define_space(uint32_t space_index, size_t space_size, const TPMA_NV nv_attributes, const uint8_t *nv_policy, size_t nv_policy_size); +/* + * Read the public data of NV index. [index] is the index for the space, + * [nvrp_resp] is hte NV index output data. The TPM error code is returned. + */ +tpm_result_t tlcl2_nv_read_public(uint32_t space_index, + struct nv_read_public_response *nvrp_resp); + /* * Issue TPM2_GetCapability command */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 7e291e0c701..9cd2cc265b7 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -105,6 +105,16 @@ config VBOOT_STARTS_IN_ROMSTAGE memory initialization). This implies that the vboot work buffer is in CBMEM from the start and doesn't need to be reserved in memlayout. +config VBOOT_NO_TPM + bool + default y if !TPM + default n + select VBOOT_MOCK_SECDATA + help + When this option is enabled, vboot doesn't attempt to access the TPM + even if one is present. Select this option if you expect the TPM to + not always be available (removed, or disabled in the case of fTPM) + config VBOOT_MOCK_SECDATA bool "Mock secdata for firmware verification" default n diff --git a/src/security/vboot/Makefile.mk b/src/security/vboot/Makefile.mk index e9b3eb69f14..ba0ba9fab28 100644 --- a/src/security/vboot/Makefile.mk +++ b/src/security/vboot/Makefile.mk @@ -25,7 +25,7 @@ VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG $$(VBOOT_LIB_$(1)): $(obj)/config.h printf " MAKE $(subst $(obj)/,,$(@))\n" +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ - CC="$$(CC_$(1))" \ + CC="$$(call vboot-fixup-includes,$$(CC_$(1)))" \ CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ EC_EFS="$(CONFIG_VBOOT_EC_EFS)" \ X86_SHA_EXT="$(if $(CONFIG_ARCH_$(call toupper,$(1))_X86_32)$(CONFIG_ARCH_$(call toupper,$(1))_X86_64),$\ @@ -128,7 +128,9 @@ romstage-$(CONFIG_TPM2) += secdata_tpm2.c ramstage-$(CONFIG_TPM2) += secdata_tpm2.c endif -verstage-$(CONFIG_TPM) += tpm_common.c +ifneq ($(CONFIG_VBOOT_NO_TPM),y) +verstage-y += tpm_common.c +endif romstage-y += common.c @@ -223,6 +225,8 @@ regions-for-file = $(subst $(spc),$(comma),$(sort \ intel_fit_ts \ fspt.bin \ pagetables \ + boot_policy_manifest.bin \ + key_manifest.bin \ $(call strip_quotes,$(CONFIG_RO_REGION_ONLY)) \ ,$(1)),COREBOOT,\ $(if $(filter \ @@ -395,7 +399,7 @@ files_added:: $(obj)/coreboot.rom $(FUTILITY) $(CBFSTOOL) --kernelkey "$(CONFIG_VBOOT_KERNEL_KEY)" \ --version $(CONFIG_VBOOT_KEYBLOCK_VERSION) \ --flags $(CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS) \ - $(obj)/coreboot.rom + $(obj)/coreboot.rom 2> /dev/null if [ "$(CONFIG_VBOOT_SLOTS_RW_AB)" = 'y' ]; then \ printf " FLASHMAP Layout generated for RO, A and B partition.\n"; \ elif [ "$(CONFIG_VBOOT_SLOTS_RW_A)" = 'y' ]; then \ diff --git a/src/security/vboot/tpm_common.h b/src/security/vboot/tpm_common.h index 22ece8927bd..619f328fa2c 100644 --- a/src/security/vboot/tpm_common.h +++ b/src/security/vboot/tpm_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#if CONFIG(TPM) +#if !CONFIG(VBOOT_NO_TPM) /* Start of the root of trust */ tpm_result_t vboot_setup_tpm(struct vb2_context *ctx); diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index 8ec900f762d..b285c992e5d 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -155,6 +155,8 @@ void clear_smi_sci_status(void) smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); } +#if !CONFIG(HUDSON_PSP) + static void clear_psp_smi(void) { uint32_t reg32; @@ -178,3 +180,5 @@ void configure_psp_smi(void) reset_psp_smi(); configure_smi(SMITYPE_PSP, SMI_MODE_SMI); } + +#endif diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f6e918204bf..4303bd7d297 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -42,7 +42,7 @@ config SOC_INTEL_ALDERLAKE select CPU_INTEL_COMMON_VOLTAGE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if CHROMEOS select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC @@ -86,6 +86,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_CRASHLOG if MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON select SOC_INTEL_CSE_SET_EOP + select HAVE_INTEL_ME_HAP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE select SSE2 @@ -403,10 +404,8 @@ config FSP_HEADER_PATH default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if !FSP_USE_REPO && SOC_INTEL_ALDERLAKE_PCH_N default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if !FSP_USE_REPO && SOC_INTEL_RAPTORLAKE default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S @@ -414,10 +413,8 @@ config FSP_HEADER_PATH config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk index 55fc83ea7c5..a3a26bfb3a1 100644 --- a/src/soc/intel/alderlake/Makefile.mk +++ b/src/soc/intel/alderlake/Makefile.mk @@ -18,6 +18,7 @@ bootblock-y += espi.c bootblock-y += p2sb.c bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c +romstage-y += cpu_util.c romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c romstage-y += espi.c romstage-y += meminit.c @@ -76,13 +77,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s endif ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) -# 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples -# 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples -# 06-b7-00 are RPL-S Engineering Samples -# ADL-S/HX C0/H0 and RPL-S C0/H0 -cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 -# RPL-S/HX B0 -cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 +cpu_microcode_bins += 3rdparty/dasharo-blobs/msi/ms7e06/microcode.bin else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00 else diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index ba3a5bcd1ec..cab4b66e8b1 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -104,7 +104,11 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = { static int cstate_set_non_s0ix[] = { C_STATE_C1, C_STATE_C6_LONG_LAT, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + C_STATE_C8 +#else C_STATE_C7S_LONG_LAT +#endif }; static int cstate_set_s0ix[] = { @@ -337,6 +341,8 @@ void soc_fill_gnvs(struct global_nvs *gnvs) /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + gnvs->s0ix = config->s0ix_enable; } int soc_madt_sci_irq_polarity(int sci) diff --git a/src/soc/intel/alderlake/acpi/oc_wdt.asl b/src/soc/intel/alderlake/acpi/oc_wdt.asl new file mode 100644 index 00000000000..072cf89047c --- /dev/null +++ b/src/soc/intel/alderlake/acpi/oc_wdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPCB) { + + /* OC Watchdog */ + Device(CWDT) + { +#if CONFIG(SOC_INTEL_RAPTORLAKE) + Name(_HID,"INTC109C") +#else + Name(_HID,"INTC1099") +#endif + Name(_CID,EISAID("PNP0C02")) + + Name (RBUF, ResourceTemplate () { + IO(Decode16, 0, 0, 0x4, 0x4, OCWD) + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateWordField(^RBUF, ^OCWD._MIN, OMIN) + CreateWordField(^RBUF, ^OCWD._MAX, OMAX) + + OMIN = ACPI_BASE_ADDRESS + 0x54 + OMAX = ACPI_BASE_ADDRESS + 0x54 + + Return (RBUF) + } + } +} diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index 414ced2cb75..919ca8effdd 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -309,6 +309,11 @@ Device (RP12) Device (PEG0) { Name (_ADR, 0x00060000) + + Method (_PRT) + { + Return (IRQM (1)) + } } #endif diff --git a/src/soc/intel/alderlake/acpi/pcie_pch_s.asl b/src/soc/intel/alderlake/acpi/pcie_pch_s.asl index 5437730af12..c2f22b54c0f 100644 --- a/src/soc/intel/alderlake/acpi/pcie_pch_s.asl +++ b/src/soc/intel/alderlake/acpi/pcie_pch_s.asl @@ -275,14 +275,26 @@ Device (RP28) Device (PEG0) { Name (_ADR, 0x00060000) + Method (_PRT) + { + Return (IRQM (1)) + } } Device (PEG1) { Name (_ADR, 0x00010000) + Method (_PRT) + { + Return (IRQM (1)) + } } Device (PEG2) { Name (_ADR, 0x00010001) + Method (_PRT) + { + Return (IRQM (2)) + } } diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 651d26c4eff..fc89cd41f23 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -16,6 +16,9 @@ /* ESPI 0:1f.0 */ #include +/* OC WDT */ +#include "oc_wdt.asl" + /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 6f8eddafe07..85f57f0d89b 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -331,7 +331,7 @@ Scope (\_SB.PCI0) Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) - Name (_STA, 0xF) + Name (_STA, 0xB) } /* @@ -542,47 +542,6 @@ Scope (\_SB.PCI0) } } - PowerResource (TBT0, 5, 1) - { - Method (_STA, 0) - { - Return (\_SB.PCI0.TDM0.STAT) - } - - Method (_ON, 0) - { - TG0N() - } - - Method (_OFF, 0) - { - If (\_SB.PCI0.TDM0.SD3C == 0) { - TG0F() - } - } - } - - PowerResource (TBT1, 5, 1) - { - Method (_STA, 0) - { - Return (\_SB.PCI0.TDM1.STAT) - } - - Method (_ON, 0) - { - TG1N() - } - - Method (_OFF, 0) - { - If (\_SB.PCI0.TDM1.SD3C == 0) { - TG1F() - } - } - } - -#if CONFIG(D3COLD_SUPPORT) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -594,9 +553,9 @@ Scope (\_SB.PCI0) /* Wait for ack, the maximum wait time for the ack is 100 msec. */ While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { /* - * Wait in this loop until TACK becomes 0 with timeout - * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. - */ + * Wait in this loop until TACK becomes 0 with timeout + * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. + */ Sleep (1) /* Delay of 1ms. */ Local0++ } @@ -617,7 +576,7 @@ Scope (\_SB.PCI0) Method (TCOF, 0) { If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0) - || (\_SB.PCI0.TDM1.SD3C != 0)) + || (\_SB.PCI0.TDM1.SD3C != 0)) { Printf("Skip D3C entry.") Return @@ -627,33 +586,74 @@ Scope (\_SB.PCI0) TD3C = 1 } - PowerResource (D3C, 5, 0) - { - /* - * Variable to save power state - * 1 - TC Cold request cleared. - * 0 - TC Cold request sent. - */ - Name (STAT, 0x1) - - Method (_STA, 0) + If (S0IX == 1) { + PowerResource (TBT0, 5, 1) { - Return (STAT) + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM0.STAT) + } + + Method (_ON, 0) + { + TG0N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM0.SD3C == 0) { + TG0F() + } + } } - Method (_ON, 0) + PowerResource (TBT1, 5, 1) { - \_SB.PCI0.TCON() - STAT = 1 + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM1.STAT) + } + + Method (_ON, 0) + { + TG1N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM1.SD3C == 0) { + TG1F() + } + } } - Method (_OFF, 0) + PowerResource (D3C, 5, 0) { - \_SB.PCI0.TCOF() - STAT = 0 + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) + + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } } - } -#endif // D3COLD_SUPPORT + } /* S0IX == 1 */ /* * TCSS xHCI device diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index 2586ecbbc75..428ff083d47 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -28,49 +28,32 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ Method (_S0W, 0x0) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x04) -#else - Return (0x03) -#endif // D3COLD_SUPPORT -} - -/* - * Get power resources that are dependent on this device for Operating System Power Management - * to put the device in the D0 device state - */ -Method (_PR0) -{ -#if CONFIG(D3COLD_SUPPORT) - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } -#else - If (DUID == 0) { - Return (Package() { \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + Return (0x04) } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + Return (0x03) } -#endif // D3COLD_SUPPORT } -Method (_PR3) -{ -#if CONFIG(D3COLD_SUPPORT) - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + +If (S0IX == 1) { + Method (_PR0) + { + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#else - If (DUID == 0) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + + Method (_PR3) + { + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 6dbde46f49d..77f513a5f0c 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -247,45 +247,33 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x4) -#else - Return (0x3) -#endif // D3COLD_SUPPORT -} - -Method (_PR0) -{ -#if CONFIG(D3COLD_SUPPORT) - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + Return (0x04) } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + Return (0x03) } -#else - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) - } -#endif // D3COLD_SUPPORT } -Method (_PR3) -{ -#if CONFIG(D3COLD_SUPPORT) - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + +If (S0IX == 1) { + Method (_PR0) + { + + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#else - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + + Method (_PR3) + { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl index ddc5a6665dc..1ca4117697c 100644 --- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x4) -#else - Return (0x3) -#endif // D3COLD_SUPPORT + If (S0IX == 1) { + Return (0x4) + } Else { + Return (0x3) + } } /* @@ -43,17 +43,17 @@ Method (_S0W, 0x0, NotSerialized) */ Name (SD3C, 0) -#if CONFIG(D3COLD_SUPPORT) -Method (_PR0) -{ - Return (Package () { \_SB.PCI0.D3C }) -} +If (S0IX == 1) { + Method (_PR0) + { + Return (Package () { \_SB.PCI0.D3C }) + } -Method (_PR3) -{ - Return (Package () { \_SB.PCI0.D3C }) + Method (_PR3) + { + Return (Package () { \_SB.PCI0.D3C }) + } } -#endif // D3COLD_SUPPORT /* * XHCI controller _DSM method diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index b8086a42abf..e9a691c37bf 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -5,6 +5,7 @@ #include #include #include +#include #include asmlinkage void bootblock_c_entry(uint64_t base_timestamp) @@ -30,4 +31,7 @@ void bootblock_soc_init(void) /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); + + if (CONFIG(INTEL_CBNT_LOGGING)) + intel_cbnt_log_registers(); } diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 57e4f522da6..21aea57fc5f 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -102,6 +102,7 @@ static struct { { PCI_DID_INTEL_RPL_S_ID_3, "Raptorlake-S (8+8)" }, { PCI_DID_INTEL_RPL_S_ID_4, "Raptorlake-S (6+8)" }, { PCI_DID_INTEL_RPL_S_ID_5, "Raptorlake-S (6+4)" }, + { PCI_DID_INTEL_RPL_S_ID_6, "Raptorlake-S (8+12)" }, }; static struct { @@ -219,6 +220,8 @@ static struct { { PCI_DID_INTEL_ADL_N_GT1, "Alderlake N GT1" }, { PCI_DID_INTEL_ADL_N_GT2, "Alderlake N GT2" }, { PCI_DID_INTEL_ADL_N_GT3, "Alderlake N GT3" }, + { PCI_DID_INTEL_ADL_N_GT4, "Alderlake N GT4" }, + { PCI_DID_INTEL_ADL_N_GT5, "Alderlake N GT5" }, { PCI_DID_INTEL_ADL_S_GT1, "Alderlake S GT1" }, { PCI_DID_INTEL_ADL_S_GT1_1, "Alderlake S GT1" }, { PCI_DID_INTEL_ADL_S_GT2, "Alderlake S GT2" }, @@ -242,6 +245,8 @@ static struct { { PCI_DID_INTEL_RPL_S_GT1_1, "Raptorlake S GT1" }, { PCI_DID_INTEL_RPL_S_GT1_2, "Raptorlake S GT1" }, { PCI_DID_INTEL_RPL_S_GT1_3, "Raptorlake S GT1" }, + { PCI_DID_INTEL_RPL_S_GT1_4, "Raptorlake S GT1" }, + { PCI_DID_INTEL_RPL_S_GT1_5, "Raptorlake S GT1" }, { PCI_DID_INTEL_TWL_GT1_1, "Twinlake GT1" }, { PCI_DID_INTEL_TWL_GT1_2, "Twinlake GT1" }, }; diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 0256de4f820..25ad220c7d0 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -74,7 +74,13 @@ const char *soc_acpi_name(const struct device *dev) return NULL; switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_ROOT: + /* MCHC only for bus 0 */ + if (dev->upstream && dev->upstream->secondary == 0) + return "MCHC"; + else + /* FIXME: handle RTD3 generic dev path in PEP to return correct acpi_name */ + return "PXSX"; #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) case SA_DEVFN_CPU_PCIE1_0: return "PEG1"; case SA_DEVFN_CPU_PCIE1_1: return "PEG2"; diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 040b3d131d2..5169c76b7ef 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -109,6 +109,9 @@ enum soc_intel_alderlake_power_limits { RPL_S_201_35W_CORE, RPL_S_201_46W_CORE, RPL_S_201_65W_CORE, + RPL_S_8121_35W_CORE, + RPL_S_8121_65W_CORE, + RPL_S_8121_125W_CORE, RPL_HX_8_16_55W_CORE, RPL_HX_8_12_55W_CORE, RPL_HX_8_8_55W_CORE, @@ -145,87 +148,91 @@ static const struct { unsigned int cpu_id; enum soc_intel_alderlake_power_limits limits; enum soc_intel_alderlake_cpu_tdps cpu_tdp; + uint8_t pl1_time; } cpuid_to_adl[] = { - { PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_442_482_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_442_482_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_282_442_482_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, - { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, - { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_N_ID_6, ADL_N_041_12W_CORE, TDP_12W }, - { PCI_DID_INTEL_ADL_N_ID_7, ADL_N_041_12W_CORE, TDP_12W }, - { PCI_DID_INTEL_ADL_N_ID_8, ADL_N_021_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_9, ADL_N_021_10W_CORE, TDP_10W }, - { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_150W_CORE, TDP_150W }, - { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_ADL_S_ID_8, ADL_S_642_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_58W_CORE, TDP_58W }, - { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W }, - { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, - { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_150W_CORE, TDP_150W }, - { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_80W_CORE, TDP_80W }, - { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_95W_CORE, TDP_90W }, - { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_58W_CORE, TDP_58W }, - { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_60W_CORE, TDP_60W }, - { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_46W_CORE, TDP_46W }, - { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_HX_ID_1, RPL_HX_8_16_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_2, RPL_HX_8_12_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_3, RPL_HX_8_8_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_4, RPL_HX_6_8_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_5, RPL_HX_6_4_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_6, RPL_HX_8_8_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_7, RPL_HX_6_8_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_8, RPL_HX_6_4_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_442_482_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_442_482_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_282_442_482_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_6, ADL_N_041_12W_CORE, TDP_12W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_7, ADL_N_041_12W_CORE, TDP_12W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_8, ADL_N_021_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_9, ADL_N_021_10W_CORE, TDP_10W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_150W_CORE, TDP_150W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_8, ADL_S_642_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_58W_CORE, TDP_58W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_150W_CORE, TDP_150W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_80W_CORE, TDP_80W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_95W_CORE, TDP_90W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_58W_CORE, TDP_58W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_60W_CORE, TDP_60W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_46W_CORE, TDP_46W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_1, RPL_HX_8_16_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_2, RPL_HX_8_12_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_3, RPL_HX_8_8_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_4, RPL_HX_6_8_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_5, RPL_HX_6_4_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_6, RPL_HX_8_8_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_7, RPL_HX_6_8_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_8, RPL_HX_6_4_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, }; /* Types of display ports */ @@ -413,6 +420,7 @@ struct soc_intel_alderlake_config { bool sata_salp_support; bool sata_ports_enable[8]; bool sata_ports_dev_slp[8]; + bool sata_ports_hotplug[8]; /* * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index 6bcfab1f450..ad998094cee 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -260,6 +260,24 @@ chip soc/intel/alderlake .tdp_pl4 = 65, }" + register "power_limits_config[RPL_S_8121_35W_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 106, + .tdp_pl4 = 194, + }" + + register "power_limits_config[RPL_S_8121_65W_CORE]" = "{ + .tdp_pl1_override = 65, + .tdp_pl2_override = 219, + .tdp_pl4 = 341, + }" + + register "power_limits_config[RPL_S_8121_125W_CORE]" = "{ + .tdp_pl1_override = 125, + .tdp_pl2_override = 253, + .tdp_pl4 = 380, + }" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 00c683c654c..f712d8e1175 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -265,7 +265,8 @@ enum adl_cpu_type get_adl_cpu_type(void) PCI_DID_INTEL_RPL_S_ID_2, PCI_DID_INTEL_RPL_S_ID_3, PCI_DID_INTEL_RPL_S_ID_4, - PCI_DID_INTEL_RPL_S_ID_5 + PCI_DID_INTEL_RPL_S_ID_5, + PCI_DID_INTEL_RPL_S_ID_6 }; const uint16_t rpl_p_mch_ids[] = { diff --git a/src/soc/intel/alderlake/cpu_util.c b/src/soc/intel/alderlake/cpu_util.c new file mode 100644 index 00000000000..b0bc33b6675 --- /dev/null +++ b/src/soc/intel/alderlake/cpu_util.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include + +struct sku_table { + uint16_t sa_devid; + uint8_t num_p_cores; + uint8_t num_e_cores; +}; + +static const struct sku_table adl_sku_table[] = { + // AlderLake CPU Desktop SA Device IDs + { 0x4660, 8, 8 }, // AlderLake Desktop (8+8+GT) SA DID + { 0x4664, 8, 6 }, // AlderLake Desktop (8+6+GT) SA DID + { 0x4668, 8, 4 }, // AlderLake Desktop (8+4+GT) SA DID + { 0x466C, 8, 2 }, // AlderLake Desktop (8+2+GT) SA DID + { 0x4670, 8, 0 }, // AlderLake Desktop (8+0+GT) SA DID + { 0x4640, 6, 8 }, // AlderLake Desktop (6+8+GT) SA DID + { 0x4644, 6, 6 }, // AlderLake Desktop (6+6+GT) SA DID + { 0x4648, 6, 4 }, // AlderLake Desktop (6+4+GT) SA DID + { 0x464C, 6, 2 }, // AlderLake Desktop (6+2+GT) SA DID + { 0x4650, 6, 0 }, // AlderLake Desktop (6+0+GT) SA DID + { 0x4630, 4, 0 }, // AlderLake Desktop (4+0+GT) SA DID + { 0x4610, 2, 0 }, // AlderLake Desktop (2+0+GT) SA DID + { 0x4673, 8, 6 }, // AlderLake Desktop (8+6+GT) SA DID + { 0x4663, 8, 8 }, // AlderLake Desktop BGA (8+8+GT) SA DID + { 0x466B, 8, 4 }, // AlderLake Desktop BGA (8+4+GT) SA DID + { 0x4653, 6, 0 }, // AlderLake Desktop BGA (6+0+GT) SA DID + { 0x4633, 4, 0 }, // AlderLake Desktop BGA (4+0+GT) SA DID + { 0x4637, 8, 8 }, // AlderLake Mobile S BGA (8+8+GT) SA DID + { 0x463B, 6, 8 }, // AlderLake Mobile S BGA (6+8+GT) SA DID + { 0x4623, 4, 8 }, // AlderLake Mobile S BGA (4+8+GT) SA DID + { 0x462B, 4, 4 }, // AlderLake Mobile S BGA (4+4+GT) SA DID + { 0x4647, 6, 4 }, // AlderLake Mobile S BGA (6+4+GT) SA DID + // AlderLake CPU Mobile SA Device IDs + { 0x4641, 6, 8 }, // AlderLake P (6+8+GT) SA DID + { 0x4649, 6, 4 }, // AlderLake P (6+4+GT) SA DID + { 0x4621, 4, 8 }, // AlderLake P (4+8+GT) SA DID + { 0x4609, 2, 4 }, // AlderLake P (2+4+GT) SA DID + { 0x4601, 2, 8 }, // AlderLake P (2+8+GT) SA DID + { 0x4661, 6, 8 }, // AlderLake P (6+8+2) SA DID + { 0x4629, 4, 4 }, // AlderLake P (4+4+1) SA DID + { 0x4619, 1, 4 }, // AlderLake P (1+4+GT) SA DID + { 0x4659, 1, 8 }, // AlderLake P (1+8+GT) SA DID + { 0x4645, 6, 6 }, // AlderLake P (6+6+GT) SA DID + { 0x4602, 2, 8 }, // AlderLake M (2+8+GT) SA DID + { 0x460A, 2, 4 }, // AlderLake M (2+4+GT) SA DID + { 0x461A, 1, 4 }, // AlderLake M (1+4+GT) SA DID + { 0x4622, 1, 8 }, // AlderLake M (1+8+GT) SA DID + { 0x4617, 0, 8 }, // AlderLake N (0+8+1) SA DID + { 0x4614, 0, 2 }, // AlderLake N Celeron (0+2+0) SA DID + { 0x4618, 0, 4 }, // AlderLake N (0+4+0) SA DID + { 0x461B, 0, 4 }, // AlderLake N Pentium (0+4+0) SA DID + { 0x461C, 0, 4 }, // AlderLake N Celeron (0+4+0) SA DID + { 0x4603, 2, 8 }, // AlderLake PS (2+8+GT) SA DID + { 0x4643, 6, 8 }, // AlderLake PS (6+8+GT) SA DID + { 0x4627, 4, 8 }, // AlderLake PS (4+8+GT) SA DID + { 0x460B, 2, 4 }, // AlderLake PS (2+4+GT) SA DID + { 0x464B, 4, 4 }, // AlderLake PS (4+4+GT) SA DID + { 0x467B, 1, 4 }, // AlderLake PS (1+4+GT) SA DID + // RaptorLake CPU Desktop SA Device IDs + { 0xA700, 8, 16 }, // RaptorLake Desktop (8+16+GT) SA DID + { 0xA701, 8, 0 }, // RaptorLake Desktop (8+0+GT) SA DID + { 0xA702, 8, 16 }, // RaptorLake Desktop(BGA) (8+16+GT) SA DID + { 0xA703, 8, 8 }, // RaptorLake Desktop (8+8+GT) SA DID + { 0xA704, 6, 8 }, // RaptorLake Desktop (6+8+GT) SA DID + { 0xA705, 6, 4 }, // RaptorLake Desktop (6+4+GT) SA DID + { 0xA717, 8, 0 }, // RaptorLake Desktop(BGA) (8+0+GT) SA DID + { 0xA718, 8, 4 }, // RaptorLake Desktop(BGA) (8+4+GT) SA DID + { 0xA719, 6, 4 }, // RaptorLake Desktop(BGA) (6+4+GT) SA DID + { 0xA71A, 4, 4 }, // RaptorLake Desktop(BGA) (4+4+GT) SA DID + { 0xA728, 8, 8 }, // RaptorLake Desktop(BGA) (8+8+GT) SA DID + { 0xA729, 8, 12 }, // RaptorLake Desktop(BGA) (8+12+GT) SA DID + { 0xA72A, 6, 8 }, // RaptorLake Desktop(BGA) (6+8+GT) SA DID + { 0xA72B, 4, 0 }, // RaptorLake Desktop (4+0+GT) SA DID + { 0xA740, 8, 12 }, // RaptorLake Desktop (8+12+GT) SA DID + // RaptorLake CPU Mobile SA Device IDs + { 0xA706, 6, 8 }, // RaptorLake P (6+8+GT) SA DID + { 0xA707, 4, 8 }, // RaptorLake P (4+8+GT) SA DID + { 0xA708, 2, 8 }, // RaptorLake P (2+8+GT) SA DID + { 0xA716, 4, 4 }, // RaptorLake P (4+4+GT) SA DID + { 0xA709, 6, 8 }, // RaptorLake Px (6+8+GT) SA DID + { 0xA70A, 4, 8 }, // RaptorLake Px (4+8+GT) SA DID + { 0xA70B, 2, 8 }, // RaptorLake Px (2+8+GT) SA DID + { 0xA715, 6, 4 }, // RaptorLake P (6+4+GT) SA DID + { 0xA71B, 2, 4 }, // RaptorLake P (2+4+GT) SA DID + { 0xA71C, 1, 4 }, // RaptorLake P (1+4+GT) SA DID + { 0xA734, 6, 8 }, // RaptorLake PS (6+8+GT) SA DID + { 0xA735, 4, 8 }, // RaptorLake PS (4+8+GT) SA DID + { 0xA736, 2, 8 }, // RaptorLake PS (2+8+GT) SA DID + { 0xA737, 2, 4 }, // RaptorLake PS (2+4+GT) SA DID + { 0xA738, 6, 4 }, // RaptorLake PS (6+4+GT) SA DID + { 0xA739, 4, 4 }, // RaptorLake PS (4+4+GT) SA DID + { 0xA73A, 1, 4 } // RaptorLake PS (1+4+GT) SA DID +}; + +void get_num_core_types(uint8_t *num_e_cores, uint8_t *num_p_cores) +{ + uint16_t sa_devid = pci_read_config16(SA_DEV_ROOT, 2); + + *num_p_cores = 0; + *num_e_cores = 0; + + if (pci_read_config16(SA_DEV_ROOT, 0) != 0x8086) + return; + + for (size_t i = 0; i < ARRAY_SIZE(adl_sku_table); i++) { + if (adl_sku_table[i].sa_devid == sa_devid) { + *num_p_cores = adl_sku_table[i].num_p_cores; + *num_e_cores = adl_sku_table[i].num_e_cores; + break; + } + } +} diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 700fde977b3..615729d3dd3 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -85,7 +85,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8a03b05c213..7eec13dbd58 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -647,6 +648,7 @@ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_confi case PCI_DID_INTEL_RPL_S_ID_3: case PCI_DID_INTEL_RPL_S_ID_4: case PCI_DID_INTEL_RPL_S_ID_5: + case PCI_DID_INTEL_RPL_S_ID_6: return ICC_MAX_RPL_S; default: printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", @@ -715,6 +717,11 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, fill_fsps_microcode_params(s_cfg, config); else s_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); + +#if CONFIG(FSP_TYPE_IOT) && CONFIG(HAVE_ACPI_RESUME) + if (!s_cfg->SkipMpInit) + s_cfg->CpuFeaturesInitOnS3ResumeOverride = 1; +#endif } static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, @@ -756,9 +763,11 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, */ s_cfg->ITbtConnectTopologyTimeoutInMs = 0; + s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER); + /* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT); + s_cfg->D3ColdEnable = get_sleep_type_option() == SLEEP_TYPE_OPTION_S0IX; s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { @@ -862,6 +871,8 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, sizeof(s_cfg->SataPortsEnable)); memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp, sizeof(s_cfg->SataPortsDevSlp)); + memcpy(s_cfg->SataPortsHotPlug, config->sata_ports_hotplug, + sizeof(s_cfg->SataPortsHotPlug)); } /* @@ -894,7 +905,7 @@ static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); /* Set TccActivationOffset */ - s_cfg->TccActivationOffset = config->tcc_offset; + s_cfg->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); } static void fill_fsps_gna_params(FSP_S_CONFIG *s_cfg, @@ -1038,7 +1049,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); -#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#if CONFIG(FSP_TYPE_IOT) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 @@ -1184,7 +1195,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, s_cfg->C1e = config->enable_c1e; else s_cfg->C1e = 1; -#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) +#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_TYPE_IOT) s_cfg->EnableHwpScalabilityTracking = config->enable_hwp_scalability_tracking; #endif } @@ -1411,7 +1422,7 @@ static void wait_for_panel_power_cycle_done(const struct soc_intel_alderlake_con if (!CONFIG(RUN_FSP_GOP)) return; - bar0 = pci_s_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0); + bar0 = pci_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0); mmio = (void *)(bar0 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); if (!mmio) return; diff --git a/src/soc/intel/alderlake/hsphy.c b/src/soc/intel/alderlake/hsphy.c index 005d85149f4..05e15d452be 100644 --- a/src/soc/intel/alderlake/hsphy.c +++ b/src/soc/intel/alderlake/hsphy.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -43,6 +44,8 @@ struct ip_push_model { uint32_t data[]; } __packed; +static bool dma_protection_en = CONFIG(ENABLE_EARLY_DMA_PROTECTION) ? true : false; + static int heci_get_hsphy_payload(void *buf, uint32_t *buf_size, uint8_t *hash_buf, uint8_t *hash_alg, uint32_t *status) { @@ -319,7 +322,7 @@ static void *allocate_hsphy_buf(void) void *hsphy_buf; size_t dma_buf_size; - if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) { + if (dma_protection_en) { hsphy_buf = vtd_get_dma_buffer(&dma_buf_size); if (!hsphy_buf || dma_buf_size < HSPHY_PAYLOAD_SIZE) { printk(BIOS_ERR, "DMA protection enabled but DMA buffer does not" @@ -360,6 +363,8 @@ void load_and_init_hsphy(void) return; } + dma_protection_en = CONFIG(ENABLE_EARLY_DMA_PROTECTION) && dma_protection_enabled(); + /* * Try to get HSPHY payload from CSME first, so we can always keep our * HSPHY cache up to date. If we cannot allocate the buffer for it, the @@ -400,7 +405,7 @@ void load_and_init_hsphy(void) printk(BIOS_ERR, "%s: CSME not enabled or not visible, but required\n", __func__); printk(BIOS_ERR, "Aborting HSPHY FW loading, PCIe Gen5 won't work.\n"); - if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + if (!dma_protection_en) free(hsphy_buf); return; } @@ -424,7 +429,7 @@ void load_and_init_hsphy(void) cache_hsphy_fw_in_flash(hsphy_buf, buf_size, hsphy_hash, hash_type); - if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + if (!dma_protection_en) free(hsphy_buf); return; } else { @@ -434,7 +439,7 @@ void load_and_init_hsphy(void) printk(BIOS_ERR, "Failed to get HSPHY FW over HECI.\n"); } - if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + if (!dma_protection_en) free(hsphy_buf); /* We failed to get HSPHY payload from CSME, cache is our last chance. */ diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index d081e85a575..c83f959a0d4 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -35,4 +35,6 @@ enum adl_cpu_type get_adl_cpu_type(void); /* Get a bitmask of supported LPM states */ uint8_t get_supported_lpm_mask(void); +void get_num_core_types(uint8_t *num_e_cores, uint8_t *num_p_cores); + #endif diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h index 1cea6cc766f..1d11fc67c56 100644 --- a/src/soc/intel/alderlake/include/soc/gpio.h +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -3,7 +3,7 @@ #ifndef _SOC_ALDERLAKE_GPIO_H_ #define _SOC_ALDERLAKE_GPIO_H_ -#if CONFIG(SOC_INTEL_RAPTORLAKE) && CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#if CONFIG(SOC_INTEL_RAPTORLAKE_PCH_S) #include #define CROS_GPIO_NAME "INTC1085" #define CROS_GPIO_DEVICE_NAME "INTC1085:00" diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 010a2101ea5..0f7ce302495 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -5,81 +5,81 @@ #include -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _SA_DEVFN(slot, func) PCI_DEVFN(SA_DEV_SLOT_ ## slot, func) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) +#define _SA_DEV(slot, func) pcidev_path_on_root(_SA_DEVFN(slot, func)) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _SA_DEV(slot, func) PCI_DEV(0, SA_DEV_SLOT_ ## slot, func) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#define SA_DEVFN_ROOT _SA_DEVFN(ROOT, 0) #if defined(__SIMPLE_DEVICE__) -#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#define SA_DEV_ROOT _SA_DEV(ROOT, 0) #endif #define SA_DEV_SLOT_CPU_1 0x01 -#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0) -#define SA_DEVFN_CPU_PCIE1_1 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 1) +#define SA_DEVFN_CPU_PCIE1_0 _SA_DEVFN(CPU_1, 0) +#define SA_DEVFN_CPU_PCIE1_1 _SA_DEVFN(CPU_1, 1) #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) -#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEVFN_IGD _SA_DEVFN(IGD, 0) +#define SA_DEV_IGD _SA_DEV(IGD, 0) #define SA_DEV_SLOT_DPTF 0x04 -#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) -#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) +#define SA_DEVFN_DPTF _SA_DEVFN(DPTF, 0) +#define SA_DEV_DPTF _SA_DEV(DPTF, 0) #define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEVFN_IPU _SA_DEVFN(IPU, 0) +#define SA_DEV_IPU _SA_DEV(IPU, 0) #define SA_DEV_SLOT_CPU_6 0x06 -#define SA_DEVFN_CPU_PCIE6_0 PCI_DEVFN(SA_DEV_SLOT_CPU_6, 0) -#define SA_DEVFN_CPU_PCIE6_2 PCI_DEVFN(SA_DEV_SLOT_CPU_6, 2) +#define SA_DEVFN_CPU_PCIE6_0 _SA_DEVFN(CPU_6, 0) +#define SA_DEVFN_CPU_PCIE6_2 _SA_DEVFN(CPU_6, 2) #define SA_DEV_SLOT_TBT 0x07 -#define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) +#define SA_DEVFN_TBT(x) _SA_DEVFN(TBT, (x)) #define NUM_TBT_FUNCTIONS 4 -#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) -#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) -#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) -#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) -#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) -#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) -#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) -#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEVFN_TBT0 _SA_DEVFN(TBT, 0) +#define SA_DEVFN_TBT1 _SA_DEVFN(TBT, 1) +#define SA_DEVFN_TBT2 _SA_DEVFN(TBT, 2) +#define SA_DEVFN_TBT3 _SA_DEVFN(TBT, 3) +#define SA_DEV_TBT0 _SA_DEV(TBT, 0) +#define SA_DEV_TBT1 _SA_DEV(TBT, 1) +#define SA_DEV_TBT2 _SA_DEV(TBT, 2) +#define SA_DEV_TBT3 _SA_DEV(TBT, 3) #define SA_DEV_SLOT_GNA 0x08 -#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) -#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) +#define SA_DEVFN_GNA _SA_DEVFN(GNA, 0) +#define SA_DEV_GNA _SA_DEV(GNA, 0) #define SA_DEV_SLOT_TMT 0x0A -#define SA_DEVFN_TMT _SA_DEVFN(TMT) -#define SA_DEV_TMT _SA_DEV(TMT) +#define SA_DEVFN_TMT _SA_DEVFN(TMT, 0) +#define SA_DEV_TMT _SA_DEV(TMT, 0) #define SA_DEV_SLOT_TCSS 0x0d #define NUM_TCSS_DMA_FUNCTIONS 2 -#define SA_DEVFN_TCSS_DMA(x) PCI_DEVFN(SA_DEV_SLOT_TCSS, ((x) + 2)) -#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) -#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) -#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) -#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) -#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) -#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) -#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) -#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) +#define SA_DEVFN_TCSS_DMA(x) _SA_DEVFN(TCSS, ((x) + 2)) +#define SA_DEVFN_TCSS_XHCI _SA_DEVFN(TCSS, 0) +#define SA_DEVFN_TCSS_XDCI _SA_DEVFN(TCSS, 1) +#define SA_DEVFN_TCSS_DMA0 _SA_DEVFN(TCSS, 2) +#define SA_DEVFN_TCSS_DMA1 _SA_DEVFN(TCSS, 3) +#define SA_DEV_TCSS_XHCI _SA_DEV(TCSS, 0) +#define SA_DEV_TCSS_XDCI _SA_DEV(TCSS, 1) +#define SA_DEV_TCSS_DMA0 _SA_DEV(TCSS, 2) +#define SA_DEV_TCSS_DMA1 _SA_DEV(TCSS, 3) #define SA_DEV_SLOT_VMD 0x0e -#define SA_DEVFN_VMD PCI_DEVFN(SA_DEV_SLOT_VMD, 0) -#define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0) +#define SA_DEVFN_VMD _SA_DEVFN(VMD, 0) +#define SA_DEV_VMD _SA_DEV(VMD, 0) /* PCH Devices */ #define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 8930a06251c..58c9fa87712 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -108,7 +108,7 @@ static void soc_pmc_fill_ssdt(const struct device *dev) acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller"); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 4a03b7438f5..75222fc2043 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -82,7 +84,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; clk_req_mapping |= 1 << cfg[i].clk_req; } - m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); + /* + * Override the usage only if the clock is unused, otherwise we lose + * FSP_CLK_FREE_RUNNING and FSP_CLK_LAN setting from fill_fspm_pcie_rp_params. + */ + if (m_cfg->PcieClkSrcUsage[cfg[i].clk_src] == FSP_CLK_NOTUSED) + m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); } } @@ -163,7 +170,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->DdrFreqLimit = config->max_dram_speed_mts; m_cfg->DdrSpeedControl = 1; } -#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) +#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_TYPE_IOT) m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; m_cfg->DisableSagvReorder = config->disable_sagv_reorder; #endif @@ -172,6 +179,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { + uint8_t max_e_cores, max_p_cores; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; /* CpuRatio Settings */ if (config->cpu_ratio_override) @@ -182,7 +191,28 @@ static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; - m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); + m_cfg->HyperThreading = get_hyper_threading_option(); + + m_cfg->ActiveCoreCount = get_active_core_count_option(); + m_cfg->ActiveSmallCoreCount = get_active_small_core_count_option(); + + get_num_core_types(&max_e_cores, &max_p_cores); + + if (max_e_cores == 0 && max_p_cores == 0) { + /* Could not identify SKU, enable all cores */ + m_cfg->ActiveCoreCount = ALL_CORES_ACTIVE; + m_cfg->ActiveSmallCoreCount = ALL_CORES_ACTIVE; + } + + if (m_cfg->ActiveCoreCount == 0) { + /* Invalid setting, enable all P-cores */ + m_cfg->ActiveCoreCount = ALL_CORES_ACTIVE; + } + + if (max_p_cores == 0 && m_cfg->ActiveSmallCoreCount == 0) { + /* Invalid setting, enable all E-cores */ + m_cfg->ActiveSmallCoreCount = ALL_CORES_ACTIVE; + } } static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, @@ -316,7 +346,7 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, m_cfg->VtdIgdEnable = m_cfg->InternalGfx; m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable; - m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION); + m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION) && dma_protection_enabled(); if (m_cfg->VtdIgdEnable && m_cfg->VtdBaseAddress[VTD_GFX] == 0) { m_cfg->VtdIgdEnable = 0; @@ -367,8 +397,8 @@ static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { /* In-Band ECC configuration */ - if (config->ibecc.enable) { - m_cfg->Ibecc = config->ibecc.enable; + if (get_ibecc_option(config->ibecc.enable)) { + m_cfg->Ibecc = 1; m_cfg->IbeccOperationMode = config->ibecc.mode; if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable, diff --git a/src/soc/intel/alderlake/spi.c b/src/soc/intel/alderlake/spi.c index 11494251014..3c71efd39be 100644 --- a/src/soc/intel/alderlake/spi.c +++ b/src/soc/intel/alderlake/spi.c @@ -10,7 +10,8 @@ #include #include -#define PSF_SPI_DESTINATION_ID 0x23a8 +#define PCH_LP_PSF_SPI_DESTINATION_ID 0x23a8 +#define PCH_S_PSF_SPI_DESTINATION_ID 0x23b8 int spi_soc_devfn_to_bus(unsigned int devfn) { @@ -29,5 +30,8 @@ int spi_soc_devfn_to_bus(unsigned int devfn) uint32_t soc_get_spi_psf_destination_id(void) { - return PSF_SPI_DESTINATION_ID; + if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) + return PCH_S_PSF_SPI_DESTINATION_ID; + else + return PCH_LP_PSF_SPI_DESTINATION_ID; } diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index be0c6996a49..91cd684aa7b 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -183,7 +183,7 @@ void soc_systemagent_init(struct device *dev) if (sa_pci_id == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) { soc_config = &config->power_limits_config[cpuid_to_adl[i].limits]; - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + set_power_limits(cpuid_to_adl[i].pl1_time, soc_config); break; } } diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 95dba9fbd03..423c02d3872 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -170,6 +170,9 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, @@ -240,6 +243,9 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_ICC(120, 30) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_ICC(140, 30) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, @@ -310,6 +316,9 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -380,6 +389,9 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(51, 22) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(69, 22) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(140, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(94, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 22) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 55f59b3bed7..18152a920e8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -60,14 +60,18 @@ config SOC_INTEL_APOLLOLAKE select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS - select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_NO_MSR_SPCL_CHIPSET_USAGE + select SOC_INTEL_COMMON_BLOCK_TCO + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_RESET select SOC_INTEL_INTEGRATED_SOUTHCLUSTER diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index a304331f1d3..d4c148504dd 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -56,6 +56,84 @@ Method (_CRS, 0, Serialized) 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, 0x00020000,,,) + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000) + /* * PCI MMIO Region (TOLUD - PCI extended base MMCONF) * This assumes that MMCONF is placed after PCI config space, @@ -75,6 +153,12 @@ Method (_CRS, 0, Serialized) NonCacheable, ReadWrite, 0x00000000, 0x00010000, 0x0001ffff, 0x00000000, 0x00010000,,, PM02) + + /* TPM Area (0xfed40000-0xfed47fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) }) /* Find PCI resource area in MCRS */ diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index b47ac24c3ee..6d557a6fa73 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -58,6 +58,7 @@ Method(_PRT) Package(){0x001DFFFF, 0, 0, UFS_INT}, #endif Package(){0x001EFFFF, 0, 0, SDIO_INT}, - Package(){0x001FFFFF, 0, 0, SMBUS_INT}, + Package(){0x001FFFFF, 0, 0, ESPI_INT}, + Package(){0x001FFFFF, 1, 0, SMBUS_INT}, }) } diff --git a/src/soc/intel/apollolake/acpi/smbus.asl b/src/soc/intel/apollolake/acpi/smbus.asl new file mode 100644 index 00000000000..468e84469d5 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/smbus.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel SMBus Controller 0:1f.4 */ + +Device (SBUS) +{ + Name (_ADR, 0x001f0001) +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f857bb97a07..c7db6049763 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -20,6 +20,9 @@ /* LPC */ #include +/* SMBUS */ +#include "smbus.asl" + /* eMMC */ #include "scs.asl" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ab5b5d884d0..c6730afbab0 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -348,6 +348,10 @@ static void soc_final(void *data) static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) { switch (dev->path.pci.devfn) { + case PCH_DEVFN_DPTF: + /* FSP does not offer an option to disable DPTF, use DEVEN register */ + pci_update_config32(pcidev_path_on_root(SA_DEVFN_ROOT), 0x54, ~2, 0); + break; case PCH_DEVFN_NPK: /* * Disable this device in the parse_devicetree_setting() function @@ -711,6 +715,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->SpiEiss = 0; silconfig->RtcLock = 0; + /* Enable CLKRUN */ + silconfig->PciClockRun = 1; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; @@ -733,6 +740,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); + /* High Precision Timer options */ + silconfig->HpetBdfValid = 1; + silconfig->HpetBusNumber = 0xFA; + silconfig->HpetDeviceNumber = 0x0F; + silconfig->HpetFunctionNumber = 0; + + /* IO-APIC options */ + silconfig->IoApicId = 2; + silconfig->IoApicBdfValid = 1; + silconfig->IoApicBusNumber = 0xFA; + silconfig->IoApicDeviceNumber = 0x1F; + silconfig->IoApicFunctionNumber = 0; + silconfig->PavpEnable = CONFIG(PAVP); /* SATA config */ @@ -750,6 +770,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* 8254 Timer */ bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + /* Timer8254ClkSetting is in fact Timer8254ClkGateEn, so invert the value */ silconfig->Timer8254ClkSetting = !use_8254; /* FSP should let coreboot set subsystem IDs, which are read/write-once */ diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index b8bf39197ea..3c15edbf274 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -28,7 +28,19 @@ #include #include #include -#include +#include + +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(IA32_PERF_STATUS); + return ((msr.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ; +} + +unsigned int smbios_processor_external_clock(void) +{ + return CONFIG_CPU_BCLK_MHZ; +} static const struct reg_script core_msr_script[] = { #if !CONFIG(SOC_INTEL_GEMINILAKE) @@ -76,6 +88,9 @@ void soc_core_init(struct device *cpu) if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || acpi_get_sleep_type() == ACPI_S5) mca_configure(); + /* Enable the local CPU apics */ + enable_lapic_tpr(); + /* Set core MSRs */ reg_script_run(core_msr_script); @@ -91,6 +106,12 @@ void soc_core_init(struct device *cpu) */ enable_pm_timer_emulation(); + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + /* Set Max Non-Turbo ratio if RAPL is disabled. */ if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); diff --git a/src/soc/intel/apollolake/include/soc/irq.h b/src/soc/intel/apollolake/include/soc/irq.h index 8e28ca182b8..e63be223c1e 100644 --- a/src/soc/intel/apollolake/include/soc/irq.h +++ b/src/soc/intel/apollolake/include/soc/irq.h @@ -43,6 +43,7 @@ #define EMMC_INT 39 #define PMC_INT 40 #define SDIO_INT 42 +#define ESPI_INT 43 #define CNVI_INT 44 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index aaa5f9b3524..509bbaa7dbb 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -125,6 +125,8 @@ void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg, void save_lpddr4_dimm_info(const struct lpddr4_cfg *lpcfg, size_t mem_sku); void save_lpddr4_dimm_info_part_num(const char *dram_part_num); +void save_ddr4_dimm_info(void); + /* Retrieve the amount of memory configured in the system in MiB. It's only * valid during romstage. */ size_t memory_in_system_in_mib(void); diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index cc31370d93f..e891e127d70 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -39,6 +39,9 @@ #define SA_GLK_DEV_GMM PCI_DEV(0, SA_GLK_DEV_SLOT_GMM, 0) /* PCH Devices */ +#define PCH_DEV_SLOT_DPTF 0x00 +#define PCH_DEVFN_DPTF _PCH_DEVFN(DPTF, 1) +#define PCH_DEV_DPTF _PCH_DEV(DPTF,1) #define PCH_DEV_SLOT_NPK 0x00 #define PCH_DEVFN_NPK _PCH_DEVFN(NPK, 2) diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index c7a57c8f9dc..8455d08779c 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include +#include +#include #include #include #include @@ -24,9 +27,24 @@ void lpc_soc_init(struct device *dev) const struct soc_intel_apollolake_config *cfg; cfg = config_of(dev); + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + lpc_enable_pci_clk_cntl(); + /* Set LPC Serial IRQ mode */ lpc_set_serirq_mode(cfg->serirq_mode); + /* Interrupt configuration */ + pch_enable_ioapic(); + pch_pirq_init(); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); + + /* Initialize i8254 timers */ + setup_i8254(); + /* Initialize RTC */ rtc_init(); } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 753451a3530..8016f5fdfc9 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -7,6 +7,9 @@ #include #include #include +#include + +#include #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -112,3 +115,109 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) save_lpddr4_dimm_info_part_num(part_num); } + +/* Save the DIMM information for SMBIOS table 17 */ +void save_ddr4_dimm_info(void) +{ + int channel, dimm, dimm_max, index, node; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = + fsp_find_extension_hob_by_guid(smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE_NUM; node++) { + ctrlr_info = &memory_info_hob->Controller[node]; + + if (!ctrlr_info->ChannelCount) { + printk(BIOS_DEBUG, "No valid channels on controller %d\n", node); + continue; + } + + for (channel = 0; channel < MAX_CHANNELS_NUM; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + + if (index >= dimm_max) + break; + + if (!channel_info->Status) { + printk(BIOS_DEBUG, "Channel %d not present\n", channel); + continue; + } + + if (!channel_info->DimmCount) { + printk(BIOS_DEBUG, "No valid DIMMs on controller %d channel %d\n", node, channel); + continue; + } + + for (dimm = 0; dimm < MAX_DIMMS_NUM; dimm++) { + if (index >= dimm_max) + break; + + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (!src_dimm->Status) { + printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n", node, channel, dimm); + continue; + } + + if (!src_dimm->DimmCapacity) { + printk(BIOS_DEBUG, "DIMM %d/%d/%d has 0 capacity\n", node, channel, dimm); + continue; + } + + u8 memProfNum = memory_info_hob->MemoryProfile; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType, + node, + memory_info_hob->MaximumMemoryClockSpeed); + index++; + } // for dimm + } // for channel + } // for node + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 5366ca8bafb..ed445e0e792 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -93,11 +93,23 @@ uint32_t soc_get_smi_status(uint32_t generic_sts) return generic_sts & ~(1 << GPE0_STS_BIT); } + +/* + * TCO + */ const char *const *soc_tco_sts_array(size_t *a) { static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", [3] = "TIMEOUT", - [17] = "SECOND_TO", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", }; *a = ARRAY_SIZE(tco_sts_bits); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 09fdbbaae40..01c49909755 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -6,7 +6,6 @@ config SOC_INTEL_BAYTRAIL select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 - select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED @@ -34,6 +33,7 @@ config SOC_INTEL_BAYTRAIL select TCO_SPACE_NOT_YET_SPLIT select USE_DDR3 select NEED_SMALL_2MB_PAGE_TABLES + select UDK_2017_BINDING help Bay Trail M/D part support. @@ -83,7 +83,11 @@ config MRC_BIN_ADDRESS default 0xfffa0000 config MRC_RMT - bool "Enable MRC RMT training + debug prints" + bool "Enable MRC RMT training" + default n + +config MRC_DEBUG_PRINTS + bool "Enable MRC debug prints" default n # Cache As RAM region layout: @@ -158,4 +162,110 @@ config VGA_BIOS_ID depends on VGA_BIOS default "8086,0f31" +config TXE_SECURE_BOOT + bool "Perform verified boot with TXE Secure Boot" + depends on !VBOOT + default n + help + The TXE on Baytrail SOC has Secure Boot capability. Choose this + option to enable the TXE Secure Boot verified boot flow in coreboot. + +config TXE_SB_INCLUDE_KEY_MANIFEST + bool "Include TXE Secure Boot Key Manifest" + depends on TXE_SECURE_BOOT + default n + help + The TXE on Baytrail SOC has Secure Boot capability. Choose this + option to include the TXE Secure Boot Key Manifest, which can be + used to authorize the Secure Boot firmware signing key. This key + should be fused into TXE FPF instead of Secure Boot firmware signing + key. TXE Key Manifest ID FPF must not be zero in such case. + + Key Manifest is optional. + +config TXE_SB_GENERATE_KEY_MANIFEST + bool "Generate TXE Secure Boot Key Manifest" + depends on TXE_SB_INCLUDE_KEY_MANIFEST + default n + help + The TXE on Baytrail SOC has Secure Boot capability. Choose this + option to generate the TXE Secure Boot Key Manifest, which can be + used to authorize the Secure Boot firmware signing key. This key + should be fused into TXE FPF instead of Secure Boot firmware signing + key. TXE Key Manifest ID FPF must not be zero in such case. + + Key Manifest is optional. + +config TXE_SB_KEY_MANIFEST_PATH + string "TXE Secure Boot Key Manifest file path" + depends on TXE_SB_INCLUDE_KEY_MANIFEST && !TXE_SB_GENERATE_KEY_MANIFEST + default "" + help + THe path to a pre-generated TXE Secure Boot Key Manifest to be included + in the coreboot image. + + Key Manifest is optional. + +config TXE_SB_KEY_MANIFEST_KEY_PATH + string "Include TXE Secure Boot Key Manifest Signing Key path" + depends on TXE_SB_GENERATE_KEY_MANIFEST + default "" + help + Path to the signing key used to generate TXE Secure Boot Key Manifest. + RSA2048 private key in PEM or DER format required. + + Key Manifest is optional. + +config TXE_SB_KEY_MANIFEST_ID + int "TXE Secure Boot Key Manifest ID value" + depends on TXE_SB_GENERATE_KEY_MANIFEST + range 1 15 + default 1 + help + Key Manifest ID used to generate TXE Secure Boot Key Manifest. + + Key Manifest is optional. + +config TXE_SB_KEY_MANIFEST_SVN + int "TXE Secure Boot Key Manifest SVN value" + depends on TXE_SB_GENERATE_KEY_MANIFEST + range 0 15 + default 2 + help + Secure Version Number used to generate TXE Secure Boot Key Manifest. + + Key Manifest is optional. + +config TXE_SB_SBM_MANIFEST_KEY_PATH + string "Include TXE Secure Boot Manifest Signing Key path" + depends on TXE_SECURE_BOOT + default "" + help + Path to the signing key used to generate TXE Secure Boot Manifest. + RSA2048 private key in PEM or DER format required. + +config TXE_SB_SBM_MANIFEST_SVN + int "TXE Secure Boot Manifest SVN value" + depends on TXE_SECURE_BOOT + range 0 63 + default 2 + help + Secure Version Number used to generate TXE Secure Boot Manifest. + + Key Manifest is optional. + +if TXE_SECURE_BOOT + +# Put the microcode right after the manifest, so it will be verified by IBB +# and accessible without walkcbfs ASM routine if CBFS_VERIFICATION is enabled. +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfffe1000 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x19800 + +endif + endif diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 281175c9a8d..615d289e144 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -84,4 +84,53 @@ mrc.bin-position := $(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) mrc.bin-type := mrc endif + +ifeq ($(CONFIG_TXE_SECURE_BOOT),y) + +cbfs-files-y += manifests.bin +manifests.bin-file := $(objcbfs)/sb_manifests +manifests.bin-type := raw + +ifeq ($(CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST),y) + +manifests.bin-COREBOOT-position := $(call int-subtract, 0x100000000 0x21000) + +ifneq ($(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH)),) + +$(objcbfs)/sb_manifests: $(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH)) + dd if=/dev/zero of=$@ bs=5120 count=1 2> /dev/null + dd if=$< of=$@ conv=notrunc 2> /dev/null +else + +$(objcbfs)/sb_manifests: + dd if=/dev/zero of=$@ bs=5120 count=1 2> /dev/null + endif + +else # CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST + +manifests.bin-COREBOOT-position := $(call int-subtract, 0x100000000 0x20000) + +$(objcbfs)/sb_manifests: + dd if=/dev/zero of=$@ bs=1024 count=1 2> /dev/null + +endif # CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST + +files_added:: $(obj)/coreboot.rom $(TXESBMANTOOL) + if [ "$(CONFIG_TXE_SB_GENERATE_KEY_MANIFEST)" = 'y' ]; then \ + $(TXESBMANTOOL) $(obj)/coreboot.rom generate-km \ + --sbm-key-file $(CONFIG_TXE_SB_SBM_MANIFEST_KEY_PATH) \ + --km-key-file $(CONFIG_TXE_SB_KEY_MANIFEST_KEY_PATH) \ + --km-id $(CONFIG_TXE_SB_KEY_MANIFEST_ID) \ + --svn $(CONFIG_TXE_SB_KEY_MANIFEST_SVN) \ + ;\ + printf " TXE Secure Boot Key Manifest generated.\n"; \ + fi; \ + $(TXESBMANTOOL) $(obj)/coreboot.rom generate-sbm \ + --sbm-key-file $(CONFIG_TXE_SB_SBM_MANIFEST_KEY_PATH) \ + --svn $(CONFIG_TXE_SB_SBM_MANIFEST_SVN) ;\ + printf " TXE Secure Boot Manifest generated.\n\n"; \ + +endif # CONFIG_TXE_SECURE_BOOT + +endif # CONFIG_SOC_INTEL_BAYTRAIL diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 5933070a6b2..e41fcc09601 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -118,6 +118,23 @@ Device (LPCB) }) } +#if CONFIG(ENABLE_BUILTIN_COM1) + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + } +#endif + /* Include mainboard's superio.asl file. */ #include "acpi/superio.asl" } diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 3f07a6b4396..d1bd2b9d381 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -66,15 +66,21 @@ static void spi_init(void) static void byt_config_com1_and_enable(void) { - uint32_t reg; + uint32_t reg32; - /* Enable the UART hardware for COM1. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + /* Enable COM1 for debug message output. */ + reg32 = read32((const volatile void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + reg32 &= ~(SUS_PWR_FLR | PWR_FLR); + reg32 |= UART_EN; + write32 ((volatile void *)(PMC_BASE_ADDRESS + GEN_PMCON1), reg32); /* Set up the pads to select the UART function */ + ssus_enable_internal_pull(UART_RXD_PAD, PAD_PU_2K | PAD_PULL_UP); score_select_func(UART_RXD_PAD, 1); score_select_func(UART_TXD_PAD, 1); + + /* Enable the legacy UART hardware. */ + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 1); } static void setup_mmconfig(void) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 2a4616cec35..81c0212aab9 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -14,12 +14,38 @@ #include #include #include +#include #include #include #include #include #include +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + unsigned int ratio = (rdmsr(IA32_PERF_STATUS).lo >> 8) & 0x1f; + + return bus_freq_khz() * ratio / 1000; +} + +unsigned int smbios_processor_external_clock(void) +{ + return bus_freq_khz() / 1000; +} + +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + unsigned int ratio = (rdmsr(IA32_PLATFORM_ID).lo >> 8) & 0x1f; + + return bus_freq_khz() * ratio / 1000; +} + +unsigned int smbios_processor_family(struct cpuid_result res) +{ + return 0x2b; /* Intel Atom */ +} + + /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 0b19922f14d..ba94c5d5bea 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -233,7 +233,7 @@ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -#define GPIO_OUT_LOW \ +#define GPIO_OUT_LOW_LEGACY \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ @@ -242,7 +242,7 @@ .gp_lvl = GPIO_LEVEL_LOW, \ .is_gpio = 1 } -#define GPIO_OUT_HIGH \ +#define GPIO_OUT_HIGH_LEGACY \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ @@ -251,6 +251,24 @@ .gp_lvl = GPIO_LEVEL_HIGH, \ .is_gpio = 1 } +#define GPIO_OUT_LOW \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ + .use_sel = GPIO_USE_MMIO, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_LOW, \ + .is_gpio = 1 } + +#define GPIO_OUT_HIGH \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ + .use_sel = GPIO_USE_MMIO, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_HIGH, \ + .is_gpio = 1 } + /* Define no-pull / PU / PD configs for each functional config option */ #define GPIO_FUNC(_func, _pudir, _str) \ { .use_sel = GPIO_USE_MMIO, \ @@ -448,4 +466,32 @@ static inline void ssus_enable_internal_pull(int pad, int mask) (read32(ssus_pconf0(pad)) & pull_mask) | mask); } +static inline void setup_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) +{ + uint32_t reg; + uint32_t *pad_addr = ssus_pconf0(gpio_num); + /* + * Pad Configuration 0 Register + * 2:0 - func_pin_mux + * 8:7 - Pull assignment: 00 - Non pull 01 - Pull Up 10 - Pull down + * 11 - reserved + * 10:9 - Pull strength: 00 - 2K 01 - 10K 10 - 20K 11 - 40K + */ + reg = PAD_CONFIG0_DEFAULT; + reg |= pconf0 & 0x787; + write32(pad_addr + (PAD_CONF0_REG/sizeof(u32)), reg); + + /* + * Pad Value Register + * 0: Pad value + * 1: output enable (0 is enabled) + * 2: input enable (0 is enabled) + */ + reg = read32(pad_addr + (PAD_VAL_REG/sizeof(u32))); + reg &= ~0x7; + reg |= pad_val & 0x7; + write32(pad_addr + (PAD_VAL_REG/sizeof(u32)), reg); +} + + #endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h index 3a1d7c79e42..e13cae82a46 100644 --- a/src/soc/intel/baytrail/include/soc/irq.h +++ b/src/soc/intel/baytrail/include/soc/irq.h @@ -77,7 +77,6 @@ #define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) /* PIC IRQ settings. */ -#define PIRQ_PIC_IRQDISABLE 0x0 #define PIRQ_PIC_IRQ3 0x3 #define PIRQ_PIC_IRQ4 0x4 #define PIRQ_PIC_IRQ5 0x5 @@ -89,6 +88,8 @@ #define PIRQ_PIC_IRQ12 0xc #define PIRQ_PIC_IRQ14 0xe #define PIRQ_PIC_IRQ15 0xf +#define PIRQ_PIC_IRQDISABLE 0x80 +#define PIRQ_PIC_UNKNOWN_UNUSED 0xff /* Overloaded term, but these values determine the per device route. */ #define PIRQA 0 @@ -110,7 +111,7 @@ # define SCIS_IRQ21 0x05 # define SCIS_IRQ22 0x06 # define SCIS_IRQ23 0x07 - +#define ILB_MC 0x04 /* * In each mainboard directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which diff --git a/src/soc/intel/baytrail/include/soc/lpc.h b/src/soc/intel/baytrail/include/soc/lpc.h index 7b3fbf8c900..6fb1aa8ed5e 100644 --- a/src/soc/intel/baytrail/include/soc/lpc.h +++ b/src/soc/intel/baytrail/include/soc/lpc.h @@ -36,4 +36,14 @@ enum baytrail_stepping { #define GCS 0x00 # define BILD (1 << 0) +/* iLB Memory Mapped IO */ +#define ILB_OIC 0x60 +#define SIRQEN (1 << 12) +#define AEN (1 << 8) + +/* Memory Mapped IO in LPC bridge */ +#define ILB_SERIRQ_CNTL 0x10 +#define SCNT_CONTINUOUS_MODE (1 << 7) +#define SCNT_QUIET_MODE 0 + #endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/pci_devs.h b/src/soc/intel/baytrail/include/soc/pci_devs.h index 74acb8ea45c..dff1307fa84 100644 --- a/src/soc/intel/baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/baytrail/include/soc/pci_devs.h @@ -13,6 +13,10 @@ #define GFX_DEV 0x2 #define GFX_FUNC 0 +/* MIPI */ +#define MIPI_DEV 0x3 +#define MIPI_FUNC 0 + /* MMC Port */ #define MMC_DEV 0x10 #define MMC_FUNC 0 @@ -37,6 +41,10 @@ #define LPE_DEV 0x15 #define LPE_FUNC 0 +/* OTG */ +#define OTG_DEV 0x16 +#define OTG_FUNC 0 + /* MMC45 Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 @@ -107,6 +115,7 @@ #define SOC_DEVID 0x0f00 #define GFX_DEVID 0x0f31 +#define MIPI_DEVID 0x0f38 #define MMC_DEVID 0x0f14 #define SDIO_DEVID 0x0f15 #define SD_DEVID 0x0f16 @@ -116,6 +125,7 @@ #define AHCI2_DEVID 0x0f23 #define XHCI_DEVID 0x0f35 #define LPE_DEVID 0x0f28 +#define OTG_DEVID 0x0f37 #define MMC45_DEVID 0x0f50 #define SIO_DMA1_DEVID 0x0f40 #define I2C1_DEVID 0x0f41 diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index dea44733833..9d276ec1343 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -66,10 +66,13 @@ #define HSUART1_DIS (1 << 3) #define HSUART2_DIS (1 << 4) #define SPI_DIS (1 << 5) -#define MMC_DIS (1 << 8) +/* Baytrail EDS says this should be 11 but it appears to be wrong */ +#define MIPI_DIS (1 << 8) #define SDIO_DIS (1 << 9) #define SD_DIS (1 << 10) -#define MMC45_DIS (1 << 11) +/* Baytrail EDS says these should be 8 but it appears to be wrong */ +#define MMC45_DIS (1 << 11) +#define MMC_DIS (1 << 11) #define HDA_DIS (1 << 12) #define LPE_DIS (1 << 13) #define OTG_DIS (1 << 14) diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index fa1b957ba12..9ed7c3b6d1f 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -104,6 +105,55 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) } #define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) +#define PIN_SET_FOR_I2C 0x2003C881 + +static void i2c_set_pins(struct device *dev) +{ + switch (dev->path.pci.devfn) { + CASE_I2C(I2C1) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0210), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0200), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C2) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01F0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01E0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C3) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01D0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01B0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C4) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0190), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01C0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C5) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01A0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0170), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C6) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0150), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0140), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C7) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0180), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0160), + PIN_SET_FOR_I2C); + break; + } +} static void i2c_disable_resets(struct device *dev) { @@ -144,6 +194,7 @@ static void lpss_init(struct device *dev) } dev_enable_snoop_and_pm(dev, iosf_reg); i2c_disable_resets(dev); + i2c_set_pins(dev); if (config->lpss_acpi_mode) dev_enable_acpi_mode(dev, iosf_reg, nvs_index); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 6244072c55c..37565317f74 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -50,7 +50,8 @@ int smbus_enable_iobar(uintptr_t base) static void ABI_X86 send_to_console(unsigned char b) { - do_putchar(b); + if (CONFIG(MRC_DEBUG_PRINTS)) + do_putchar(b); } static void populate_smbios_tables(void *dram_data, int speed, int num_channels) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 658da2c44b0..c1d6a08dc5a 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -85,6 +85,16 @@ static int chipset_prev_sleep_state(const struct chipset_power_state *ps) return prev_sleep_state; } +static void print_txe_status(const char* timepoint) +{ + pci_devfn_t txe = PCI_DEV(0, TXE_DEV, TXE_FUNC); + + printk(BIOS_DEBUG, "TXE status %s\n", timepoint); + printk(BIOS_DEBUG, "TXE SEC FWSTS0 %08x\n", pci_read_config32(txe, 0x40)); + printk(BIOS_DEBUG, "TXE SEC FWSTS1 %08x\n", pci_read_config32(txe, 0x48)); + printk(BIOS_DEBUG, "TXE SB STATUS %08x\n", pci_read_config32(txe, 0x50)); +} + /* Entry from cpu/intel/car/romstage.c */ void mainboard_romstage_entry(void) { @@ -112,9 +122,13 @@ void mainboard_romstage_entry(void) elog_boot_notify(s3resume); + print_txe_status("before MRC"); + /* Initialize RAM */ raminit(&mp, prev_sleep_state); + print_txe_status("after MRC"); + timestamp_add_now(TS_INITRAM_END); romstage_handoff_init(s3resume); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 1afea590a23..45c61d30f69 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -2,6 +2,8 @@ #include #include +#include +#include #include #include #include @@ -11,6 +13,9 @@ #include #include #include +#include +#include +#include #include #include @@ -135,30 +140,265 @@ static void com1_configure_resume(struct device *dev) outb(3, port + UART8250_LCR); } -static void sc_init(struct device *dev) + +static void sc_enable_ioapic(struct device *dev) { int i; + u32 reg32; + volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10); + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); + + /* + * Enable ACPI I/O and power management. + * Set SCI IRQ to IRQ9 + */ + write32(ilb_base + ILB_OIC, 0x100); /* AEN */ + reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ + write32(ilb_base + ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + /* affirm full set of redirection table entries ("write once") */ + *ioapic_index = 1; + reg32 = *ioapic_data; + *ioapic_index = 1; + *ioapic_data = reg32; + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); + for (i=0; i<3; i++) { + *ioapic_index = i; + printk(BIOS_SPEW, " reg 0x%04x:", i); + reg32 = *ioapic_data; + printk(BIOS_SPEW, " 0x%08x\n", reg32); + } + + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ +} + +static void sc_enable_serial_irqs(struct device *dev) +{ +#ifdef SETUPSERIQ /* NOT defined. Remove when the TODO is done. */ + /* + * TODO: SERIRQ seems to have a number of problems on baytrail. + * With it enabled, we get some spurious interrupts (ps2) + * in seabios. It also caused IOCHK# NMIs. Remove it + * until we understand how it needs to be configured. + */ + u8 reg8; + u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); + + /* + * Disable the IOCHK# NMI. Let the NMI handler enable it if it needs. + */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 |= (1 << 3); /* IOCHK# NMI Disable for now */ + outb(reg8, 0x61); + + write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); + write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); + + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) { + /* + * SoC requires that the System BIOS first set the SERIRQ logic to + * continuous mode operation for at least one frame before switching + * it into quiet mode operation. + */ + outb(0x00, 0xED); /* I/O Delay to get the 1 frame */ + write8(ibase + ILB_SERIRQ_CNTL, SCNT_QUIET_MODE); + } +#endif /* DON'T SET UP IRQS */ +} + +/* + * Write PCI config space IRQ assignments. PCI devices have the INT_LINE + * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing + * information to operating systems and drivers. The INT_PIN register is + * generally read only and reports which interrupt pin A - D it uses. The + * INT_LINE register is configurable and reports which IRQ (generally the + * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling + * on devices that are downstream on a PCI bridge into account. + * + * This function will loop through all enabled PCI devices and program the + * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it + * uses. It then configures each interrupt in the pic to be level triggered. + */ +static void write_pci_config_irqs(void) +{ + struct device *irq_dev; + struct device *targ_dev; + uint8_t int_line = 0; + uint8_t original_int_pin = 0; + uint8_t new_int_pin = 0; + uint16_t current_bdf = 0; + uint16_t parent_bdf = 0; + uint8_t pirq = 0; + uint8_t device_num = 0; + const struct baytrail_irq_route *ir = &global_baytrail_irq_route; + + if (ir == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'global_baytrail_irq_route' structure does not exist\n"); + return; + } + + /* + * Loop through all enabled devices and program their + * INT_LINE, INT_PIN registers from values taken from + * the Interrupt Route registers in the ILB + */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + + if ((irq_dev->path.type != DEVICE_PATH_PCI) || + (!irq_dev->enabled)) + continue; + + current_bdf = irq_dev->path.pci.devfn | + irq_dev->upstream->secondary << 8; + + /* + * Step 1: Get the INT_PIN and device structure to look for + * in the pirq_data table defined in the mainboard directory. + */ + targ_dev = NULL; + new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); + if (targ_dev == NULL || new_int_pin < 1) + continue; + + /* + * Adjust the INT routing for the PCIe root ports + * See 'Interrupt Generated for INT[A-D] Interrupts' + * Table 241 in Document Number: 538136, Rev. 3.9 + */ + if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV && + targ_dev != irq_dev) + new_int_pin = ((new_int_pin - 1 + + PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1; + + /* Get the original INT_PIN for record keeping */ + original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + parent_bdf = targ_dev->path.pci.devfn + | targ_dev->upstream->secondary << 8; + device_num = PCI_SLOT(parent_bdf); + + /* Find the PIRQ that is attached to the INT_PIN this device uses */ + pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; + + /* Get the INT_LINE this device/function will use */ + int_line = ir->pic[pirq]; + + if (int_line != PIRQ_PIC_IRQDISABLE) { + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + /* Set the Interrupt Line register in PCI config space */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } else { + /* Set the Interrupt line register as "unknown or unused" */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, + PIRQ_PIC_UNKNOWN_UNUSED); + } + + printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", + original_int_pin, pin_to_str(original_int_pin)); + if (parent_bdf != current_bdf) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + new_int_pin, pin_to_str(new_int_pin)); + printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + 'A' + pirq, int_line, int_line); + } + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} + +static void sc_pirq_init(struct device *dev) +{ + int i, j; + int pirq; u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); - u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - struct soc_intel_baytrail_config *config = config_of(dev); /* Set up the PIRQ PIC routing based on static config. */ + printk(BIOS_SPEW, "Start writing IRQ assignments\n" + "PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n" + "IRQ "); for (i = 0; i < NUM_PIRQS; i++) { write8(pr_base + i, ir->pic[i]); + printk(BIOS_SPEW, "\t%d", ir->pic[i]); } - /* Set up the per device PIRQ routing base on static config. */ - for (i = 0; i < NUM_IR_DEVS; i++) { + printk(BIOS_SPEW, "\n\n"); + + /* Set up the per device PIRQ routing based on static config. */ + printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" + "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); + for (i = 0; i < 32; i++) { write16(ir_base + i, ir->pcidev[i]); + + /* If the entry is more than just 0, print it out */ + if (ir->pcidev[i]) { + printk(BIOS_SPEW, " %d: ", i); + for (j = 0; j < 4; j++) { + pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; + printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]); + } + printk(BIOS_SPEW, "\n"); + } } /* Route SCI to IRQ9 */ write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); + printk(BIOS_SPEW, "Finished writing IRQ assignments\n"); + + /* Write IRQ assignments to PCI config space */ + write_pci_config_irqs(); +} + +static void sc_init(struct device *dev) +{ + struct soc_intel_baytrail_config *config = config_of(dev); + u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); + u8 *ibase; + + printk(BIOS_DEBUG, "soc: southcluster_init\n"); + + ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); + + write8(ibase + ILB_MC, 0); cmos_init(rtc_failure()); + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + + /* IO APIC initialization. */ + sc_enable_ioapic(dev); + + sc_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + sc_pirq_init(dev); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + setup_i8259(); + + setup_i8254(); + if (config->disable_slp_x_stretch_sus_fail) { printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); @@ -175,6 +415,14 @@ static void sc_init(struct device *dev) * Common code for the south cluster devices. */ +#define SET_DIS_MASK(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask |= name_ ## _DIS +#define SET_DIS_MASK2(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask2 |= name_ ## _DIS + + /* Set bit in function disable register to hide this device. */ static void sc_disable_devfn(struct device *dev) { @@ -184,94 +432,72 @@ static void sc_disable_devfn(struct device *dev) uint32_t mask2 = 0; switch (dev->path.pci.devfn) { - case PCI_DEVFN(MMC_DEV, MMC_FUNC): - mask |= MMC_DIS; + SET_DIS_MASK(MIPI); break; - case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): - mask |= SDIO_DIS; + SET_DIS_MASK(SDIO); break; - case PCI_DEVFN(SD_DEV, SD_FUNC): - mask |= SD_DIS; + SET_DIS_MASK(SD); break; - case PCI_DEVFN(SATA_DEV, SATA_FUNC): - mask |= SATA_DIS; + SET_DIS_MASK(SATA); break; - case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): - mask |= XHCI_DIS; + SET_DIS_MASK(XHCI); /* Disable super speed PHY when XHCI is not available. */ mask2 |= USH_SS_PHY_DIS; break; - case PCI_DEVFN(LPE_DEV, LPE_FUNC): - mask |= LPE_DIS; + SET_DIS_MASK(LPE); break; - case PCI_DEVFN(MMC45_DEV, MMC45_FUNC): - mask |= MMC45_DIS; + SET_DIS_MASK(MMC); break; - case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): - mask |= SIO_DMA1_DIS; + SET_DIS_MASK(MMC45); break; - case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): - mask |= I2C1_DIS; + SET_DIS_MASK(SIO_DMA1); break; - case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): - mask |= I2C1_DIS; + SET_DIS_MASK(I2C1); break; - case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): - mask |= I2C3_DIS; + SET_DIS_MASK(I2C2); break; - case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): - mask |= I2C4_DIS; + SET_DIS_MASK(I2C3); break; - case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): - mask |= I2C5_DIS; + SET_DIS_MASK(I2C4); break; - case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): - mask |= I2C6_DIS; + SET_DIS_MASK(I2C5); break; - case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): - mask |= I2C7_DIS; + SET_DIS_MASK(I2C6); break; - case PCI_DEVFN(TXE_DEV, TXE_FUNC): - mask |= TXE_DIS; + SET_DIS_MASK(I2C7); break; - case PCI_DEVFN(HDA_DEV, HDA_FUNC): - mask |= HDA_DIS; + SET_DIS_MASK(TXE); break; - case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): - mask |= PCIE_PORT1_DIS; + SET_DIS_MASK(HDA); break; - case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): - mask |= PCIE_PORT2_DIS; + SET_DIS_MASK(PCIE_PORT1); break; - case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): - mask |= PCIE_PORT3_DIS; + SET_DIS_MASK(PCIE_PORT2); break; - case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): - mask |= PCIE_PORT4_DIS; + SET_DIS_MASK(PCIE_PORT3); break; - case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): - mask |= EHCI_DIS; + SET_DIS_MASK(PCIE_PORT4); break; - case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): - mask |= SIO_DMA2_DIS; + SET_DIS_MASK2(SMBUS); break; - case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): - mask |= PWM1_DIS; + SET_DIS_MASK(EHCI); break; - case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): - mask |= PWM2_DIS; + SET_DIS_MASK(SIO_DMA2); break; - case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): - mask |= HSUART1_DIS; + SET_DIS_MASK(PWM1); break; - case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): - mask |= HSUART2_DIS; + SET_DIS_MASK(PWM2); break; - case PCI_DEVFN(SPI_DEV, SPI_FUNC): - mask |= SPI_DIS; + SET_DIS_MASK(HSUART1); break; - case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): - mask2 |= SMBUS_DIS; + SET_DIS_MASK(HSUART2); + break; + SET_DIS_MASK(SPI); + break; + + SET_DIS_MASK(OTG); + /* Disable OTG PHY when OTG is not available. */ + mask2 |= OTG_SS_PHY_DIS; break; } @@ -526,6 +752,8 @@ static void finalize_chipset(void *unused) write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } + + apm_control(APM_CNT_FINALIZE); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 59b09a5d332..a37a9ec54e8 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -22,6 +22,7 @@ config SOC_INTEL_CANNONLAKE_BASE select HAVE_FSP_LOGO_SUPPORT select HAVE_HYPERTHREADING select HAVE_INTEL_FSP_REPO + select HAVE_INTEL_ME_HAP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -51,6 +52,7 @@ config SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 + select SOC_INTEL_COMMON_BLOCK_OC_WDT select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS @@ -95,7 +97,7 @@ config SOC_INTEL_COMETLAKE select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if CHROMEOS config SOC_INTEL_COMETLAKE_1 bool @@ -324,10 +326,25 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xe00 +config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS + default 300 + +if INTEL_TXT + config INTEL_TXT_BIOSACM_ALIGNMENT - hex default 0x40000 # 256KB +config INTEL_TXT_DPR_SIZE + default 4 + +config INTEL_TXT_SINIT_SIZE + default 0x50000 + +config INTEL_TXT_HEAP_SIZE + default 0xf0000 + +endif + config INTEL_GMA_BCLV_OFFSET default 0xc8258 diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 974794bd977..461ba3a884e 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -87,7 +87,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) heci1_disable(); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index df5fcee36f1..488780bc892 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -670,7 +671,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) #endif /* Set TccActivationOffset */ - tconfig->TccActivationOffset = config->tcc_offset; + tconfig->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); tconfig->TccOffsetClamp = config->tcc_offset > 0; /* Unlock all GPIO pads */ @@ -709,6 +710,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) s_cfg->PchLockDownRtcMemoryLock = lockdown_by_fsp; tconfig->SkipPamLock = !lockdown_by_fsp; #if CONFIG(SOC_INTEL_COMETLAKE) + supd->FspsConfig.DebugInterfaceEnable = 0; + supd->FspsTestConfig.DebugInterfaceEnable = 0; + /* + * IA32_DEBUG_INTERFACE_MSR has to be locked by coreboot, + * because FSP does not do it unless DebugInterfaceEnable is 1 + */ + supd->FspsTestConfig.DebugInterfaceLockEnable = 0; /* * Making this config "0" means FSP won't set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index 3205c7f303b..c2656e620af 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -1,11 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include #include #include +#define MSR_IA32_DEBUG_INTERFACE 0xc80 +#define MSR_IA32_DEBUG_INTERFACE_EN (1 << 0) +#define MSR_IA32_DEBUG_INTERFACE_LOCK (1 << 30) + static void pmc_lock_pmsync(void) { uint8_t *pmcbase; @@ -55,8 +61,22 @@ static void pmc_lockdown_cfg(int chipset_lockdown) pmc_lock_smi(); } +static void cpu_lockdown_cfg(void) +{ + msr_t msr = rdmsr(MSR_IA32_DEBUG_INTERFACE); + + if (!(msr.lo & MSR_IA32_DEBUG_INTERFACE_LOCK)) { + if (CONFIG(INTEL_TXT)) + msr.lo &= ~MSR_IA32_DEBUG_INTERFACE_EN; + + msr.lo |= MSR_IA32_DEBUG_INTERFACE_LOCK; + wrmsr(MSR_IA32_DEBUG_INTERFACE, msr); + } +} + void soc_lockdown_config(int chipset_lockdown) { /* PMC lock down configuration */ pmc_lockdown_cfg(chipset_lockdown); + cpu_lockdown_cfg(); } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index b3777b686f7..bd4be6a635d 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -6,9 +6,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -122,6 +124,8 @@ void mainboard_romstage_entry(void) bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + setup_oc_wdt(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ @@ -130,6 +134,10 @@ void mainboard_romstage_entry(void) cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + if (CONFIG(INTEL_TXT)) + intel_txt_romstage_init(); + fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) { diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 827bedd50d3..df354c77cfd 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -54,6 +54,15 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID help Defines hybrid CPU specific ACPI helper functions. +config SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS + bool + depends on SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID + help + Core performance and efficient scaling factors are read at runtime + using the soc_read_core_scaling_factors() function instead of using + statically defined values SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and + SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR. + config SOC_INTEL_UFS_OCP_TIMER_DISABLE bool help diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index d683726d866..a9bb3b7f875 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -402,6 +402,7 @@ void generate_cpu_entries(const struct device *device) sgx_fill_ssdt(); } +#if !CONFIG(SOC_INTEL_COMMON_OC_WDT_WDAT) static bool fill_wdat_timeout_entry(acpi_wdat_entry_t *entry) { @@ -574,3 +575,5 @@ unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) return current; } + +#endif /* #if !CONFIG(SOC_INTEL_COMMON_OC_WDT_WDAT) */ diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index adda519e901..e9bbb737eba 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -23,4 +23,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve) U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume , 64, // 0x30 - 0x37 Hest log buffer (used in SMM, not ASL code) + S0IX, 8, // 0x38 - Sleep Type (1 = S0IX, 0 = S3) } diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 68abba7eb8d..2c3b84ceee9 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -15,11 +15,6 @@ #define CPPC_NOM_FREQ_IDX 22 #define CPPC_NOM_PERF_IDX 3 -enum cpu_perf_eff_type { - CPU_TYPE_EFF, - CPU_TYPE_PERF, -}; - struct cpu_apic_info_type { /* * Ordered APIC IDs based on core type. @@ -113,18 +108,27 @@ void set_dev_core_type(void) static void acpi_get_cpu_nomi_perf(u16 *eff_core_nom_perf, u16 *perf_core_nom_perf) { u8 max_non_turbo_ratio = cpu_get_max_non_turbo_ratio(); + static u16 performance, efficient; - _Static_assert(CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR != 0, + _Static_assert(CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) || + CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR != 0, "CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR must not be zero"); - _Static_assert(CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR != 0, + _Static_assert(CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) || + CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR != 0, "CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR must not be zero"); - *perf_core_nom_perf = (u16)((max_non_turbo_ratio * - CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR) / 100); + if (!performance) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS)) { + soc_read_core_scaling_factors(&performance, &efficient); + } else { + performance = CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR; + efficient = CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR; + } + } - *eff_core_nom_perf = (u16)((max_non_turbo_ratio * - CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR) / 100); + *perf_core_nom_perf = (u16)((max_non_turbo_ratio * performance) / 100); + *eff_core_nom_perf = (u16)((max_non_turbo_ratio * efficient) / 100); } static u16 acpi_get_cpu_nominal_freq(void) diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index a6ae454d063..183c53513e5 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -190,6 +190,9 @@ static void acpi_lpi_get_constraints(void *unused) if (min_sleep_state == ACPI_DEVICE_SLEEP_NONE) continue; + if (dev->path.type == DEVICE_PATH_PCI && !dev->enabled) + continue; + acpigen_write_package(3); { /* Emit the device path */ diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index c077fb84418..b681f362ac2 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -300,17 +301,20 @@ uint8_t cpu_get_max_non_turbo_ratio(void) void configure_tcc_thermal_target(void) { const config_t *conf = config_of_soc(); + uint32_t tcc_offset; msr_t msr; - if (!conf->tcc_offset) + tcc_offset = get_cpu_throttling_offset(conf->tcc_offset); + + if (!tcc_offset) return; /* Set TCC activation offset */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & BIT(30))) { msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); - msr.lo |= (conf->tcc_offset & 0xf) << 24; + msr.lo &= ~(0x3f << 24); + msr.lo |= (tcc_offset & 0x3f) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 63890444280..5f07ef38c48 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -3,13 +3,16 @@ #define __SIMPLE_DEVICE__ #include +#include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -275,6 +278,11 @@ bool cse_is_hfs1_com_secover_mei_msg(void) return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG); } +bool cse_is_hfs1_com_debug(void) +{ + return cse_check_hfs1_com(ME_HFS1_COM_DEBUG); +} + bool cse_is_hfs1_com_soft_temp_disable(void) { return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); @@ -1173,7 +1181,7 @@ void cse_enable_ptt(bool state) */ if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal() || !cse_is_hfs1_fw_init_complete() || !ENV_RAMSTAGE) { - printk(BIOS_ERR, "HECI: Unmet prerequisites for" + printk(BIOS_ERR, "HECI: Unmet prerequisites for " "FW FEATURE SHIPMENT TIME STATE OVERRIDE\n"); return; } @@ -1216,6 +1224,97 @@ void cse_enable_ptt(bool state) #if ENV_RAMSTAGE +#ifndef HAP_OFFSET +#define HAP_OFFSET 0 +#endif + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A +#define SI_DESC_SIZE 0x1000 +#define SI_DESC_REGION "SI_DESC" + +/* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */ +static bool is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_ERR, "Flash Descriptor is not valid\n"); + return 0; + } + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); + return 0; + } + return 1; +} + +static void cse_set_hap_bit(bool state) +{ + uint8_t *si_desc_buf; + struct region_device desc_rdev; + + si_desc_buf = (uint8_t *)malloc(SI_DESC_SIZE); + + if (!si_desc_buf) { + printk(BIOS_ERR, "Failed to allocate buffer for %s\n", SI_DESC_REGION); + return; + } + + if (fmap_locate_area_as_rdev_rw("SI_DESC", &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + free(si_desc_buf); + return; + } + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + free(si_desc_buf); + return; + } + if (!is_descriptor_writeable(si_desc_buf)) { + free(si_desc_buf); + return; + } + + if (!!(si_desc_buf[HAP_OFFSET] & 1) == state) { + printk(BIOS_DEBUG, "Update of Descriptor is not required!\n"); + if (state) + printk(BIOS_INFO, "ME is HAP disabled\n"); + free(si_desc_buf); + return; + } + + si_desc_buf[HAP_OFFSET] ^= 1; + if (rdev_eraseat(&desc_rdev, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + free(si_desc_buf); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + free(si_desc_buf); + return; + } + + printk(BIOS_DEBUG, "Update of Descriptor successful\n"); + free(si_desc_buf); + do_global_reset(); +} + +static void set_hap_bit(void *unused) +{ + bool state = cse_get_me_disable_mode() == ME_MODE_DISABLE_HAP; + if (HAP_OFFSET != 0) + cse_set_hap_bit(state); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, set_hap_bit, NULL); + /* * Disable the Intel (CS)Management Engine via HECI based on a cmos value * of `me_state`. A value of `0` will result in a (CS)ME state of `0` (working) @@ -1315,37 +1414,71 @@ static void cse_set_state(struct device *dev) int send; int result; + int enable_timeout = 0; /* * Check if the CMOS value "me_state" exists, if it doesn't, then * don't do anything. */ + + const unsigned int efi_me_state = cse_get_me_disable_mode() == ME_MODE_DISABLE_HECI; const unsigned int cmos_me_state = get_uint_option("me_state", UINT_MAX); + unsigned int me_state; - if (cmos_me_state == UINT_MAX) - return; + /* EFI setting takes priority */ + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + me_state = efi_me_state; + else if (CONFIG(USE_OPTION_TABLE)) + me_state = cmos_me_state; + else + me_state = CONFIG_INTEL_ME_DEFAULT_STATE; + + printk(BIOS_DEBUG, "me_state = %u\n", me_state); printk(BIOS_DEBUG, "CMOS: me_state = %u\n", cmos_me_state); + /* + * Skip action while ME is in debug (HAP) mode, as HECI will not work + * in this state + */ + + if (cse_is_hfs1_com_debug()) { + printk(BIOS_DEBUG, "ME is in HAP mode, skipping soft temp disable"); + return; + } + /* * We only take action if the me_state doesn't match the CS(ME) working state */ const unsigned int soft_temp_disable = cse_is_hfs1_com_soft_temp_disable(); - if (cmos_me_state && !soft_temp_disable) { + if (me_state && !soft_temp_disable) { /* me_state should be disabled, but it's enabled */ printk(BIOS_DEBUG, "ME needs to be disabled.\n"); send = heci_send_receive(&me_disable, sizeof(me_disable), &disable_reply, &disable_reply_size, HECI_MKHI_ADDR); result = disable_reply.hdr.result; - } else if (!cmos_me_state && soft_temp_disable) { + } else if (!me_state && soft_temp_disable) { /* me_state should be enabled, but it's disabled */ printk(BIOS_DEBUG, "ME needs to be enabled.\n"); send = heci_send_receive(&me_enable, sizeof(me_enable), &enable_reply, &enable_reply_size, HECI_MKHI_ADDR); result = enable_reply.hdr.result; + + while (1) { + if (cse_is_hfs1_cws_normal()) + break; + + delay(1); + enable_timeout++; + if (enable_timeout > 5) { + printk(BIOS_ERR, "Timeout occurred, ME HFSTS1: %08x\n", + me_read_config32(PCI_ME_HFSTS1)); + break; + } + } } else { - printk(BIOS_DEBUG, "ME is %s.\n", cmos_me_state ? "disabled" : "enabled"); + printk(BIOS_DEBUG, "ME is %s.\n", me_state ? "disabled" : "enabled"); unsigned int cmos_me_state_counter = get_uint_option("me_state_counter", UINT_MAX); /* set me_state_counter to 0 */ @@ -1468,9 +1601,28 @@ static void cse_final(struct device *dev) cse_final_end_of_firmware(); } +#if ENV_RAMSTAGE && !CONFIG(BOARD_NOVACUSTOM_NUC_BOX) +static void heci_read_resources(struct device *dev) +{ + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + if (ENV_X86_32) { + /* Put resource below 4G to ensure coreboot can access it */ + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + res->limit = 0xffffffff; + res->flags &= ~IORESOURCE_ABOVE_4G; + } +} +#endif + struct device_operations cse_ops = { .set_resources = pci_dev_set_resources, +#if !CONFIG(BOARD_NOVACUSTOM_NUC_BOX) + .read_resources = heci_read_resources, +#else .read_resources = pci_dev_read_resources, +#endif .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, .ops_pci = &pci_dev_ops_pci, diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 265fe04bbc4..87254da7b3a 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -131,13 +131,19 @@ static enum cse_cmd_result cse_send_eop(void) * 3) Only sent after DID (accomplished by compiling this into ramstage) */ - if (cse_is_hfs1_com_soft_temp_disable()) { + if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_debug()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) return CSE_CMD_RESULT_ERROR; return CSE_CMD_RESULT_DISABLED; } + if (cse_is_hfs1_com_secover_mei_msg()) { + printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); + /* For CSE Lite this is expected state in update flow, so don't return an error */ + return CSE_CMD_RESULT_DISABLED; + } + if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); return CSE_CMD_RESULT_ERROR; @@ -285,14 +291,16 @@ static bool is_cse_eop_supported(void) /* CSE Lite */ if ((CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled()) && cse_is_hfs1_com_soft_temp_disable()) { - printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE Lite in expected " - "SOFT TEMP DISABLE state, skipping EOP\n"); + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE Lite in expected SOFT TEMP DISABLE state, skipping EOP\n"); return false; } /* Other CSE Type */ if (cse_is_hfs1_com_soft_temp_disable()) { - printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected " - "SOFT TEMP DISABLE state, skipping EOP\n"); + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT TEMP DISABLE state, skipping EOP\n"); + return false; + } + if (cse_is_hfs1_com_debug()) { + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected Debug Mode state, skipping EOP\n"); return false; } diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig index 3a541f861c9..2c59cea2081 100644 --- a/src/soc/intel/common/block/fast_spi/Kconfig +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -52,6 +52,13 @@ config EXT_BIOS_WIN_SIZE region greater than 16MiB. The actual mapped window might be smaller depending upon the size of the BIOS region. +config FAST_SPI_FULL_RO_BOOTMEDIA + bool + default n + help + Make read-only boot device produced by Fast SPI cover the entire + flash chip. + config FAST_SPI_GENERATE_SSDT bool default n diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 45519611ab6..7f698b07e31 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -254,6 +254,16 @@ size_t fast_spi_get_bios_region(size_t *bios_size) bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB; *bios_size = bios_end - bios_start; + + /* + * Optionally extend BIOS region size up to 16 MiB which is the size of fixed map + * window. + */ + if (CONFIG(FAST_SPI_FULL_RO_BOOTMEDIA) && *bios_size < 16 * MiB) { + *bios_size = MIN(16 * MiB, CONFIG_ROM_SIZE); + bios_start = bios_end - *bios_size; + } + return bios_start; } diff --git a/src/soc/intel/common/block/fast_spi/mmap_boot.c b/src/soc/intel/common/block/fast_spi/mmap_boot.c index 2315c44bbde..eb2e889ec1f 100644 --- a/src/soc/intel/common/block/fast_spi/mmap_boot.c +++ b/src/soc/intel/common/block/fast_spi/mmap_boot.c @@ -18,24 +18,59 @@ enum window_type { FIXED_DECODE_WINDOW, /* Additional decode window for mapping BIOS region greater than 16MiB */ EXT_BIOS_DECODE_WINDOW, + + /* Number of memory-backed regions for reading flash */ + TOTAL_MMAP_DECODE_WINDOWS, + + /* + * Maximum number of decode windows. + * + * There is an optional RW window to cover part of the flash preceding IFD BIOS region, + * so `TOTAL_DECODE_WINDOWS` is `TOTAL_MMAP_DECODE_WINDOWS + 1`. + */ TOTAL_DECODE_WINDOWS, }; +static struct mem_region_device mmap_shadow_devs[TOTAL_MMAP_DECODE_WINDOWS]; +static struct xlate_window mmap_windows[TOTAL_MMAP_DECODE_WINDOWS]; + +static struct xlate_window rw_window; + static struct xlate_region_device real_dev; -static struct mem_region_device shadow_devs[TOTAL_DECODE_WINDOWS]; static struct xlate_window real_dev_windows[TOTAL_DECODE_WINDOWS]; +static size_t real_dev_win_count; -static void initialize_window(enum window_type type, uintptr_t host_base, - uintptr_t flash_base, size_t size) +static void append_real_dev_window(const struct xlate_window *w) { - mem_region_device_ro_init(&shadow_devs[type], (void *)host_base, size); - xlate_window_init(&real_dev_windows[type], &shadow_devs[type].rdev, - flash_base, size); + if (real_dev_win_count < ARRAY_SIZE(real_dev_windows)) + real_dev_windows[real_dev_win_count++] = *w; + else + printk(BIOS_CRIT, "Fast SPI BUG: no room to add a window, ignoring it\n"); +} + +static void initialize_mmap_window(enum window_type type, uintptr_t host_base, + uintptr_t flash_base, size_t size) +{ + mem_region_device_ro_init(&mmap_shadow_devs[type], (void *)host_base, size); + xlate_window_init(&mmap_windows[type], &mmap_shadow_devs[type].rdev, flash_base, size); printk(BIOS_INFO, "%s: ", (type == FIXED_DECODE_WINDOW) ? "Fixed Decode Window" : "Extended Decode Window"); printk(BIOS_INFO, "SPI flash base=0x%lx, Host base=0x%lx, Size=0x%zx\n", flash_base, host_base, size); + + append_real_dev_window(&mmap_windows[type]); +} + +static void initialize_rw_window(uintptr_t flash_base, size_t size) +{ + const struct region_device *rw_device = boot_device_rw(); + + xlate_window_init(&rw_window, rw_device, flash_base, size); + printk(BIOS_INFO, "Fast SPI RW Decode Window: SPI flash base=0x%lx, Size=0x%zx\n", + flash_base, size); + + append_real_dev_window(&rw_window); } /* @@ -92,8 +127,6 @@ static void bios_mmap_init(void) uintptr_t ext_win_host_base, ext_win_flash_base; size_t fixed_win_size, ext_win_size; - size_t win_count = 0; - if (init_done) return; @@ -109,9 +142,8 @@ static void bios_mmap_init(void) fixed_win_host_base = 4ULL * GiB - fixed_win_size; fixed_win_flash_base = bios_start + bios_size - fixed_win_size; - initialize_window(FIXED_DECODE_WINDOW, fixed_win_host_base, fixed_win_flash_base, - fixed_win_size); - win_count++; + initialize_mmap_window(FIXED_DECODE_WINDOW, fixed_win_host_base, fixed_win_flash_base, + fixed_win_size); _Static_assert(CONFIG_EXT_BIOS_WIN_BASE != 0, "Extended BIOS window base cannot be 0!"); _Static_assert(CONFIG_EXT_BIOS_WIN_SIZE != 0, "Extended BIOS window size cannot be 0!"); @@ -129,12 +161,23 @@ static void bios_mmap_init(void) ext_win_host_base = CONFIG_EXT_BIOS_WIN_BASE + CONFIG_EXT_BIOS_WIN_SIZE - ext_win_size; ext_win_flash_base = fixed_win_flash_base - ext_win_size; - initialize_window(EXT_BIOS_DECODE_WINDOW, ext_win_host_base, - ext_win_flash_base, ext_win_size); - win_count++; + initialize_mmap_window(EXT_BIOS_DECODE_WINDOW, ext_win_host_base, + ext_win_flash_base, ext_win_size); } - xlate_region_device_ro_init(&real_dev, win_count, real_dev_windows, CONFIG_ROM_SIZE); + /* + * While it's possible to include everything to the start of the flash into extended + * BIOS region, reads of that area always produce 0xFF. Some part of the hardware + * seems to ignore flash's contents outside of IFD BIOS region. + * + * Instead, use RW device as yet another window to allow reading whole flash via + * result of boot_device_ro(). + */ + if (CONFIG(FAST_SPI_FULL_RO_BOOTMEDIA) && bios_start) + initialize_rw_window(0, bios_start); + + xlate_region_device_ro_init(&real_dev, real_dev_win_count, real_dev_windows, + CONFIG_ROM_SIZE); init_done = true; } @@ -148,7 +191,7 @@ const struct region_device *boot_device_ro(void) void fast_spi_get_ext_bios_window(uintptr_t *base, size_t *size) { - const struct region_device *rd = &shadow_devs[EXT_BIOS_DECODE_WINDOW].rdev; + const struct region_device *rd = &mmap_shadow_devs[EXT_BIOS_DECODE_WINDOW].rdev; bios_mmap_init(); @@ -172,14 +215,14 @@ uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) bios_mmap_init(); - for (i = 0; i < TOTAL_DECODE_WINDOWS; i++) { - if (region_sz(&real_dev_windows[i].sub_region) == 0) + for (i = 0; i < TOTAL_MMAP_DECODE_WINDOWS; i++) { + if (region_sz(&mmap_windows[i].sub_region) == 0) continue; count++; - table->flash_base = region_offset(&real_dev_windows[i].sub_region); - table->host_base = (uintptr_t)rdev_mmap_full(&shadow_devs[i].rdev); - table->size = region_sz(&real_dev_windows[i].sub_region); + table->flash_base = region_offset(&mmap_windows[i].sub_region); + table->host_base = (uintptr_t)rdev_mmap_full(&mmap_shadow_devs[i].rdev); + table->size = region_sz(&mmap_windows[i].sub_region); table++; } diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 144e8c30d6e..f24257d6ac4 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -288,6 +288,13 @@ static void graphics_dev_read_resources(struct device *dev) pci_dev_set_resources(dev); res_bar0->flags |= IORESOURCE_FIXED; } + + if (ENV_X86_32 && !CONFIG(BOARD_NOVACUSTOM_NUC_BOX)) { + /* Place framebuffer below 4G to ensure coreboot can access it */ + struct resource *res_bar2 = find_resource(dev, PCI_BASE_ADDRESS_2); + res_bar2->limit = 0xffffffff; + res_bar2->flags &= ~IORESOURCE_ABOVE_4G; + } } static void graphics_join_mbus(void) @@ -459,16 +466,26 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_ADL_N_GT1, PCI_DID_INTEL_ADL_N_GT2, PCI_DID_INTEL_ADL_N_GT3, + PCI_DID_INTEL_ADL_N_GT4, + PCI_DID_INTEL_ADL_N_GT5, PCI_DID_INTEL_RPL_S_GT0, PCI_DID_INTEL_RPL_S_GT1_1, PCI_DID_INTEL_RPL_S_GT1_2, PCI_DID_INTEL_RPL_S_GT1_3, + PCI_DID_INTEL_RPL_S_GT1_4, + PCI_DID_INTEL_RPL_S_GT1_5, PCI_DID_INTEL_RPL_HX_GT1, PCI_DID_INTEL_RPL_HX_GT2, PCI_DID_INTEL_RPL_HX_GT3, PCI_DID_INTEL_RPL_HX_GT4, PCI_DID_INTEL_TWL_GT1_1, PCI_DID_INTEL_TWL_GT1_2, + PCI_DID_INTEL_MTL_M_GT2, + PCI_DID_INTEL_MTL_P_GT2_1, + PCI_DID_INTEL_MTL_P_GT2_2, + PCI_DID_INTEL_MTL_P_GT2_3, + PCI_DID_INTEL_MTL_P_GT2_4, + PCI_DID_INTEL_MTL_P_GT2_5, 0, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 3c2f211d282..12b49fb3364 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -134,6 +134,21 @@ uintptr_t dw_i2c_base_address(unsigned int bus) return (uintptr_t)ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); } +#if !CONFIG(BOARD_NOVACUSTOM_NUC_BOX) +static void dw_i2c_read_resources(struct device *dev) +{ + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + if (ENV_X86_32) { + /* Put resource below 4G to ensure coreboot can access it */ + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + res->limit = 0xffffffff; + res->flags &= ~IORESOURCE_ABOVE_4G; + } +} +#endif + /* * This function ensures that the device is actually out of reset and * its ready for initialization sequence. @@ -161,7 +176,11 @@ static void dw_i2c_device_init(struct device *dev) } struct device_operations i2c_dev_ops = { +#if CONFIG(BOARD_NOVACUSTOM_NUC_BOX) .read_resources = pci_dev_read_resources, +#else + .read_resources = dw_i2c_read_resources, +#endif .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .scan_bus = scan_static_bus, diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index fa320925686..a3f82481c97 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -18,8 +18,21 @@ enum core_type { CPUID_UNKNOWN = 0xff, }; +/* CPU Performance Type */ +enum cpu_perf_eff_type { + CPU_TYPE_EFF, + CPU_TYPE_PERF, +}; + unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current); +/* + * Read the performance and efficient core ratios. + * This is to be implemented by the SoC specific code if + * SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS is selected. + */ +enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient); + /* Generates ACPI code to define _CPC control method */ void acpigen_write_CPPC_hybrid_method(int core_id); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c97e4ec65ce..25aa468d4d5 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -61,6 +61,7 @@ enum mkhi_group_id { /* ME Current Operation Modes */ #define ME_HFS1_COM_NORMAL 0x0 +#define ME_HFS1_COM_DEBUG 0x2 #define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 #define ME_HFS1_COM_SECOVER_MEI_MSG 0x5 @@ -461,6 +462,12 @@ bool cse_is_hfs1_com_normal(void); */ bool cse_is_hfs1_com_secover_mei_msg(void); +/* + * Checks CSE's current operation mode is Debug Mode or not. + * Returns true if CSE's current operation mode is Debug Mode, otherwise false. + */ +bool cse_is_hfs1_com_debug(void); + /* * Checks CSE's current operation mode is Soft Disable Mode or not. * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false. diff --git a/src/soc/intel/common/block/include/intelblocks/me_12.h b/src/soc/intel/common/block/include/intelblocks/me_12.h index 9e9a3c18349..7e4d8c642d7 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_12.h +++ b/src/soc/intel/common/block/include/intelblocks/me_12.h @@ -3,6 +3,15 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_12_H_ #define _SOC_INTEL_COMMON_ME_SPEC_12_H_ +/* HAP bit */ +#if CONFIG(SOC_INTEL_COMETLAKE_1) || CONFIG(SOC_INTEL_COMETLAKE_2) || CONFIG(SOC_INTEL_COMETLAKE_1_2) +#define HAP_OFFSET 0x172 +#elif CONFIG(SOC_INTEL_COMETLAKE_V) +#define HAP_OFFSET 0x102 +#elif CONFIG(SOC_INTEL_COMETLAKE_S) +#define HAP_OFFSET 0x182 +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/me_13.h b/src/soc/intel/common/block/include/intelblocks/me_13.h index 912930d6adc..e7cbb5344a8 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_13.h +++ b/src/soc/intel/common/block/include/intelblocks/me_13.h @@ -3,6 +3,11 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_13_H_ #define _SOC_INTEL_COMMON_ME_SPEC_13_H_ +/* HAP bit */ +#if CONFIG(SOC_INTEL_JASPERLAKE) +#define HAP_OFFSET 0x16A +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/me_15.h b/src/soc/intel/common/block/include/intelblocks/me_15.h index 60fbbae5205..47188fbbc1c 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_15.h +++ b/src/soc/intel/common/block/include/intelblocks/me_15.h @@ -3,6 +3,15 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_15_H_ #define _SOC_INTEL_COMMON_ME_SPEC_15_H_ +/* HAP bit */ +#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) +#define HAP_OFFSET 0x196 +#elif CONFIG(SOC_INTEL_TIGERLAKE) +#define HAP_OFFSET 0x17E +#elif CONFIG(SOC_INTEL_ELKHARTLAKE) +#define HAP_OFFSET 0x186 +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/me_16.h b/src/soc/intel/common/block/include/intelblocks/me_16.h index ef3dbd1b4c0..89dd95ef00d 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_16.h +++ b/src/soc/intel/common/block/include/intelblocks/me_16.h @@ -3,6 +3,13 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_16_H_ #define _SOC_INTEL_COMMON_ME_SPEC_16_H_ +/* HAP bit */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define HAP_OFFSET 0x1DE +#elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define HAP_OFFSET 0x17E +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/me_18.h b/src/soc/intel/common/block/include/intelblocks/me_18.h index b226ebc5019..e32ee958b7b 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_18.h +++ b/src/soc/intel/common/block/include/intelblocks/me_18.h @@ -3,6 +3,10 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_18_H_ #define _SOC_INTEL_COMMON_ME_SPEC_18_H_ +#if CONFIG(SOC_INTEL_METEORLAKE_U_H) +#define HAP_OFFSET 0x21E +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 071be665ea3..0fd1d4ae43f 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -25,6 +25,7 @@ struct __packed global_nvs { u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ u64 hest_log_addr; /* 0x30 - 0x37 err log addr (used in SMM, not ASL code) */ + u8 s0ix; /* 0x38 - Sleep Type (1 = S0IX, 0 = S3) */ }; #endif diff --git a/src/soc/intel/common/block/include/intelblocks/oc_wdt.h b/src/soc/intel/common/block/include/intelblocks/oc_wdt.h index bc0f0b1a27a..f5b50db87a7 100644 --- a/src/soc/intel/common/block/include/intelblocks/oc_wdt.h +++ b/src/soc/intel/common/block/include/intelblocks/oc_wdt.h @@ -5,6 +5,19 @@ #include +/* OC WDT configuration */ +#define PCH_OC_WDT_CTL (ACPI_BASE_ADDRESS + 0x54) +#define PCH_OC_WDT_CTL_RLD BIT(31) +#define PCH_OC_WDT_CTL_ICCSURV_STS BIT(25) +#define PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT(24) +#define PCH_OC_WDT_CTL_SCRATCH_OFFSET 0x10 +#define PCH_OC_WDT_CTL_SCRATCH_MASK (0xFF << PCH_OC_WDT_CTL_SCRATCH_OFFSET) +#define PCH_OC_WDT_CTL_FORCE_ALL BIT(15) +#define PCH_OC_WDT_CTL_EN BIT(14) +#define PCH_OC_WDT_CTL_ICCSURV BIT(13) +#define PCH_OC_WDT_CTL_LCK BIT(12) +#define PCH_OC_WDT_CTL_TOV_MASK 0x3FF + /* Starts and reloads the OC watchdog if enabled in Kconfig */ void setup_oc_wdt(void); diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index d02eaa1352d..ebf4128bcea 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -14,6 +14,7 @@ /* Default power limit value in secs */ #define MOBILE_SKU_PL1_TIME_SEC 28 +#define POWER_LIMIT1_TIME_56_SEC 56 #define MILLIWATTS_TO_WATTS 1000 diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index a3fec18086a..ff78b030759 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -177,15 +177,15 @@ bool ioe_tcss_valid_tbt_auth(void); #define FW_RESET_TIME 50000 /* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 +#define FW_DL_UP_TIME Ones /* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 +#define FW_FLR_RESET_TIME Ones /* Number of microseconds to wait from D3 hot to D0 transition */ #define FW_D3HOT_TO_D0_TIME 50000 /* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 +#define FW_VF_ENABLE_TIME Ones #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/common/block/lpc/Makefile.mk b/src/soc/intel/common/block/lpc/Makefile.mk index b510cd0ec35..60792654b5a 100644 --- a/src/soc/intel/common/block/lpc/Makefile.mk +++ b/src/soc/intel/common/block/lpc/Makefile.mk @@ -5,3 +5,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c + +ifeq ($(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM),y) +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c +endif diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index 385f307a699..9e4c3463109 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -36,5 +36,6 @@ #define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_PCCTL 0xE0 /* PCI Clock Control */ #define LPC_PCCTL_CLKRUN_EN (1 << 0) +#define ESPI_CS1_ENABLE 0xa0 #endif /* _SOC_COMMON_BLOCK_LPC_DEF_H_ */ diff --git a/src/soc/intel/common/block/oc_wdt/Kconfig b/src/soc/intel/common/block/oc_wdt/Kconfig index f0966e0f383..107e3b66e98 100644 --- a/src/soc/intel/common/block/oc_wdt/Kconfig +++ b/src/soc/intel/common/block/oc_wdt/Kconfig @@ -18,7 +18,7 @@ config SOC_INTEL_COMMON_OC_WDT_ENABLE config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS int - depends on SOC_INTEL_COMMON_OC_WDT_ENABLE + depends on SOC_INTEL_COMMON_OC_WDT_ENABLE || SOC_INTEL_COMMON_OC_WDT_WDAT range 70 1024 default 600 help @@ -32,6 +32,7 @@ config SOC_INTEL_COMMON_OC_WDT_RELOAD_IN_PERIODIC_SMI bool "Reload the overclocking watchdog using periodic SMI" depends on SOC_INTEL_COMMON_OC_WDT_ENABLE depends on SOC_INTEL_COMMON_BLOCK_SMM + default n if SOC_INTEL_COMMON_OC_WDT_WDAT default y help Enables Intel chipset Overclocking Watchdog reloading in the periodic @@ -39,3 +40,10 @@ config SOC_INTEL_COMMON_OC_WDT_RELOAD_IN_PERIODIC_SMI unless the OS drivers are installed for this watchdog. If unsure, say Y. + +config SOC_INTEL_COMMON_OC_WDT_WDAT + bool "Expose the overclocking watchdog in ACPI WDAT table" + depends on SOC_INTEL_COMMON_BLOCK_OC_WDT + select ACPI_WDAT_WDT + help + Select this option to expose the OC watchdog in ACPI WDAT tables. diff --git a/src/soc/intel/common/block/oc_wdt/Makefile.mk b/src/soc/intel/common/block/oc_wdt/Makefile.mk index 8f7282a004d..d7bd7746ca2 100644 --- a/src/soc/intel/common/block/oc_wdt/Makefile.mk +++ b/src/soc/intel/common/block/oc_wdt/Makefile.mk @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only all-$(CONFIG_SOC_INTEL_COMMON_BLOCK_OC_WDT) += oc_wdt.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT) += acpi.c + smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_OC_WDT) += oc_wdt.c diff --git a/src/soc/intel/common/block/oc_wdt/acpi.c b/src/soc/intel/common/block/oc_wdt/acpi.c new file mode 100644 index 00000000000..90214842bdf --- /dev/null +++ b/src/soc/intel/common/block/oc_wdt/acpi.c @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +#define OC_WDT_MIN_VALUE 0 +#define OC_WDT_MAX_VALUE 1023 +#define OC_WDT_PERIOD_MS 1000 + +static bool fill_wdat_timeout_entry(acpi_wdat_entry_t *entry) +{ + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = ACPI_WDAT_SET_COUNTDOWN; + entry->instruction = ACPI_WDAT_WRITE_COUNTDOWN | ACPI_WDAT_PRESERVE_REGISTER; + entry->mask = PCH_OC_WDT_CTL_TOV_MASK | PCH_OC_WDT_CTL_ICCSURV_STS + | PCH_OC_WDT_CTL_NO_ICCSURV_STS; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = PCH_OC_WDT_CTL; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_DWORD; + + return true; +} + +static bool fill_wdat_boot_status_entry(acpi_wdat_entry_t *entry, uint8_t action, + uint8_t instruction, uint32_t value, uint32_t mask) +{ + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = action; + entry->instruction = instruction; + entry->value = value; + entry->mask = mask; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = PCH_OC_WDT_CTL; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_DWORD; + + return true; +} + +static bool fill_wdat_run_state_entry(acpi_wdat_entry_t *entry, uint8_t action, + uint8_t instruction, uint32_t value, uint32_t mask) +{ + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = action; + entry->instruction = instruction; + entry->value = value; + entry->mask = mask; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = PCH_OC_WDT_CTL; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_DWORD; + + return true; +} + +static bool fill_wdat_ping_entry(acpi_wdat_entry_t *entry) +{ + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = ACPI_WDAT_RESET; + entry->instruction = ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER; + entry->value = PCH_OC_WDT_CTL_RLD; + entry->mask = + PCH_OC_WDT_CTL_RLD | PCH_OC_WDT_CTL_ICCSURV_STS | PCH_OC_WDT_CTL_NO_ICCSURV_STS; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = PCH_OC_WDT_CTL; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_DWORD; + + return true; +} + +unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) +{ + if (!wdat) + return current; + + wdat->pci_segment = 0xff; + wdat->pci_bus = 0xff; + wdat->pci_device = 0xff; + wdat->pci_function = 0xff; + + wdat->timer_period = OC_WDT_PERIOD_MS; + wdat->min_count = OC_WDT_MIN_VALUE; + wdat->max_count = OC_WDT_MAX_VALUE; + wdat->flags = ACPI_WDAT_FLAG_ENABLED; + wdat->entries = 0; + + acpi_wdat_entry_t *entry = (acpi_wdat_entry_t *)current; + + /* Write countdown */ + if (!fill_wdat_timeout_entry(entry)) + goto out_err; + + entry++; + + /* Get boot status */ + if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_GET_STATUS, ACPI_WDAT_READ_VALUE, + PCH_OC_WDT_CTL_SCRATCH_MASK, + PCH_OC_WDT_CTL_SCRATCH_MASK)) + + goto out_err; + + entry++; + + /* Set boot status */ + if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_SET_STATUS, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, 0, + PCH_OC_WDT_CTL_SCRATCH_MASK + | PCH_OC_WDT_CTL_ICCSURV_STS + | PCH_OC_WDT_CTL_NO_ICCSURV_STS)) + + goto out_err; + + entry++; + + /* Get running status */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_RUNNING_STATE, ACPI_WDAT_READ_VALUE, + PCH_OC_WDT_CTL_EN, PCH_OC_WDT_CTL_EN)) + goto out_err; + + entry++; + + /* Start the watchdog */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_RUNNING_STATE, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, + PCH_OC_WDT_CTL_EN, + PCH_OC_WDT_CTL_EN | PCH_OC_WDT_CTL_ICCSURV_STS + | PCH_OC_WDT_CTL_NO_ICCSURV_STS)) + goto out_err; + + entry++; + + /* Get stopped status */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_STOPPED_STATE, ACPI_WDAT_READ_VALUE, + 0, PCH_OC_WDT_CTL_EN)) + goto out_err; + + entry++; + + /* Stop the watchdog */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_STOPPED_STATE, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, 0, + PCH_OC_WDT_CTL_EN | PCH_OC_WDT_CTL_ICCSURV_STS + | PCH_OC_WDT_CTL_NO_ICCSURV_STS)) + goto out_err; + + entry++; + + /* Ping */ + if (!fill_wdat_ping_entry(entry)) + goto out_err; + + entry++; + + wdat->entries = ((unsigned long)entry - current) / sizeof(acpi_wdat_entry_t); + + return (unsigned long)entry; + +out_err: + wdat->flags = ACPI_WDAT_FLAG_DISABLED; + printk(BIOS_ERR, "Fail to populate WDAT ACPI Table"); + + return current; +} diff --git a/src/soc/intel/common/block/oc_wdt/oc_wdt.c b/src/soc/intel/common/block/oc_wdt/oc_wdt.c index d0f054a074a..d3280a5a9de 100644 --- a/src/soc/intel/common/block/oc_wdt/oc_wdt.c +++ b/src/soc/intel/common/block/oc_wdt/oc_wdt.c @@ -2,21 +2,12 @@ #include #include +#include #include #include #include -/* OC WDT configuration */ -#define PCH_OC_WDT_CTL (ACPI_BASE_ADDRESS + 0x54) -#define PCH_OC_WDT_CTL_RLD BIT(31) -#define PCH_OC_WDT_CTL_ICCSURV_STS BIT(25) -#define PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT(24) -#define PCH_OC_WDT_CTL_FORCE_ALL BIT(15) -#define PCH_OC_WDT_CTL_EN BIT(14) -#define PCH_OC_WDT_CTL_ICCSURV BIT(13) -#define PCH_OC_WDT_CTL_LCK BIT(12) -#define PCH_OC_WDT_CTL_TOV_MASK 0x3FF - +static struct watchdog_config wdt_config; /* * Starts and reloads the OC watchdog with given timeout. * @@ -25,9 +16,7 @@ static void oc_wdt_start(unsigned int timeout) { uint32_t oc_wdt_ctrl; - - if (!CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE)) - return; + bool bootstatus; if ((timeout < 70) || (timeout > (PCH_OC_WDT_CTL_TOV_MASK + 1))) { timeout = CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS; @@ -35,11 +24,19 @@ static void oc_wdt_start(unsigned int timeout) " using config default: %ds\n", timeout); } - printk(BIOS_SPEW, "OC Watchdog: start and relaod timer (timeout %ds)\n", timeout); + printk(BIOS_SPEW, "OC Watchdog: start and reload timer (timeout %ds)\n", timeout); oc_wdt_ctrl = inl(PCH_OC_WDT_CTL); - oc_wdt_ctrl |= (PCH_OC_WDT_CTL_EN | PCH_OC_WDT_CTL_FORCE_ALL | PCH_OC_WDT_CTL_ICCSURV); + bootstatus = !!(oc_wdt_ctrl & (PCH_OC_WDT_CTL_ICCSURV_STS | PCH_OC_WDT_CTL_NO_ICCSURV_STS)); + if (bootstatus) + printk(BIOS_ALERT, "OC Watchdog: Last reset caused by timeout!\n"); + + /* Store bootstatus in scratch register to be consumed by WDAT */ + oc_wdt_ctrl &= ~PCH_OC_WDT_CTL_SCRATCH_MASK; + oc_wdt_ctrl |= bootstatus << PCH_OC_WDT_CTL_SCRATCH_OFFSET; + + oc_wdt_ctrl |= (PCH_OC_WDT_CTL_EN | PCH_OC_WDT_CTL_FORCE_ALL | PCH_OC_WDT_CTL_ICCSURV); oc_wdt_ctrl &= ~PCH_OC_WDT_CTL_TOV_MASK; oc_wdt_ctrl |= (timeout - 1); @@ -91,8 +88,10 @@ unsigned int oc_wdt_get_current_timeout(void) /* Starts and reloads the OC watchdog if enabled in Kconfig */ void setup_oc_wdt(void) { - if (CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE)) { - oc_wdt_start(CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS); + get_watchdog_config(&wdt_config); + + if (wdt_config.wdt_enable) { + oc_wdt_start(wdt_config.wdt_timeout); if (is_oc_wdt_enabled()) printk(BIOS_DEBUG, "OC Watchdog enabled\n"); else diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ddea3b667b4..7a9733c93fa 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -306,6 +306,7 @@ static const unsigned short pcie_device_ids[] = { PCI_DID_INTEL_ADL_P_PCIE_RP1, PCI_DID_INTEL_ADL_P_PCIE_RP2, PCI_DID_INTEL_ADL_P_PCIE_RP3, + PCI_DID_INTEL_ADL_P_PCIE_RP4, PCI_DID_INTEL_ADP_P_PCIE_RP1, PCI_DID_INTEL_ADP_P_PCIE_RP2, PCI_DID_INTEL_ADP_P_PCIE_RP3, diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c index 650da1ff914..8cf48f6513a 100644 --- a/src/soc/intel/common/block/pcie/pcie_rp.c +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -117,7 +117,10 @@ static bool pcie_rp_update_dev( printk(BIOS_NOTICE, "%s: Couldn't find PCIe Root Port #%u " "(originally %s) which was enabled in devicetree, removing and disabling.\n", __func__, rp_idx + 1, dev_path(dev)); + /* Disable the dev and its children if not present */ dev->enabled = 0; + if (dev->downstream) + disable_children(dev->downstream); } return true; } else if (PCI_FUNC(dev->path.pci.devfn) != new_fn) { diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 3a7c8b4afcb..8cf67ff7331 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -533,7 +534,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) acpigen_write_device(acpi_device_name(dev)); acpigen_write_ADR(0); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); - if (CONFIG(D3COLD_SUPPORT)) + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S0IX) acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); else acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); @@ -543,7 +544,13 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) acpigen_pop_len(); /* Device */ printk(BIOS_INFO, "%s: Added StorageD3Enable property\n", scope); - } + } else { + /* Write the device to make PEP happy */ + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_ADR(0); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_pop_len(); /* Device */ + } acpigen_pop_len(); /* Scope */ } diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 0fadd6e4096..2a79b3fcae8 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -760,8 +761,7 @@ void pmc_clear_pmcon_sts(void) void pmc_set_power_failure_state(const bool target_on) { - const unsigned int state = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); + const unsigned int state = dasharo_get_power_on_after_fail(); /* * On the shutdown path (target_on == false), we only need to diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig index 31bef05f717..30f403840ea 100644 --- a/src/soc/intel/common/block/smbus/Kconfig +++ b/src/soc/intel/common/block/smbus/Kconfig @@ -19,3 +19,10 @@ config SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS depends on SOC_INTEL_COMMON_BLOCK_TCO help Select this config to enable TCO BAR through SMBUS + +config SOC_INTEL_COMMON_BLOCK_TCO_WDT_WDAT + bool + depends on SOC_INTEL_COMMON_BLOCK_TCO + select ACPI_WDAT_WDT + help + Select this option to expose the TCO watchdog in ACPI WDAT tables. diff --git a/src/soc/intel/common/block/smbus/Makefile.mk b/src/soc/intel/common/block/smbus/Makefile.mk index 2ef3a5b752d..9c16f56d123 100644 --- a/src/soc/intel/common/block/smbus/Makefile.mk +++ b/src/soc/intel/common/block/smbus/Makefile.mk @@ -9,6 +9,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_WDT_WDAT) += acpi.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c diff --git a/src/soc/intel/common/block/smbus/acpi.c b/src/soc/intel/common/block/smbus/acpi.c new file mode 100644 index 00000000000..0389380f89a --- /dev/null +++ b/src/soc/intel/common/block/smbus/acpi.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static bool fill_wdat_timeout_entry(acpi_wdat_entry_t *entry) +{ + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + return false; + + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = ACPI_WDAT_SET_COUNTDOWN; + entry->instruction = ACPI_WDAT_WRITE_COUNTDOWN | ACPI_WDAT_PRESERVE_REGISTER; + entry->mask = TCO_TMR_MASK; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = tcobase + TCO_TMR; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + + return true; +} + +static bool fill_wdat_boot_status_entry(acpi_wdat_entry_t *entry, uint8_t action, + uint8_t instruction, uint32_t value) +{ + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + return false; + + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = action; + entry->instruction = instruction; + entry->value = value; + entry->mask = TCO2_STS_SECOND_TO; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = tcobase + TCO_MESSAGE1; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_BYTE; + + return true; +} + +static bool fill_wdat_run_state_entry(acpi_wdat_entry_t *entry, uint8_t action, + uint8_t instruction, uint32_t value) +{ + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + return false; + + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = action; + entry->instruction = instruction; + entry->value = value; + entry->mask = TCO1_TMR_HLT; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = tcobase + TCO1_CNT; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + + return true; +} + +static bool fill_wdat_ping_entry(acpi_wdat_entry_t *entry) +{ + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + return false; + + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = ACPI_WDAT_RESET; + entry->instruction = ACPI_WDAT_WRITE_VALUE; + entry->value = 0x01; + entry->mask = 0x01; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = tcobase + TCO_RLD; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + + return true; +} + +unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) +{ + if (!wdat) + return current; + + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + goto out_err; + + wdat->pci_segment = 0xff; + wdat->pci_bus = 0xff; + wdat->pci_device = 0xff; + wdat->pci_function = 0xff; + + wdat->timer_period = tco_get_timer_period(); + wdat->min_count = tco_get_timer_min_value(); + wdat->max_count = tco_get_timer_max_value(); + wdat->flags = ACPI_WDAT_FLAG_ENABLED; + wdat->entries = 0; + + acpi_wdat_entry_t *entry = (acpi_wdat_entry_t *)current; + + /* Write countdown */ + if (!fill_wdat_timeout_entry(entry)) + goto out_err; + + entry++; + + /* Get boot status */ + if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_GET_STATUS, + ACPI_WDAT_READ_VALUE, TCO2_STS_SECOND_TO)) + goto out_err; + + entry++; + + /* Set boot status */ + if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_SET_STATUS, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, + 0)) + goto out_err; + + entry++; + + /* Get running status */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_RUNNING_STATE, + ACPI_WDAT_READ_VALUE, 0)) + goto out_err; + + entry++; + + /* Start the watchdog */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_RUNNING_STATE, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, + 0)) + goto out_err; + + entry++; + + /* Get stopped status */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_STOPPED_STATE, + ACPI_WDAT_READ_VALUE, TCO1_TMR_HLT)) + goto out_err; + + entry++; + + /* Stop the watchdog */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_STOPPED_STATE, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, + TCO1_TMR_HLT)) + goto out_err; + + entry++; + + /* Ping */ + if (!fill_wdat_ping_entry(entry)) + goto out_err; + + entry++; + + wdat->entries = ((unsigned long)entry - current) / sizeof(acpi_wdat_entry_t); + + return (unsigned long)entry; + +out_err: + wdat->flags = ACPI_WDAT_FLAG_DISABLED; + printk(BIOS_ERR, "Fail to populate WDAT ACPI Table"); + + return current; +} diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index cf60e64c1d4..3bd1cc57a51 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -13,8 +13,11 @@ static void update_spd_len(struct spd_block *blk) if (blk->spd_array[i] != NULL) j |= blk->spd_array[i][SPD_DRAM_TYPE]; + /* If spd used is DDR5, then its length is 1024 byte. */ + if (j == SPD_DRAM_DDR5) + blk->len = SPD_LEN_DDR5; /* If spd used is DDR4, then its length is 512 byte. */ - if (j == SPD_DRAM_DDR4) + else if (j == SPD_DRAM_DDR4) blk->len = SPD_PAGE_LEN_DDR4; else blk->len = SPD_PAGE_LEN; @@ -37,6 +40,58 @@ static void spd_read(u8 *spd, u8 addr) } } +static void switch_page(u8 spd_addr, u8 new_page) +{ + /* + * By default, an SPD5 hub accepts 1 byte addressing pointing + * to the first 128 bytes of memory. MR11[2:0] selects the page + * pointer to address the entire 1024 bytes of non-volatile memory. + */ + smbus_write_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR11), new_page); +} + +/* + * Read the SPD data over the SMBus, at the specified SPD address, + * starting at the specified starting offset and read the given amount of data. + */ +static void smbus_read_spd5(u8 *spd, u8 spd_addr, u16 size) +{ + u8 page = ~0; + u32 max_page_size = MAX_SPD_PAGE_SIZE_SPD5; + + if (size > MAX_SPD_SIZE) { + printk(BIOS_ERR, "Maximum SPD size reached\n"); + return; + } + for (int i = 0; i < size; i++) { + u8 next_page = (u8) (i / max_page_size); + if (next_page != page) { + switch_page(spd_addr, next_page); + page = next_page; + } + unsigned int byte_addr = SPD_HUB_MEMREG(i % max_page_size); + spd[i] = smbus_read_byte(spd_addr, byte_addr); + } +} + +/* Read SPD5 MR0 and check if SPD Byte 0 matches the SPD5 HUB MR0 identifier.*/ +static int is_spd5_hub(u8 spd_addr) +{ + u8 spd_hub_byte; + + spd_hub_byte = smbus_read_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR0)); + return spd_hub_byte == SPD5_MR0_SPD5_HUB_DEV; +} + +/* + * Reset the SPD page back to page 0 on an SPD5 Hub device at the + * input SPD SMbus address. + */ +static void reset_page_spd5(u8 spd_addr) +{ + switch_page(spd_addr, 0); +} + /* return -1 if SMBus errors otherwise return 0 */ static int get_spd(u8 *spd, u8 addr) { @@ -52,26 +107,34 @@ static int get_spd(u8 *spd, u8 addr) return -1; } - /* IMC doesn't support i2c eeprom read. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) || - i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { - printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - spd_read(spd, addr); - } - - /* Check if module is DDR4, DDR4 spd is 512 byte. */ - if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { - /* Switch to page 1 */ - spd_write_byte(SPD_PAGE_1, 0, 0); + if (is_spd5_hub(addr)) { + smbus_read_spd5(spd, addr, SPD_LEN_DDR5); + /* Reset the page for the next loop iteration */ + reset_page_spd5(addr); + } else { /* IMC doesn't support i2c eeprom read. */ if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) || - i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - spd_read(spd + SPD_PAGE_LEN, addr); + spd_read(spd, addr); + } + + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { + /* Switch to page 1 */ + smbus_write_byte(SPD_PAGE_1, 0, 0); + + /* IMC doesn't support i2c eeprom read. */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) || + i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); + spd_read(spd + SPD_PAGE_LEN, addr); + } + /* Restore to page 0 */ + smbus_write_byte(SPD_PAGE_0, 0, 0); } - /* Restore to page 0 */ - spd_write_byte(SPD_PAGE_0, 0, 0); } return 0; } diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index 84c406ef3e0..fe23172558d 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -55,3 +55,12 @@ config PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B Intel Core processors select the periodic SMI rate via GEN_PMCON_A. On Intel Atom processors the register is different and they use GEN_PMCON_B/GEN_PMCON2 with different address. + +config SOC_INTEL_COMMON_BLOCK_SMM_NO_MSR_SPCL_CHIPSET_USAGE + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + Intel Core processors write the MSR_SPCL_CHIPSET_USAGE to allow + writes to the BIOS region when EISS is enabled. Some processors + may not have this MSR. If so, select this option. diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 59489a4f037..65a15b09649 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -9,17 +9,20 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -275,7 +278,8 @@ static void set_insmm_sts(const bool enable_writes) else msr.lo &= ~1; - wrmsr(MSR_SPCL_CHIPSET_USAGE, msr); + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_NO_MSR_SPCL_CHIPSET_USAGE)) + wrmsr(MSR_SPCL_CHIPSET_USAGE, msr); } static void southbridge_smi_store( @@ -345,11 +349,19 @@ static void finalize(void) } finalize_done = 1; + if (CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) { + /* SPI lock down configuration */ + fast_spi_lockdown_bios(CHIPSET_LOCKDOWN_COREBOOT); + + /* LPC/eSPI lock down configuration */ + lpc_lockdown_config(CHIPSET_LOCKDOWN_COREBOOT); + } + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ fast_spi_init(); - if (CONFIG(BOOTMEDIA_SMM_BWP)) { + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) { fast_spi_enable_wp(); set_insmm_sts(false); } @@ -440,7 +452,7 @@ void smihandler_southbridge_tco( fast_spi_clear_sync_smi_status(); /* If enabled, enforce SMM BIOS write protection */ - if (CONFIG(BOOTMEDIA_SMM_BWP) && fast_spi_wpd_status()) { + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted() && fast_spi_wpd_status()) { /* * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 098c3c4385b..a8a8fde9f2e 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -551,6 +551,7 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_RPL_S_ID_3, PCI_DID_INTEL_RPL_S_ID_4, PCI_DID_INTEL_RPL_S_ID_5, + PCI_DID_INTEL_RPL_S_ID_6, PCI_DID_INTEL_RPL_P_ID_1, PCI_DID_INTEL_RPL_P_ID_2, PCI_DID_INTEL_RPL_P_ID_3, diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index ff898abb125..d3bfa918270 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -10,6 +10,7 @@ #define INTEL_TBT_IMR_VALID_UUID "C44D002F-69F9-4E7D-A904-A7BAABDF43F7" #define INTEL_TBT_WAKE_SUPPORTED_UUID "6C501103-C189-4296-BA72-9BF5A26EBE5D" +#define INTEL_TBT_PCIE_SUPPORTED_UUID "197DB5E0-F095-4F33-B915-71DD70833E55" #if CONFIG(HAVE_ACPI_TABLES) static const char *tbt_dma_acpi_name(const struct device *dev) @@ -24,6 +25,51 @@ static const char *tbt_dma_acpi_name(const struct device *dev) } } +static bool tbt_pcie_enabled(struct device *tbt_pcie) +{ + return (tbt_pcie && tbt_pcie->enabled); +} + +static void tbt_pcie_ports_present(void *arg) +{ + uint8_t tbt0_bitmask, tbt1_bitmask; + + tbt0_bitmask = tbt_pcie_enabled(SA_DEV_TBT0) | (tbt_pcie_enabled(SA_DEV_TBT1) << 1); + tbt1_bitmask = tbt_pcie_enabled(SA_DEV_TBT2) | (tbt_pcie_enabled(SA_DEV_TBT3) << 1); + + /* Name (PCPN, Buffer (1) {0}) */ + acpigen_write_name("PCPN"); + acpigen_emit_byte(BUFFER_OP); + acpigen_write_len_f(); + acpigen_emit_byte(1); + acpigen_emit_byte(0); + acpigen_pop_len(); + + /* If DUID == 1 set TBT0/TBT1 bitmask, else set TBT2/TBT3 bitmask */ + acpigen_write_if_lequal_namestr_int("DUID", 0); + acpigen_write_store_int_to_namestr(tbt0_bitmask, "PCPN"); + acpigen_write_else(); + acpigen_write_store_int_to_namestr(tbt1_bitmask, "PCPN"); + acpigen_write_if_end(); + + acpigen_write_return_namestr("PCPN"); +} + +static void tbt_dma_caps_info(void *arg) +{ + /* + * Bit0 is IMR_VALID, bit1 is WAKE_SUPPORTED, bit2 is vPro Dock supported. + * We hardcode both IMR_VALID and WAKE_SUPPORTED to 1. + */ + acpigen_write_return_singleton_buffer(3); +} + +static void (*tbt_pcie_helpers[])(void *) = { + NULL, /* enumerate functions (autogenerated) */ + tbt_pcie_ports_present, /* Return supported TBT PCIe */ + tbt_dma_caps_info, /* Return supported TBT DMA capabilities */ +}; + static void tbt_dma_fill_ssdt(const struct device *dev) { struct acpi_dp *dsd, *pkg; @@ -47,6 +93,11 @@ static void tbt_dma_fill_ssdt(const struct device *dev) acpi_dp_add_package(dsd, pkg); acpi_dp_write(dsd); + acpigen_write_dsm(INTEL_TBT_PCIE_SUPPORTED_UUID, + tbt_pcie_helpers, + ARRAY_SIZE(tbt_pcie_helpers), + NULL); + acpigen_pop_len(); /* Scope */ } #endif diff --git a/src/soc/intel/common/block/vtd/vtd.c b/src/soc/intel/common/block/vtd/vtd.c index 12ca151c7af..edaa1d2098c 100644 --- a/src/soc/intel/common/block/vtd/vtd.c +++ b/src/soc/intel/common/block/vtd/vtd.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -251,6 +252,11 @@ void vtd_enable_dma_protection(void) if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) return; + if (!dma_protection_enabled()) { + printk(BIOS_INFO, "VT-d DMA protection disabled by option\n"); + return; + } + vtd_engine_enable_dma_protection(VTVC0_BASE_ADDRESS); /* * FIXME: GFX VT-d will fail to set PMR (tested on ADL-S). diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h index b5aba06fe0e..1b96f41a2a4 100644 --- a/src/soc/intel/common/pch/include/intelpch/lockdown.h +++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h @@ -22,4 +22,7 @@ int get_lockdown_config(void); */ void soc_lockdown_config(int chipset_lockdown); +void fast_spi_lockdown_bios(int chipset_lockdown); +void lpc_lockdown_config(int chipset_lockdown); + #endif /* SOC_INTEL_COMMON_PCH_LOCKDOWN_H */ diff --git a/src/soc/intel/common/pch/lockdown/Kconfig b/src/soc/intel/common/pch/lockdown/Kconfig index 38f60d20569..545185c52f2 100644 --- a/src/soc/intel/common/pch/lockdown/Kconfig +++ b/src/soc/intel/common/pch/lockdown/Kconfig @@ -3,7 +3,22 @@ config SOC_INTEL_COMMON_PCH_LOCKDOWN bool default n + select HAVE_INTEL_CHIPSET_LOCKDOWN help This option allows to have chipset lockdown for DMI, FAST_SPI and soc_lockdown_config() to implement any additional lockdown as PMC, LPC for supported PCH. + +config SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM + bool "Lock down SPI controller in SMM" + default n + depends on HAVE_SMI_HANDLER && !INTEL_CHIPSET_LOCKDOWN + select SPI_FLASH_SMM + help + This option allows to have chipset lockdown for FAST_SPI and LPC for + supported PCH. If selected, coreboot will skip locking down the SPI + and LPC controller. The payload or OS is responsible for locking it + using APM_CNT_FINALIZE SMI. Used by heads to set and lock PR0 flash + protection. + + If unsure, say N. diff --git a/src/soc/intel/common/pch/lockdown/Makefile.mk b/src/soc/intel/common/pch/lockdown/Makefile.mk index 71466f8edd1..64aad562acf 100644 --- a/src/soc/intel/common/pch/lockdown/Makefile.mk +++ b/src/soc/intel/common/pch/lockdown/Makefile.mk @@ -1,2 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_lpc.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_spi.c + +smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_lpc.c +smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_spi.c diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index eec3beb01b4..2d229e1a90a 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -60,56 +60,17 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown) /* Set FAST_SPI opcode menu */ fast_spi_set_opcode_menu(); - /* Discrete Lock Flash PR registers */ - fast_spi_pr_dlock(); - /* Check if SPI transaction is pending */ fast_spi_cycle_in_progress(); /* Clear any outstanding status bits like AEL, FCERR, FDONE, SAF etc. */ fast_spi_clear_outstanding_status(); - /* Lock FAST_SPIBAR */ - fast_spi_lock_bar(); - /* Set Vendor Component Lock (VCL) */ fast_spi_vscc0_lock(); - /* Set BIOS Interface Lock, BIOS Lock */ - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* BIOS Interface Lock */ - fast_spi_set_bios_interface_lock_down(); - - /* Only allow writes in SMM */ - if (CONFIG(BOOTMEDIA_SMM_BWP)) { - fast_spi_set_eiss(); - fast_spi_enable_wp(); - } - - /* BIOS Lock */ - fast_spi_set_lock_enable(); - - /* EXT BIOS Lock */ - fast_spi_set_ext_bios_lock_enable(); - } -} - -static void lpc_lockdown_config(int chipset_lockdown) -{ - /* Set BIOS Interface Lock, BIOS Lock */ - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* BIOS Interface Lock */ - lpc_set_bios_interface_lock_down(); - - /* Only allow writes in SMM */ - if (CONFIG(BOOTMEDIA_SMM_BWP)) { - lpc_set_eiss(); - lpc_enable_wp(); - } - - /* BIOS Lock */ - lpc_set_lock_enable(); - } + if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) + fast_spi_lockdown_bios(chipset_lockdown); } static void sa_lockdown_config(int chipset_lockdown) @@ -135,8 +96,9 @@ static void platform_lockdown_config(void *unused) /* SPI lock down configuration */ fast_spi_lockdown_cfg(chipset_lockdown); - /* LPC/eSPI lock down configuration */ - lpc_lockdown_config(chipset_lockdown); + if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) + /* LPC/eSPI lock down configuration */ + lpc_lockdown_config(chipset_lockdown); /* GPMR lock down configuration */ gpmr_lockdown_cfg(); diff --git a/src/soc/intel/common/pch/lockdown/lockdown_lpc.c b/src/soc/intel/common/pch/lockdown/lockdown_lpc.c new file mode 100644 index 00000000000..79a27d520f3 --- /dev/null +++ b/src/soc/intel/common/pch/lockdown/lockdown_lpc.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void lpc_lockdown_config(int chipset_lockdown) +{ + /* Set BIOS Interface Lock, BIOS Lock */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* BIOS Interface Lock */ + lpc_set_bios_interface_lock_down(); + + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) { + lpc_set_eiss(); + lpc_enable_wp(); + } + + /* BIOS Lock */ + lpc_set_lock_enable(); + } +} diff --git a/src/soc/intel/common/pch/lockdown/lockdown_spi.c b/src/soc/intel/common/pch/lockdown/lockdown_spi.c new file mode 100644 index 00000000000..0815a370bf0 --- /dev/null +++ b/src/soc/intel/common/pch/lockdown/lockdown_spi.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void fast_spi_lockdown_bios(int chipset_lockdown) +{ + /* Discrete Lock Flash PR registers */ + fast_spi_pr_dlock(); + + /* Lock FAST_SPIBAR */ + fast_spi_lock_bar(); + + /* Set BIOS Interface Lock, BIOS Lock */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* BIOS Interface Lock */ + fast_spi_set_bios_interface_lock_down(); + + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) { + fast_spi_set_eiss(); + fast_spi_enable_wp(); + } + + /* BIOS Lock */ + fast_spi_set_lock_enable(); + + /* EXT BIOS Lock */ + fast_spi_set_ext_bios_lock_enable(); + } +} diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7dc971ea92a..c4f7681c621 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -536,7 +536,8 @@ static const struct pci_driver lpc_driver __pci_driver = { static void finalize_chipset(void *unused) { - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index ff3c82f6ff1..7abdde014d6 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -15,6 +15,7 @@ config SOC_INTEL_ELKHARTLAKE select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP + select HAVE_INTEL_ME_HAP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM @@ -47,6 +48,7 @@ config SOC_INTEL_ELKHARTLAKE select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 + select SOC_INTEL_COMMON_BLOCK_OC_WDT select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA @@ -256,4 +258,7 @@ config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN config DIMM_SPD_SIZE default 512 +config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS + default 300 + endif diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index 275413b4efa..3fcc29e2a13 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -33,8 +33,16 @@ static void pch_finalize(void) static void heci_finalize(void) { + bool heci_disable = false; + heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + + if (is_cse_enabled()) { + heci_disable = cse_is_hfs1_com_debug() || + cse_is_hfs1_com_soft_temp_disable(); + } + + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || heci_disable) heci1_disable(); } @@ -43,7 +51,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) heci_finalize(); diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 7b715f83d9a..6274cf3a59c 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -448,7 +449,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* TccActivationOffset config */ - params->TccActivationOffset = config->tcc_offset; + params->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); params->TccOffsetClamp = config->tcc_offset_clamp; params->TccOffsetLock = 0x1; //lock Tcc Offset register diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index d05a94d2aad..ecdb2246e49 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -99,9 +100,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Processor Early Power On Configuration FCLK setting */ m_cfg->FClkFrequency = 0x1; - /* Ib-Band ECC configuration */ - if (config->ibecc.enable) { - m_cfg->Ibecc = !!config->ibecc.enable; + /* In-Band ECC configuration */ + if (get_ibecc_option(config->ibecc.enable)) { + m_cfg->Ibecc = 1; m_cfg->IbeccParity = !!config->ibecc.parity_en; m_cfg->IbeccOperationMode = config->ibecc.mode; if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) { diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 3dfb7c247dc..8b89406024f 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -128,6 +129,8 @@ void mainboard_romstage_entry(void) bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + setup_oc_wdt(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 3fd6826e121..48a247f38e6 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -16,6 +16,7 @@ config SOC_INTEL_JASPERLAKE select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_DPTF_EISA_HID + select HAVE_INTEL_ME_HAP select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER @@ -48,6 +49,7 @@ config SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 + select SOC_INTEL_COMMON_BLOCK_OC_WDT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM @@ -206,4 +208,8 @@ config INTEL_GMA_BCLM_OFFSET config INTEL_GMA_BCLM_WIDTH default 32 + +config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS + default 300 + endif diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl index 648cb416613..8c846399d59 100644 --- a/src/soc/intel/jasperlake/acpi/pmc.asl +++ b/src/soc/intel/jasperlake/acpi/pmc.asl @@ -8,6 +8,7 @@ Scope (\_SB.PCI0) { { Name (_HID, "INTC1026") Name (_DDN, "Intel(R) Jasper Lake IPC Controller") + Name (_STA, 0xB) /* * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index e3214c9054d..d783b0e634e 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -24,12 +24,12 @@ static struct { u16 mchid; const char *name; } mch_table[] = { - { PCI_DID_INTEL_JSL_ID_1, "Jasperlake SKU4-1" }, - { PCI_DID_INTEL_JSL_ID_2, "Jasperlake SKU4-2" }, - { PCI_DID_INTEL_JSL_ID_3, "Jasperlake SKU2-1" }, - { PCI_DID_INTEL_JSL_ID_4, "Jasperlake SKU2-2" }, - { PCI_DID_INTEL_JSL_ID_5, "Jasperlake SKU4-3" }, - { PCI_DID_INTEL_JSL_ID_6, "Jasperlake SKU4-3" }, + { PCI_DID_INTEL_JSL_ID_1, "Jasperlake N4500" }, + { PCI_DID_INTEL_JSL_ID_2, "Jasperlake N6000" }, + { PCI_DID_INTEL_JSL_ID_3, "Jasperlake N5100" }, + { PCI_DID_INTEL_JSL_ID_4, "Jasperlake N4505" }, + { PCI_DID_INTEL_JSL_ID_5, "Jasperlake N5105" }, + { PCI_DID_INTEL_JSL_ID_6, "Jasperlake N6005" }, }; static struct { diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 8788db155d6..4840c0c04c5 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -76,7 +76,8 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); /* Indicate finalize step with post code */ post_code(POSTCODE_OS_BOOT); diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 3bad5334240..d2583aefabc 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include #include +#include #include #include #include @@ -177,8 +178,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable Processor Thermal Control */ params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); + params->GnaEnable = is_devfn_enabled(SA_DEVFN_GNA); + /* Set TccActivationOffset */ - params->TccActivationOffset = config->tcc_offset; + params->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); /* eMMC configuration */ params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 787eb77c913..dd6c4f369ab 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -128,6 +129,8 @@ void mainboard_romstage_entry(void) bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + setup_oc_wdt(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 73d68df2969..f41452a23d5 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -28,6 +28,7 @@ config SOC_INTEL_METEORLAKE select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP select HAVE_HYPERTHREADING select HAVE_INTEL_COMPLIANCE_TEST_MODE + select HAVE_INTEL_ME_HAP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -36,6 +37,7 @@ config SOC_INTEL_METEORLAKE select INTEL_GMA_OPREGION_2_1 select INTEL_GMA_VERSION_2 select IOAPIC + select INTEL_TXT_LIB select MP_SERVICES_PPI_V2 select MRC_CACHE_USING_MRC_VERSION select MRC_SETTINGS_PROTECT @@ -81,10 +83,11 @@ config SOC_INTEL_METEORLAKE select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC + select SOC_INTEL_COMMON_BLOCK_VTD select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if CHROMEOS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET @@ -158,6 +161,10 @@ config MAX_CPUS int default 22 +config CPU_MAX_TEMPERATURE + int + default 110 + config DCACHE_RAM_BASE default 0xfef00000 @@ -317,7 +324,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL default 0x7fff config VBOOT - select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS @@ -449,4 +455,29 @@ config SOC_PHYSICAL_ADDRESS_WIDTH int default 42 +config INTEL_GMA_BCLV_OFFSET + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 + +if INTEL_TXT + +config INTEL_TXT_DPR_SIZE + default 4 + +config INTEL_TXT_SINIT_SIZE + default 0x50000 + +config INTEL_TXT_HEAP_SIZE + default 0xf0000 + +endif + endif diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk index f3dce871318..9276b8a2b5e 100644 --- a/src/soc/intel/meteorlake/Makefile.mk +++ b/src/soc/intel/meteorlake/Makefile.mk @@ -60,6 +60,9 @@ smm-y += xhci.c CPPFLAGS_common += -I$(src)/soc/intel/meteorlake CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include +# Include the missing MemInfoHob.h from vendorcode +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/meteorlake + ifeq ($(CONFIG_SOC_INTEL_METEORLAKE_U_H),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-aa-04 endif diff --git a/src/soc/intel/meteorlake/acpi/pcie.asl b/src/soc/intel/meteorlake/acpi/pcie.asl index 386a57d26c0..889889cffdb 100644 --- a/src/soc/intel/meteorlake/acpi/pcie.asl +++ b/src/soc/intel/meteorlake/acpi/pcie.asl @@ -296,6 +296,16 @@ Device (RP12) Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (1)) } } + +Device (SRAM) +{ + Name (_ADR, 0x00140002) +} + +Device (HEC1) +{ + Name (_ADR, 0x00160000) +} diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index 24d28f3b63d..1c91160c5c3 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -135,6 +135,23 @@ Scope (\_SB) Return (0) } + Method (TCWK, 1, NotSerialized) { + If (Arg0 == 3 || Arg0 == 4) { + If (LNotEqual (\_SB.PCI0.TRP0.VDID,0xFFFFFFFF)) { + Notify (\_SB.PCI0.TRP0, 0) + } + If (LNotEqual (\_SB.PCI0.TRP1.VDID,0xFFFFFFFF)) { + Notify (\_SB.PCI0.TRP1, 0) + } + If (LNotEqual (\_SB.PCI0.TRP2.VDID,0xFFFFFFFF)) { + Notify (\_SB.PCI0.TRP2, 0) + } + If (LNotEqual (\_SB.PCI0.TRP3.VDID,0xFFFFFFFF)) { + Notify (\_SB.PCI0.TRP3, 0) + } + } + } + Method (_OSC, 4, Serialized) { CreateDWordField (Arg3, 0, CDW1) @@ -319,6 +336,13 @@ Scope (_GPE) \_SB.PCI0.TRP2.HPME() \_SB.PCI0.TRP3.HPME() } + + Method (_L71, 0, Serialized) + { + \_SB.PCI0.IMNG (0x71) + } + + Method (_L73, 0 , Serialized) { } } Scope (\_SB.PCI0) @@ -405,11 +429,66 @@ Scope (\_SB.PCI0) TACK, 1, /* [16:16] IOM Acknowledge bit */ DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ /* display is OFF, clear otherwise */ + Offset (0x44), /* SW_CONFIG_2 */ + DPHD, 1, /* [0:0] DP_ALT and DP Tunneling HPD assertion. */ + Offset (0x48), /* SW_CONFIG_3 */ + , 12, + INDP, 1, /* [12:12] The capability of monitoring the DP_ALT and DP tunneling. */ Offset(0x70), /* Physical addr is offset 0x70. */ IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ } + Name (IGFG, 0) /* Internal Monitor On/Off Flag. 1 - Off, 0 - On */ + /* Notify iGfx when HPD_ASSERT with DP_ALT/DP tunneling. */ + Method (IMNG, 1) + { + Switch (ToInteger (Arg0)) { + Case (0) { + /* Clear IOM_TYPEC_SW_CONFIGURATION_2 BIT0 to 0 while BIOS detect BIT0 is 1 */ + If (INDP == 1) { + /* + * Set Internal Monitor off flag for skipping notification + * to iGfx after PEP Fun#3 Display off notification. + */ + IGFG = 1 + } + If (DPHD == 1) { + DPHD = 0 /* Clear IOM HPD indication. */ + } + } + Case (1) { + /* Clear IOM_TYPEC_SW_CONFIGURATION_2 BIT0 to 0 and notify IGD for device scan */ + If (INDP == 1) { + /* + * Clear the internal monitor off flag for enabling + * _L71 notification to iGfx when iGfx is in D3 hot. + */ + IGFG = 0 + } + If (DPHD == 1) { + DPHD = 0 /* Clear IOM HPD indication. */ + } + } + /* _L71 using condition */ + Case (0x71) { + Local0 = 0xF + If (CondRefOf (\_SB.PCI0.GFX0.GFPS)) { + Local0 = \_SB.PCI0.GFX0.GFPS () + } + If (IGFG == 0) { + /* + * Notify iGfx when the capability bit of monitoring DP_ALT and + * DP tunneling is set and iGfx is in D3 hot. + */ + If (INDP == 1 && Local0 == 3) { + Notify (\_SB.PCI0.GFX0, 0) + } + } + } + } + } + /* * TBT Group0 ON method */ @@ -818,3 +897,17 @@ Scope (\_SB.PCI0) #include "tcss_pcierp.asl" } } + +Scope (\_SB.PCI0.GFX0) +{ + OperationRegion (PXCS, PCI_Config, 0xd4, 4) + Field (PXCS, AnyAcc, NoLock, Preserve) { + D3HT, 2, // PowerState + } + + Method (GFPS,0,Serialized) + { + + Return (D3HT) + } +} diff --git a/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl b/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl index 4ae13768589..7144827e614 100644 --- a/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl @@ -345,3 +345,14 @@ Method (HPME, 0, Serialized) } Return (0x00) } + +Name (AR01, Package () { + Package () {0x0000FFFF, 0, 0, 16 }, + Package () {0x0000FFFF, 1, 0, 17 }, + Package () {0x0000FFFF, 2, 0, 18 }, + Package () {0x0000FFFF, 3, 0, 19 }, +}) + +Method (_PRT, 0, NotSerialized) { + Return (AR01) +} diff --git a/src/soc/intel/meteorlake/acpi/tcss_xhci.asl b/src/soc/intel/meteorlake/acpi/tcss_xhci.asl index ddc5a6665dc..7b62334f69c 100644 --- a/src/soc/intel/meteorlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/meteorlake/acpi/tcss_xhci.asl @@ -111,10 +111,61 @@ Device (RHUB) { Name (_ADR, 0) + Method (_DSM, 4, Serialized) + { + If (Arg0 == ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) { + If (Arg2 == 0) { + /* + * Function index: 0 + * Standard query - A bitmask of functions supported + */ + Return (0x81) + } ElseIf (Arg2 == 7) { + /* + * Function index: 7 + * Query if _UPC supports USB-C port capabilities + */ + Return (0x1) + } + } + Return (Buffer() { 0x0 }) + } + + Method (_PS0,0,Serialized) { } + Method (_PS2,0,Serialized) { } + Method (_PS3,0,Serialized) { } + /* High Speed Ports */ Device (HS01) { Name (_ADR, 0x01) + + /* + * HS01 port is not functional + * Report as not visible and not connectable + */ + Method(_UPC, 0 , Serialized) { + Name (UPCP, Package (4) { 0, 0, 0, 0 }) + + Return (UPCP) + } + + Method(_PLD, 0 , Serialized) { + /* Fill with Type-C values */ + Name (PLDP, Package (1) { + Buffer (20) { + 2, /* [7:0] Revision 2 */ + 0,0,0, /* [31:8] */ + 8,0, /* [47:32] Width 8.34mm */ + 3,0, /* [63:48] Height 2.56mm */ + 0, /* [71:64] */ + 4, /* [79:72] Shape oval */ + 0,0,0,0,0,0,0,0,0,0 /* [159:80] */ + } + }) + + Return (PLDP) + } } /* Super Speed Ports */ diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index a0a13997cb7..b3ec0ad6610 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -73,6 +73,7 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case PCI_DEVFN_ROOT: return "MCHC"; case PCI_DEVFN_IGD: return "GFX0"; + case PCI_DEVFN_DPTF: return "DPTF"; case PCI_DEVFN_TCSS_XHCI: return "TXHC"; case PCI_DEVFN_TCSS_XDCI: return "TXDC"; case PCI_DEVFN_TCSS_DMA0: return "TDM0"; @@ -116,6 +117,8 @@ const char *soc_acpi_name(const struct device *dev) case PCI_DEVFN_HDA: return "HDAS"; case PCI_DEVFN_SMBUS: return "SBUS"; case PCI_DEVFN_GBE: return "GLAN"; + case PCI_DEVFN_CSE: return "HEC1"; + case PCI_DEVFN_SRAM: return "SRAM"; } printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n", PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index 1fd1d98fb5f..3e95c8547a3 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -54,8 +54,16 @@ static void sa_finalize(void) static void heci_finalize(void) { + bool heci_disable = false; + heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + + if (is_cse_enabled()) { + heci_disable = cse_is_hfs1_com_debug() || + cse_is_hfs1_com_soft_temp_disable(); + } + + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || heci_disable) heci1_disable(); } @@ -64,7 +72,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); sa_finalize(); if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 5bd28aad2cd..e6513d808ef 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -59,7 +60,7 @@ static const struct slot_irq_constraints irq_constraints[] = { .slot = PCI_DEV_SLOT_IGD, .fns = { /* INTERRUPT_PIN is RO/0x01 */ - FIXED_INT_ANY_PIRQ(PCI_DEV_SLOT_IGD, PCI_INT_A), + FIXED_INT_ANY_PIRQ(PCI_DEVFN_IGD, PCI_INT_A), }, }, { @@ -405,6 +406,8 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, */ if (CONFIG(USE_FSP_FEATURE_PROGRAM_ON_APS)) fill_fsps_microcode_params(s_cfg, config); + + s_cfg->TxtEnable = CONFIG(INTEL_TXT); } @@ -437,7 +440,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, /* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT); + s_cfg->D3ColdEnable = get_sleep_type_option() == SLEEP_TYPE_OPTION_S0IX; s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { @@ -565,7 +568,7 @@ static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF); /* Set TccActivationOffset */ - s_cfg->TccActivationOffset = config->tcc_offset; + s_cfg->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); } static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, @@ -744,7 +747,7 @@ static void arch_silicon_init_params(FSPS_ARCHx_UPD *s_arch_cfg) #endif /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ - if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) #if CONFIG(PLATFORM_USES_FSP2_X86_32) diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h index f52ca6edaac..e5da5d09371 100644 --- a/src/soc/intel/meteorlake/include/soc/pci_devs.h +++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h @@ -241,5 +241,9 @@ #define SA_DEVFN_ROOT PCI_DEVFN_ROOT #define SA_DEVFN_TCSS_DMA0 PCI_DEVFN_TCSS_DMA0 #define SA_DEVFN_TCSS_DMA1 PCI_DEVFN_TCSS_DMA1 +#define SA_DEV_TBT0 PCI_DEV_TBT0 +#define SA_DEV_TBT1 PCI_DEV_TBT1 +#define SA_DEV_TBT2 PCI_DEV_TBT2 +#define SA_DEV_TBT3 PCI_DEV_TBT3 #define SA_DEV_IGD PCI_DEV_IGD #define SA_DEVFN_IGD PCI_DEVFN_IGD diff --git a/src/soc/intel/meteorlake/lockdown.c b/src/soc/intel/meteorlake/lockdown.c index 324c37ba385..0ea10a8dc25 100644 --- a/src/soc/intel/meteorlake/lockdown.c +++ b/src/soc/intel/meteorlake/lockdown.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -13,6 +14,23 @@ #define PCR_PSTH_CTRLREG 0x1d00 #define PSTH_CTRLREG_IOSFPTCGE (1 << 2) +#define MSR_IA32_DEBUG_INTERFACE 0xc80 +#define MSR_IA32_DEBUG_INTERFACE_EN (1 << 0) +#define MSR_IA32_DEBUG_INTERFACE_LOCK (1 << 30) + +static void cpu_lockdown_cfg(void) +{ + msr_t msr = rdmsr(MSR_IA32_DEBUG_INTERFACE); + + if (!(msr.lo & MSR_IA32_DEBUG_INTERFACE_LOCK)) { + if (CONFIG(INTEL_TXT)) + msr.lo &= ~MSR_IA32_DEBUG_INTERFACE_EN; + + msr.lo |= MSR_IA32_DEBUG_INTERFACE_LOCK; + wrmsr(MSR_IA32_DEBUG_INTERFACE, msr); + } +} + static void pmc_lockdown_cfg(int chipset_lockdown) { uint8_t *pmcbase = pmc_mmio_regs(); @@ -51,4 +69,5 @@ void soc_lockdown_config(int chipset_lockdown) pmc_lockdown_cfg(chipset_lockdown); /* SOC Die lock down configuration */ soc_die_lockdown_cfg(); + cpu_lockdown_cfg(); } diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c index dae175fd1a0..2b2edcca38d 100644 --- a/src/soc/intel/meteorlake/meminit.c +++ b/src/soc/intel/meteorlake/meminit.c @@ -38,18 +38,16 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { .num_phys_channels = DDR5_CHANNELS, .phys_to_mrc_map = { [0] = 0, - [1] = 1, - [2] = 4, - [3] = 5, + [1] = 4, }, .md_phy_masks = { /* - * Physical channels 0 and 1 are populated in case of - * half-populated configurations. + * Only channel 0 is populated in case of half-populated + * configuration. */ - .half_channel = BIT(0) | BIT(1), - /* In mixed topologies, channels 2 and 3 are always memory-down. */ - .mixed_topo = BIT(2) | BIT(3), + .half_channel = BIT(0), + /* In mixed topologies, either channel 0 or 1 can be memory-down. */ + .mixed_topo = BIT(0) | BIT(1), }, }, [MEM_TYPE_LP5X] = { @@ -75,7 +73,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { }, }; -static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) +static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + bool expand_channels) { efi_uintn_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, @@ -108,7 +107,16 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { efi_uintn_t *spd_ptr = spd_upds[ch][dimm]; - *spd_ptr = data->spd[ch][dimm]; + // In DDR5 systems, we need to copy the SPD data such that: + // Channel 0 data is used by channel 0 and 1 + // Channel 2 data is used by channel 2 and 3 + // Channel 4 data is used by channel 4 and 5 + // Channel 6 data is used by channel 6 and 7 + if (expand_channels) + *spd_ptr = data->spd[ch & 6][dimm]; + else + *spd_ptr = data->spd[ch][dimm]; + if (*spd_ptr) enable_channel = 1; } @@ -174,27 +182,12 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); } -#define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm)) - -static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info) -{ - for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) { - for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { - size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch]; - mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] = - spd_info->smbus[ch].addr_dimm[dimm] << 1; - } - } - mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true); - mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); -} - void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; + bool expand_channels = false; FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; mem_cfg->ECT = mb_cfg->ect; @@ -205,14 +198,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, case MEM_TYPE_DDR5: meminit_ddr(mem_cfg, &mb_cfg->ddr_config); dq_dqs_auto_detect = true; - /* - * TODO: Drop this workaround once SMBus driver in coreboot is updated to - * support DDR5 EEPROM reading. - */ - if (spd_info->topo == MEM_TOPO_DIMM_MODULE) { - ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info); - return; - } + expand_channels = true; break; case MEM_TYPE_LP5X: meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config); @@ -221,9 +207,9 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, die("Unsupported memory type(%d)\n", mb_cfg->type); } - mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, - half_populated, &data); - mem_init_spd_upds(mem_cfg, &data); + mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, + &data); + mem_init_spd_upds(mem_cfg, &data, expand_channels); mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); } diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 82706ed3bff..a4f98e33483 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -2,10 +2,12 @@ #include #include +#include #include #include #include #include +#include #include #include #include @@ -17,6 +19,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -62,7 +67,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; clk_req_mapping |= 1 << cfg[i].clk_req; } - m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; + /* + * Override the usage only if the clock is unused, otherwise we lose + * FSP_CLK_FREE_RUNNING and FSP_CLK_LAN setting from fill_fspm_pcie_rp_params. + */ + if (m_cfg->PcieClkSrcUsage[cfg[i].clk_src] == FSP_CLK_NOTUSED) + m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; } } @@ -168,7 +178,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->RMC = 0; m_cfg->MarginLimitCheck = 0; /* Enable MRC Fast Boot */ - m_cfg->MrcFastBoot = 1; + m_cfg->MrcFastBoot = !vbnv_cmos_failed(); m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; } @@ -285,6 +295,8 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { + const struct device *dev; + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA); m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; @@ -299,6 +311,13 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + + dev = pcidev_path_on_root(PCI_DEVFN_HDA); + if (dev) { + uint16_t svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086); + uint16_t ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0x7e28); + m_cfg->PchHdaSubSystemIds = (ssid << 16) | svid; + } } static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg, @@ -359,6 +378,8 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION) && dma_protection_enabled(); } static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, @@ -377,8 +398,8 @@ static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { /* In-Band ECC configuration */ - if (config->ibecc.enable) { - m_cfg->Ibecc = config->ibecc.enable; + if (get_ibecc_option(config->ibecc.enable)) { + m_cfg->Ibecc = 1; m_cfg->IbeccParity = config->ibecc.parity_en; m_cfg->IbeccOperationMode = config->ibecc.mode; if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { @@ -406,6 +427,48 @@ static void fill_fsps_acoustic_params(FSP_M_CONFIG *m_cfg, } } +static void fill_txt_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_meteorlake_config *config) +{ +/* Use pre-processor because CONFIG_INTEL_TXT_CBFS_BIOS_ACM is not defined otherwise */ +#if CONFIG(INTEL_TXT) + size_t acm_size = 0; + uintptr_t acm_base; + + intel_txt_log_spad(); + + if (CONFIG(INTEL_CBNT_LOGGING)) + intel_cbnt_log_registers(); + + if (CONFIG(INTEL_TXT_LOGGING)) { + intel_txt_log_bios_acm_error(); + txt_dump_chipset_info(); + } + + acm_base = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, &acm_size); + + /* + * IA32_DEBUG_INTERFACE_MSR has to be locked by coreboot, + * because FSP does not do it unless DebugInterfaceEnable is 1. + * But to use Intel TXT, the debug interface has to be disabled, + * so let coreboot handle the IA32_DEBUG_INTERFACE_MSR programming. + */ + m_cfg->DebugInterfaceEnable = 0; + m_cfg->DebugInterfaceLockEnable = 0; + + m_cfg->VmxEnable = 1; + m_cfg->TxtImplemented = 1; + m_cfg->Txt = 1; + m_cfg->SinitMemorySize = CONFIG_INTEL_TXT_SINIT_SIZE; + m_cfg->TxtHeapMemorySize = CONFIG_INTEL_TXT_HEAP_SIZE; + m_cfg->TxtDprMemorySize = CONFIG_INTEL_TXT_DPR_SIZE << 20; + m_cfg->TxtDprMemoryBase = 1; // Set to non-zero, FSP will update it + m_cfg->BiosAcmBase = acm_base; + m_cfg->BiosAcmSize = acm_size; + m_cfg->ApStartupBase = 1; // Set to non-zero, FSP does NULL check +#endif +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { @@ -430,6 +493,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, fill_fspm_vr_config_params, fill_fspm_ibecc_params, fill_fsps_acoustic_params, + fill_txt_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 5ceb6d55778..c2341fdc545 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -9,7 +9,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -47,7 +49,6 @@ static void save_dimm_info(void) printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); return; } - /* * Allocate CBMEM area for DIMM information used to populate SMBIOS * table 17 @@ -69,6 +70,10 @@ static void save_dimm_info(void) dimm_max = ARRAY_SIZE(mem_info->dimm); for (node = 0; node < MAX_NODE; node++) { ctrlr_info = &meminfo_hob->Controller[node]; + + if (ctrlr_info->Status != CHANNEL_PRESENT) + continue; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { channel_info = &ctrlr_info->ChannelInfo[channel]; if (channel_info->Status != CHANNEL_PRESENT) @@ -91,6 +96,8 @@ static void save_dimm_info(void) uint8_t memProfNum = meminfo_hob->MemoryProfile; serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; + printk(BIOS_DEBUG, "Filling DIMM info for Controller %d Channel %d DIMM %d\n", + node, channel, dimm); /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -128,6 +135,11 @@ void mainboard_romstage_entry(void) /* Initialize HECI interface */ cse_init(HECI1_BASE_ADDRESS); + if (!CONFIG(INTEL_TXT)) + disable_intel_txt(); + else + intel_txt_romstage_init(); + if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) { cse_fill_bp_info(); if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE)) @@ -155,4 +167,7 @@ void mainboard_romstage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); + + if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + vtd_enable_dma_protection(); } diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 81dbe8050d1..4f6f658fc14 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -79,6 +79,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP @@ -248,14 +249,6 @@ config P2SB_2_PCR_BASE_ADDRESS config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR - int - default 125 # TODO: Update with PTL data - -config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR - int - default 100 # TODO: Update with PTL data - config CPU_BCLK_MHZ int default 100 diff --git a/src/soc/intel/pantherlake/finalize.c b/src/soc/intel/pantherlake/finalize.c index 05ec3eaaca9..186a2b87b42 100644 --- a/src/soc/intel/pantherlake/finalize.c +++ b/src/soc/intel/pantherlake/finalize.c @@ -64,6 +64,9 @@ static void soc_finalize(void *unused) pch_finalize(); apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); sa_finalize(); if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && diff --git a/src/soc/intel/pantherlake/include/soc/systemagent.h b/src/soc/intel/pantherlake/include/soc/systemagent.h index fbe8dd25cce..4139c37aff5 100644 --- a/src/soc/intel/pantherlake/include/soc/systemagent.h +++ b/src/soc/intel/pantherlake/include/soc/systemagent.h @@ -23,6 +23,8 @@ #define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define PCODE_MAILBOX_DATA 0x5da0 +#define PCODE_MAILBOX_INTERFACE 0x5da4 #define BIOS_RESET_CPL 0x5da8 #define IMRBASE 0x6a40 #define IMRLIMIT 0x6a48 diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c index e7a0701f98b..a5a734f02dc 100644 --- a/src/soc/intel/pantherlake/systemagent.c +++ b/src/soc/intel/pantherlake/systemagent.c @@ -2,9 +2,12 @@ #include #include +#include #include +#include #include #include +#include #include #include #include @@ -183,6 +186,142 @@ static void configure_tdp(struct device *dev) } } +union pcode_mailbox_command { + struct { + uint32_t command: 8; + uint32_t param1: 8; + uint32_t param2: 13; + uint32_t reserved: 2; + /* + * Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is + * ready. pcode will clear this bit after the message is + * consumed. + */ + uint32_t runbusy: 1; + } fields; + uint32_t data; +}; + +union pcode_scaling_factor { + struct { + /* Core scaling factor */ + uint32_t scaling_factor: 16; + /* + * Number of modules with consecutive module id sharing the same scaling + * factor + */ + uint32_t num_equivalent_module: 8; + uint32_t reserved: 8; + } fields; + uint32_t data; +}; + +#define MAILBOX_WAIT_TIMEOUT_US 1000 +#define PCODE_READ_CORE_SCALING_FACTOR_CMD 0x21 + +static bool poll_mailbox_ready(void) +{ + union pcode_mailbox_command cmd; + size_t i; + + for (i = 0; i < MAILBOX_WAIT_TIMEOUT_US; i++) { + cmd.data = MCHBAR32(PCODE_MAILBOX_INTERFACE); + if (!cmd.fields.runbusy) + return true; + udelay(1); + } + return false; +} + +static u16 u88_to_scaling_factor(u16 u88) +{ + unsigned int tmp = (u88 & 0xff) * 100; + unsigned int fraction = tmp / (1 << 8); + + /* Rounding */ + if (((tmp & 0xff) << 1) >= (1 << 8)) + fraction++; + return ((u88 >> 8) * 100) + fraction; +} + +/* + * The following function sends commands to the pcode mailbox interface to read the core scaling + * factors for performance and efficient cores. + * + * The READ_CORE_SCALING_FACTOR command takes a module ID as a parameter. The function iterates + * over all the CPU devices to identify module IDs of different core types (efficient and + * performance). + * + * If no efficient cores are present, no efficient factor is returned. + * + * Return values: + * - CB_ERR_ARG: If any of the input pointers were NULL. + * - CB_ERR: If there was a generic error while reading the scaling factors. + * - CB_SUCCESS: If the scaling factors were read successfully. + */ +enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient) +{ + extern struct cpu_info cpu_infos[]; + union pcode_mailbox_command cmd = { + .fields = { + .command = PCODE_READ_CORE_SCALING_FACTOR_CMD, + .runbusy = 1 + } + }; + union pcode_scaling_factor res; + bool has_efficient_core = false; + + if (!performance || !efficient) + return CB_ERR_ARG; + + for (size_t i = 0; i < CONFIG_MAX_CPUS; i++) { + struct device *cpu = cpu_infos[i].cpu; + + if (!cpu) + continue; + + if (cpu->path.apic.core_type != CPU_TYPE_PERF) + has_efficient_core = true; + + if (cpu->path.apic.core_type == CPU_TYPE_PERF && *performance) + continue; + + cmd.fields.param1 = cpu->path.apic.module_id; + + if (!poll_mailbox_ready()) { + printk(BIOS_ERR, "pcode mailbox is busy\n"); + return CB_ERR; + } + + MCHBAR32(PCODE_MAILBOX_INTERFACE) = cmd.data; + + if (!poll_mailbox_ready()) { + printk(BIOS_ERR, "pcode command mailbox not completing in time\n"); + return CB_ERR; + } + + res.data = MCHBAR32(PCODE_MAILBOX_DATA); + + if (cpu->path.apic.core_type == CPU_TYPE_PERF) + *performance = u88_to_scaling_factor(res.fields.scaling_factor); + else + *efficient = u88_to_scaling_factor(res.fields.scaling_factor); + + if (*performance && *efficient) + break; + } + + if (!*performance) { + printk(BIOS_ERR, "Could not read performance scaling factor\n"); + return CB_ERR; + } + if (has_efficient_core && !*efficient) { + printk(BIOS_ERR, "Could not read efficient scaling factor\n"); + return CB_ERR; + } + return CB_SUCCESS; +} + /* * SoC implementation * diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a6844e068a0..153777a95d9 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -501,7 +502,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->Eist = config->eist_enable; /* Set TccActivationOffset */ - tconfig->TccActivationOffset = config->tcc_offset; + tconfig->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); /* Already handled in coreboot code, so tell FSP to ignore UPDs */ params->PchIoApicBdfValid = 0; diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index fd80aeac1a0..a147b62e46f 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -106,7 +106,8 @@ static void soc_finalize(void *unused) pch_finalize_script(dev); soc_lockdown(dev); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); /* Indicate finalize step with post code */ post_code(POSTCODE_OS_BOOT); diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 1b04fbc0c8f..ff7cf652892 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -69,6 +69,7 @@ config SOC_INTEL_TIGERLAKE select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_VTD select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT @@ -76,17 +77,15 @@ config SOC_INTEL_TIGERLAKE select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_CSE_SEND_EOP_LATE select SOC_INTEL_CSE_SET_EOP + select HAVE_INTEL_ME_HAP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING - select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM - select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if CHROMEOS select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50 select X86_CLFLUSH_CAR help diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index dd9ef731a3d..bb12f697a48 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -326,6 +326,8 @@ void soc_fill_gnvs(struct global_nvs *gnvs) /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + gnvs->s0ix = config->s0ix_enable; } int soc_madt_sci_irq_polarity(int sci) diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 588ed5e2857..fd827ed70cf 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -331,7 +331,7 @@ Scope (\_SB.PCI0) Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) - Name (_STA, 0xF) + Name (_STA, 0xB) } /* @@ -542,47 +542,6 @@ Scope (\_SB.PCI0) } } - PowerResource (TBT0, 5, 1) - { - Method (_STA, 0) - { - Return (\_SB.PCI0.TDM0.STAT) - } - - Method (_ON, 0) - { - TG0N() - } - - Method (_OFF, 0) - { - If (\_SB.PCI0.TDM0.SD3C == 0) { - TG0F() - } - } - } - - PowerResource (TBT1, 5, 1) - { - Method (_STA, 0) - { - Return (\_SB.PCI0.TDM1.STAT) - } - - Method (_ON, 0) - { - TG1N() - } - - Method (_OFF, 0) - { - If (\_SB.PCI0.TDM1.SD3C == 0) { - TG1F() - } - } - } - -#if CONFIG(D3COLD_SUPPORT) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -627,33 +586,74 @@ Scope (\_SB.PCI0) TD3C = 1 } - PowerResource (D3C, 5, 0) - { - /* - * Variable to save power state - * 1 - TC Cold request cleared. - * 0 - TC Cold request sent. - */ - Name (STAT, 0x1) - - Method (_STA, 0) + If (S0IX == 1) { + PowerResource (TBT0, 5, 1) { - Return (STAT) + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM0.STAT) + } + + Method (_ON, 0) + { + TG0N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM0.SD3C == 0) { + TG0F() + } + } } - Method (_ON, 0) + PowerResource (TBT1, 5, 1) { - \_SB.PCI0.TCON() - STAT = 1 + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM1.STAT) + } + + Method (_ON, 0) + { + TG1N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM1.SD3C == 0) { + TG1F() + } + } } - Method (_OFF, 0) + PowerResource (D3C, 5, 0) { - \_SB.PCI0.TCOF() - STAT = 0 + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) + + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } } - } -#endif // D3COLD_SUPPORT + } // S0IX == 1 /* * TCSS xHCI device diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 2586ecbbc75..54cc68ffb40 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -28,49 +28,32 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ Method (_S0W, 0x0) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x04) -#else - Return (0x03) -#endif // D3COLD_SUPPORT -} - -/* - * Get power resources that are dependent on this device for Operating System Power Management - * to put the device in the D0 device state - */ -Method (_PR0) -{ -#if CONFIG(D3COLD_SUPPORT) - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } -#else - If (DUID == 0) { - Return (Package() { \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + Return (0x04) } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + Return (0x03) } -#endif // D3COLD_SUPPORT } -Method (_PR3) -{ -#if CONFIG(D3COLD_SUPPORT) - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) +If (S0IX == 1) { + Method (_PR0) + { + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#else - If (DUID == 0) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + + Method (_PR3) + { + + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 6dbde46f49d..f40c012b4f5 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -245,47 +245,34 @@ Method (_PS3, 0, Serialized) } } -Method (_S0W, 0x0, NotSerialized) -{ -#if CONFIG(D3COLD_SUPPORT) - Return (0x4) -#else - Return (0x3) -#endif // D3COLD_SUPPORT -} -Method (_PR0) +Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + Return (0x04) } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + Return (0x03) } -#else - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) - } -#endif // D3COLD_SUPPORT } -Method (_PR3) -{ -#if CONFIG(D3COLD_SUPPORT) - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) +If (S0IX == 1) { + Method (_PR0) + { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#else - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + + Method (_PR3) + { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl index ddc5a6665dc..1ca4117697c 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x4) -#else - Return (0x3) -#endif // D3COLD_SUPPORT + If (S0IX == 1) { + Return (0x4) + } Else { + Return (0x3) + } } /* @@ -43,17 +43,17 @@ Method (_S0W, 0x0, NotSerialized) */ Name (SD3C, 0) -#if CONFIG(D3COLD_SUPPORT) -Method (_PR0) -{ - Return (Package () { \_SB.PCI0.D3C }) -} +If (S0IX == 1) { + Method (_PR0) + { + Return (Package () { \_SB.PCI0.D3C }) + } -Method (_PR3) -{ - Return (Package () { \_SB.PCI0.D3C }) + Method (_PR3) + { + Return (Package () { \_SB.PCI0.D3C }) + } } -#endif // D3COLD_SUPPORT /* * XHCI controller _DSM method diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index cd02745a9e6..158b2fb6916 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -55,7 +55,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index c3400b45c93..0060a4e1592 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -329,7 +330,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) if (cpu_id == CPUID_TIGERLAKE_A0) params->D3ColdEnable = 0; else - params->D3ColdEnable = CONFIG(D3COLD_SUPPORT); + params->D3ColdEnable = get_sleep_type_option() == SLEEP_TYPE_OPTION_S0IX; params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; @@ -489,7 +490,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); /* Set TccActivationOffset */ - params->TccActivationOffset = config->tcc_offset; + params->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); /* LAN */ params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); diff --git a/src/soc/intel/tigerlake/include/soc/dptf.h b/src/soc/intel/tigerlake/include/soc/dptf.h index 467ac659158..83278f4dfcf 100644 --- a/src/soc/intel/tigerlake/include/soc/dptf.h +++ b/src/soc/intel/tigerlake/include/soc/dptf.h @@ -10,5 +10,9 @@ #define DPTF_GEN_DEVICE "INTC1043" /* Fan ACPI Device ID */ #define DPTF_FAN_DEVICE "INTC1044" +/* TPWR ACPI Device ID */ +#define DPTF_TPWR_DEVICE "INTC1047" +/* BAT1 ACPI Device ID */ +#define DPTF_BAT1_DEVICE "INTC1050" #endif /* _SOC_DPTF_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index d93c97f3c33..c58243a2580 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -5,81 +5,81 @@ #include -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _SA_DEVFN(slot, func) PCI_DEVFN(SA_DEV_SLOT_ ## slot, func) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) +#define _SA_DEV(slot, func) pcidev_path_on_root(_SA_DEVFN(slot, func)) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _SA_DEV(slot, func) PCI_DEV(0, SA_DEV_SLOT_ ## slot, func) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#define SA_DEVFN_ROOT _SA_DEVFN(ROOT, 0) #if defined(__SIMPLE_DEVICE__) #define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif #define SA_DEV_SLOT_PEG 0x01 -#define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 0) -#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 1) -#define SA_DEVFN_PEG3 PCI_DEVFN(SA_DEV_SLOT_PEG, 2) +#define SA_DEVFN_PEG1 _SA_DEVFN(PEG, 0) +#define SA_DEVFN_PEG2 _SA_DEVFN(PEG, 1) +#define SA_DEVFN_PEG3 _SA_DEVFN(PEG, 2) #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) -#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEVFN_IGD _SA_DEVFN(IGD, 0) +#define SA_DEV_IGD _SA_DEV(IGD, 0) #define SA_DEV_SLOT_DPTF 0x04 -#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) -#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) +#define SA_DEVFN_DPTF _SA_DEVFN(DPTF, 0) +#define SA_DEV_DPTF _SA_DEV(DPTF, 0) #define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEVFN_IPU _SA_DEVFN(IPU, 0) +#define SA_DEV_IPU _SA_DEV(IPU, 0) #define SA_DEV_SLOT_CPU_PCIE 0x06 -#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0) +#define SA_DEVFN_CPU_PCIE _SA_DEVFN(CPU_PCIE, 0) #define SA_DEV_SLOT_TBT 0x07 -#define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x)) +#define SA_DEVFN_TBT(x) _SA_DEVFN(TBT, (x)) #define NUM_TBT_FUNCTIONS 4 -#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) -#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) -#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) -#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) -#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) -#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) -#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) -#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEVFN_TBT0 _SA_DEVFN(TBT, 0) +#define SA_DEVFN_TBT1 _SA_DEVFN(TBT, 1) +#define SA_DEVFN_TBT2 _SA_DEVFN(TBT, 2) +#define SA_DEVFN_TBT3 _SA_DEVFN(TBT, 3) +#define SA_DEV_TBT0 _SA_DEV(TBT, 0) +#define SA_DEV_TBT1 _SA_DEV(TBT, 1) +#define SA_DEV_TBT2 _SA_DEV(TBT, 2) +#define SA_DEV_TBT3 _SA_DEV(TBT, 3) #define SA_DEV_SLOT_GNA 0x08 -#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) -#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) +#define SA_DEVFN_GNA _SA_DEVFN(GNA, 0) +#define SA_DEV_GNA _SA_DEV(GNA, 0) #define SA_DEV_SLOT_TMT 0x0A -#define SA_DEVFN_TMT _SA_DEVFN(TMT) -#define SA_DEV_TMT _SA_DEV(TMT) +#define SA_DEVFN_TMT _SA_DEVFN(TMT, 0) +#define SA_DEV_TMT _SA_DEV(TMT, 0) #define SA_DEV_SLOT_TCSS 0x0d #define NUM_TCSS_DMA_FUNCTIONS 2 -#define SA_DEVFN_TCSS_DMA(x) PCI_DEVFN(SA_DEV_SLOT_TCSS, ((x) + 2)) -#define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) -#define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) +#define SA_DEVFN_TCSS_DMA(x) _SA_DEVFN(TCSS, ((x) + 2)) +#define SA_DEVFN_TCSS_XHCI _SA_DEVFN(TCSS, 0) +#define SA_DEVFN_TCSS_XDCI _SA_DEVFN(TCSS, 1) #define SA_DEVFN_TCSS_DMA0 SA_DEVFN_TCSS_DMA(0) #define SA_DEVFN_TCSS_DMA1 SA_DEVFN_TCSS_DMA(1) -#define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) -#define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) -#define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) -#define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_TCSS_XHCI _SA_DEV(TCSS, 0) +#define SA_DEV_TCSS_XDCI _SA_DEV(TCSS, 1) +#define SA_DEV_TCSS_DMA0 _SA_DEV(TCSS, 2) +#define SA_DEV_TCSS_DMA1 _SA_DEV(TCSS, 3) #define SA_DEV_SLOT_VMD 0x0e -#define SA_DEVFN_VMD PCI_DEVFN(SA_DEV_SLOT_VMD, 0) -#define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0) +#define SA_DEVFN_VMD _SA_DEVFN(VMD, 0) +#define SA_DEV_VMD _SA_DEV(VMD, 0) /* PCH Devices */ #define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index ee02a48a444..ee5783aa6a2 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -77,6 +77,10 @@ extern struct device_operations pmc_ops; #define PRSTS 0x1810 +#define PM_CFG 0x1818 +#define PM_CFG_DBG_MODE_LOCK (1 << 27) +#define PM_CFG_XRAM_READ_DISABLE (1 << 22) + #define S3_PWRGATE_POL 0x1828 #define S3DC_GATE_SUS (1 << 1) #define S3AC_GATE_SUS (1 << 0) @@ -157,6 +161,9 @@ extern struct device_operations pmc_ops; #define ACPI_EN (1 << 7) #define SCI_IRQ_SEL (7 << 0) +#define ST_PG_FDIS1 0x1e20 +#define ST_FDIS_LOCK (1 << 31) + #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 #define SCIS_IRQ11 2 diff --git a/src/soc/intel/tigerlake/lockdown.c b/src/soc/intel/tigerlake/lockdown.c index 2f7ccebc8b3..5413fae5ac6 100644 --- a/src/soc/intel/tigerlake/lockdown.c +++ b/src/soc/intel/tigerlake/lockdown.c @@ -8,10 +8,17 @@ #include #include +#include +#include #include +#include #include #include +/* PCR PSTH Control Register */ +#define PCR_PSTH_CTRLREG 0x1d00 +#define PSTH_CTRLREG_IOSFPTCGE (1 << 2) + static void pmc_lock_pmsync(void) { uint8_t *pmcbase; @@ -50,6 +57,8 @@ static void pmc_lock_smi(void) static void pmc_lockdown_cfg(int chipset_lockdown) { + uint8_t *pmcbase = pmc_mmio_regs(); + /* PMSYNC */ pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ @@ -57,10 +66,31 @@ static void pmc_lockdown_cfg(int chipset_lockdown) if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { + setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); + setbits32(pmcbase + SSML, SSML_SSL_EN); + setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | + PM_CFG_XRAM_READ_DISABLE); + } + + /* Send PMC IPC to inform about PCI enumeration done */ + pmc_send_bios_reset_pci_enum_done(); +} + +static void pch_lockdown_cfg(void) +{ + if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + return; + + /* Enable IOSF Primary Trunk Clock Gating */ + pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); } void soc_lockdown_config(int chipset_lockdown) { /* PMC lock down configuration */ pmc_lockdown_cfg(chipset_lockdown); + /* PCH lock down configuration */ + pch_lockdown_cfg(); } diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 8912cb3c63e..8846c944648 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -107,7 +107,7 @@ static void soc_pmc_fill_ssdt(const struct device *dev) acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller"); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 5ebd46dd75d..60f0f56d77b 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -183,6 +184,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; } + m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION) && dma_protection_enabled(); + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); @@ -209,8 +212,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; /* In-Band ECC configuration */ - if (config->ibecc.enable) { - m_cfg->Ibecc = !!config->ibecc.enable; + if (get_ibecc_option(config->ibecc.enable)) { + m_cfg->Ibecc = 1; m_cfg->IbeccParity = !!config->ibecc.parity_en; m_cfg->IbeccOperationMode = config->ibecc.mode; if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) { diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 1985ea3c5bc..1f498d70a81 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -8,7 +8,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -128,6 +130,9 @@ void mainboard_romstage_entry(void) bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + if (CONFIG(INTEL_CBNT_LOGGING)) + intel_cbnt_log_registers(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ @@ -150,4 +155,7 @@ void mainboard_romstage_entry(void) save_dimm_info(); } + + if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + vtd_enable_dma_protection(); } diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c index a7b36027442..f0cd8a1998f 100644 --- a/src/soc/intel/xeon_sp/finalize.c +++ b/src/soc/intel/xeon_sp/finalize.c @@ -59,7 +59,8 @@ static void soc_finalize(void *unused) if (!CONFIG(USE_PM_ACPI_TIMER)) setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); if (CONFIG_MAX_SOCKET > 1) { /* This MSR is package scope but run for all cpus for code simplicity */ diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index d6c9832f524..e36f684cc67 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -16,6 +16,7 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP select UDK_202005_BINDING select SOC_INTEL_HAS_CXL select HAVE_X86_64_SUPPORT + select HAVE_INTEL_FSP_REPO help Intel Sapphire Rapids-SP support @@ -26,8 +27,10 @@ config CHIPSET_DEVICETREE default "soc/intel/xeon_sp/spr/chipset.cb" config FSP_HEADER_PATH - string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp" + default "3rdparty/fsp/EagleStreamFspBinPkg/Include" + +config FSP_FD_PATH + default "3rdparty/fsp/EagleStreamFspBinPkg/Fsp.fd" config MAX_CPUS int diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index 39d6a99d289..63bb86611e1 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -24,6 +24,7 @@ ramstage-y += ../pcu3.c ramstage-y += ../pcu6.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8f-08 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-cf-02 diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 43eb187d841..0153485597b 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "chip.h" diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 134b57546d2..11bb87c7ac1 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -13,7 +13,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_CUSTOM_MADT - select HAVE_CONFIGURABLE_APMC_SMI_PORT select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE @@ -24,6 +23,9 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_SPI if SOUTHBRIDGE_AMD_PI_AVALON + select BOOT_DEVICE_SUPPORTS_WRITES if SOUTHBRIDGE_AMD_PI_AVALON + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if SOUTHBRIDGE_AMD_PI_AVALON select USE_AMDFWTOOL config EHCI_BAR diff --git a/src/southbridge/amd/pi/hudson/Makefile.mk b/src/southbridge/amd/pi/hudson/Makefile.mk index e7ec1b73ec5..2e40edcaa64 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.mk +++ b/src/southbridge/amd/pi/hudson/Makefile.mk @@ -35,6 +35,7 @@ all-y += reset.c smm-y += smihandler.c smm-y += smi_util.c +smm-y += lpc_simpledev.c CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include @@ -50,7 +51,7 @@ CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) else -HUDSON_FWM_POSITION=0xfff20000 +HUDSON_FWM_POSITION=0xfffa0000 endif ifeq ($(CONFIG_HUDSON_PSP), y) diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index faf549d2e8e..282dc0fc909 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -6,49 +6,11 @@ #include #include -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The HUDSON power-on default is to map 512K ROM space. - * - */ -static void hudson_enable_rom(void) -{ - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - - /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_s_read_config8(dev, 0x48); - reg8 |= (1 << 3) | (1 << 4); - pci_s_write_config8(dev, 0x48, reg8); - - /* LPC ROM address range 1: */ - /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_s_write_config16(dev, 0x68, 0x000e); - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_s_write_config16(dev, 0x6a, 0x000f); - - /* LPC ROM address range 2: */ - /* - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_s_write_config16(dev, 0x6e, 0xffff); -} - void bootblock_early_southbridge_init(void) { u32 data; - hudson_enable_rom(); + hudson_enable_lpc_rom(); enable_acpimmio_decode_pm04(); hudson_lpc_decode(); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 1e1a2f44aec..ad91cd36df2 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -191,13 +192,13 @@ void hudson_clk_output_48Mhz(void) misc_write32(FCH_MISC_REG40, ctrl); } -static uintptr_t hudson_spibase(void) +uintptr_t lpc_get_spibase(void) { /* Make sure the base address is predictable */ const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) - & 0xfffffff0; + & 0xffffffc0; if (!base) { base = SPI_BASE_ADDRESS; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base @@ -209,7 +210,7 @@ static uintptr_t hudson_spibase(void) void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { - uintptr_t base = hudson_spibase(); + uintptr_t base = lpc_get_spibase(); write16p(base + SPI100_SPEED_CONFIG, (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | @@ -221,7 +222,7 @@ void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) void hudson_disable_4dw_burst(void) { - uintptr_t base = hudson_spibase(); + uintptr_t base = lpc_get_spibase(); write16p(base + SPI100_HOST_PREF_CONFIG, read16p(base + SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST); @@ -230,7 +231,7 @@ void hudson_disable_4dw_burst(void) /* Hudson 1-3 only. For Hudson 1, call with fast=1 */ void hudson_set_readspeed(u16 norm, u16 fast) { - uintptr_t base = hudson_spibase(); + uintptr_t base = lpc_get_spibase(); write16p(base + SPI_CNTRL1, (read16p(base + SPI_CNTRL1) & ~SPI_CNTRL1_SPEED_MASK) @@ -240,7 +241,7 @@ void hudson_set_readspeed(u16 norm, u16 fast) void hudson_read_mode(u32 mode) { - uintptr_t base = hudson_spibase(); + uintptr_t base = lpc_get_spibase(); write32p(base + SPI_CNTRL0, (read32p(base + SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode); @@ -255,4 +256,43 @@ void hudson_tpm_decode_spi(void) | ROUTE_TPM_2_SPI); } +/* + * Enable LPC ROM access at 0xFFXX0000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The HUDSON power-on default is to map 512K ROM space. + * + */ +void hudson_enable_lpc_rom(void) +{ + u8 reg8; + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_s_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_s_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_s_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_s_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + * ... + */ + pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_s_write_config16(dev, 0x6e, 0xffff); +} + #endif diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 26fb2588790..9d034d9bcdb 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -16,13 +16,6 @@ #include "smi.h" #include "fchec.h" -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - return (int)tmp; -} - void hudson_enable(struct device *dev) { printk(BIOS_DEBUG, "%s()\n", __func__); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 96a5367a448..d742dd34bb5 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -167,6 +167,7 @@ void hudson_set_readspeed(u16 norm, u16 fast); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); void hudson_tpm_decode_spi(void); +void hudson_enable_lpc_rom(void); void hudson_enable(struct device *dev); void s3_resume_init_data(void *FchParams); diff --git a/src/southbridge/amd/pi/hudson/include/soc/acpi.h b/src/southbridge/amd/pi/hudson/include/soc/acpi.h new file mode 100644 index 00000000000..80fcc9921ec --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/acpi.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_ACPI_H +#define SOC_ACPI_H + +#endif /* SOC_ACPI_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/iomap.h b/src/southbridge/amd/pi/hudson/include/soc/iomap.h new file mode 100644 index 00000000000..df40f0fe714 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/iomap.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_IOMAP_H +#define SOC_IOMAP_H + +#endif /* SOC_IOMAP_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/lpc.h b/src/southbridge/amd/pi/hudson/include/soc/lpc.h new file mode 100644 index 00000000000..0c966e93838 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/lpc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_LPC_H +#define SOC_LPC_H + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(6) +#define SPI_BASE_RESERVED (BIT(0) | BIT(2) | BIT(4) | BIT(5)) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_PRESERVE_BITS (BIT(1) | BIT(3)) + +#endif /* SOC_LPC_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/nvs.h b/src/southbridge/amd/pi/hudson/include/soc/nvs.h new file mode 100644 index 00000000000..c4db17e8db7 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/nvs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_NVS_H +#define SOC_NVS_H + +struct __packed global_nvs { + // TODO + uint8_t rsv0; + uint8_t rsv1; + uint8_t rsv2; + uint32_t rsv3; + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t rsv4; + uint8_t rsv5; + uint8_t rsv6; +}; + +#endif /* SOC_NVS_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/pci_devs.h b/src/southbridge/amd/pi/hudson/include/soc/pci_devs.h new file mode 100644 index 00000000000..747ccfc0884 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/pci_devs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_PCI_DEVS_H +#define SOC_PCI_DEVS_H + +#include + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _SOC_DEV(slot, func) pcidev_on_root(slot, func) +#else +#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) +#endif + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_FUNC 3 +#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) +#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) + +#endif /* SOC_PCI_DEVS_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/smi.h b/src/southbridge/amd/pi/hudson/include/soc/smi.h index da5ddbc2f73..0ee3721c0f4 100644 --- a/src/southbridge/amd/pi/hudson/include/soc/smi.h +++ b/src/southbridge/amd/pi/hudson/include/soc/smi.h @@ -3,9 +3,43 @@ #ifndef SOC_SMI_H #define SOC_SMI_H +/* TODO: include Fch.h and use macros from there? */ + +#define SCI_GPES 32 +#define SCIMAPS 64 +#define SMI_GEVENTS 24 +#define NUMBER_SMITYPES 160 + +#define SMITYPE_SMI_CMD_PORT 0x4b + +#define SMI_EVENT_STATUS 0x00 #define SMI_SCI_TRIG 0x08 #define SMI_SCI_LEVEL 0x0c #define SMI_SCI_STATUS 0x10 #define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +#define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) + +#define SMI_REG_SMISTS0 0x80 +#define GEVENT_MASK 0x00ffffff +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +#define SMI_STATUS_SRC_SCI (1 << 0) +#define SMI_STATUS_SRC_0 (1 << 1) +#define SMI_STATUS_SRC_1 (1 << 2) +#define SMI_STATUS_SRC_2 (1 << 3) +#define SMI_STATUS_SRC_3 (1 << 4) +#define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_REG_SMITRIG0 0x98 +#define SMITRG0_SMIENB (1 << 31) +#define SMITRG0_EOS (1 << 28) + +#define SMI_REG_CONTROL0 0xa0 + #endif /* SOC_SMI_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/southbridge.h b/src/southbridge/amd/pi/hudson/include/soc/southbridge.h new file mode 100644 index 00000000000..bea21c50e38 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/southbridge.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_SOUTHBRIDGE_H +#define SOC_SOUTHBRIDGE_H + +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + +#define PM_ACPI_SMI_CMD 0x6a + +#define PWRBTN_STS (1 << 8) +#define RTC_STS (1 << 10) +#define PCIEXPWAK_STS (1 << 14) +#define WAK_STS (1 << 15) + +#endif /* SOC_SOUTHBRIDGE_H */ diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 66ec82414fe..1cce7428736 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include #include @@ -314,6 +316,18 @@ static void hudson_lpc_enable_resources(struct device *dev) hudson_lpc_enable_childrens_resources(dev); } +uintptr_t lpc_get_spibase(void) +{ + struct device *dev = pcidev_on_root(0x14, 3); + + u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) & 0xffffffc0; + if (!base) { + base = SPI_BASE_ADDRESS; + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base | SPI_ROM_ENABLE); + } + return (uintptr_t)base; +} + static const char *lpc_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) @@ -328,10 +342,12 @@ static const char *lpc_acpi_name(const struct device *dev) static void lpc_final(struct device *dev) { if (!acpi_is_wakeup_s3()) { + acpi_clear_pm_gpe_status(); + if (CONFIG(HAVE_SMI_HANDLER)) - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + acpi_disable_sci(); else - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + acpi_enable_sci(); } } diff --git a/src/southbridge/amd/pi/hudson/lpc_simpledev.c b/src/southbridge/amd/pi/hudson/lpc_simpledev.c new file mode 100644 index 00000000000..bee7ed66740 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/lpc_simpledev.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "hudson.h" +#include "pci_devs.h" + +uintptr_t lpc_get_spibase(void) +{ + u32 base; + + base = pci_read_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), + SPIROM_BASE_ADDRESS_REGISTER); + base &= 0xffffffc0; + return (uintptr_t)base; +} diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 560b66679b5..193e64d2c84 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -4,16 +4,11 @@ * Utilities for SMM setup */ -#include +#include #include -#include "smi.h" - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) +void smm_region(uintptr_t *start, size_t *size) { - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); + *start = (uintptr_t)cbmem_top(); + *size = CONFIG_SMM_TSEG_SIZE; } diff --git a/src/southbridge/amd/pi/hudson/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c index 70b35850d6e..3dc2d8a31e5 100644 --- a/src/southbridge/amd/pi/hudson/smi_util.c +++ b/src/southbridge/amd/pi/hudson/smi_util.c @@ -6,9 +6,7 @@ #include #include -#include -#include "hudson.h" #include "smi.h" #define HUDSON_SMI_ACPI_COMMAND 75 @@ -79,8 +77,3 @@ void hudson_enable_acpi_cmd_smi(void) { configure_smi(HUDSON_SMI_ACPI_COMMAND, SMI_MODE_SMI); } - -uint16_t pm_acpi_smi_cmd_port(void) -{ - return pm_read16(PM_ACPI_SMI_CMD); -} diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 8b88c06de3f..8aa77135d4c 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -4,125 +4,44 @@ * SMI handler for Hudson southbridges */ -#include +#include +#include +#include +#include #include #include -#include "hudson.h" -#include "smi.h" - -#define SMI_0x88_ACPI_COMMAND (1 << 11) - -enum smi_source { - SMI_SOURCE_SCI = (1 << 0), - SMI_SOURCE_GPE = (1 << 1), - SMI_SOURCE_0x84 = (1 << 2), - SMI_SOURCE_0x88 = (1 << 3), - SMI_SOURCE_IRQ_TRAP = (1 << 4), - SMI_SOURCE_0x90 = (1 << 5) -}; - -static void hudson_apmc_smi_handler(void) +static void fch_apmc_smi_handler_no_psp(void) { - u32 reg32; - const uint8_t cmd = apm_get_apmc(); + const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); switch (cmd) { case APM_CNT_ACPI_ENABLE: - reg32 = inl(ACPI_PM1_CNT_BLK); - reg32 |= (1 << 0); /* SCI_EN */ - outl(reg32, ACPI_PM1_CNT_BLK); + acpi_clear_pm_gpe_status(); + acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: - reg32 = inl(ACPI_PM1_CNT_BLK); - reg32 &= ~(1 << 0); /* clear SCI_EN */ - outl(ACPI_PM1_CNT_BLK, reg32); + acpi_disable_sci(); + break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + handle_smi_store(); break; } mainboard_smi_apmc(cmd); } -static void process_smi_sci(void) -{ - const uint32_t status = smi_read32(0x10); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x10, status); -} - -static void process_gpe_smi(void) -{ - const uint32_t status = smi_read32(0x80); - const uint32_t gevent_mask = (1 << 24) - 1; - - /* Only Bits [23:0] indicate GEVENT SMIs. */ - if (status & gevent_mask) { - /* A GEVENT SMI occurred */ - mainboard_smi_gpi(status & gevent_mask); - } - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x80, status); -} - -static void process_smi_0x84(void) -{ - const uint32_t status = smi_read32(0x84); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x84, status); -} - -static void process_smi_0x88(void) -{ - const uint32_t status = smi_read32(0x88); - - if (status & SMI_0x88_ACPI_COMMAND) { - /* Command received via ACPI SMI command port */ - hudson_apmc_smi_handler(); - } - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x88, status); -} - -static void process_smi_0x8c(void) -{ - const uint32_t status = smi_read32(0x8c); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x8c, status); -} - -static void process_smi_0x90(void) -{ - const uint32_t status = smi_read32(0x90); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x90, status); -} +static const struct smi_sources_t smi_sources[] = { + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler_no_psp }, +}; -void southbridge_smi_handler(void) +void *get_smi_source_handler(int source) { - const uint16_t smi_src = smi_read16(0x94); - - if (smi_src & SMI_SOURCE_SCI) - process_smi_sci(); - if (smi_src & SMI_SOURCE_GPE) - process_gpe_smi(); - if (smi_src & SMI_SOURCE_0x84) - process_smi_0x84(); - if (smi_src & SMI_SOURCE_0x88) - process_smi_0x88(); - if (smi_src & SMI_SOURCE_IRQ_TRAP) - process_smi_0x8c(); - if (smi_src & SMI_SOURCE_0x90) - process_smi_0x90(); -} + size_t i; -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); + for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) + if (smi_sources[i].type == source) + return smi_sources[i].handler; + return NULL; } diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 5ecbbd5dbf5..63e8b94b5d7 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -259,3 +259,125 @@ Method (_OSC, 4) Return (Arg3) } + +Scope (_GPE) +{ + Method (_L09, 0, NotSerialized) + { + If ((RP1D == Zero)) + { + \_SB.PCI0.RP01.HPME () + Notify (\_SB.PCI0.RP01, 0x02) + } + + If ((RP2D == Zero)) + { + \_SB.PCI0.RP02.HPME () + Notify (\_SB.PCI0.RP02, 0x02) + } + + If ((RP3D == Zero)) + { + \_SB.PCI0.RP03.HPME () + Notify (\_SB.PCI0.RP03, 0x02) + } + + If ((RP4D == Zero)) + { + \_SB.PCI0.RP04.HPME () + Notify (\_SB.PCI0.RP04, 0x02) + } + + If ((RP5D == Zero)) + { + \_SB.PCI0.RP05.HPME () + Notify (\_SB.PCI0.RP05, 0x02) + } + + If ((RP6D == Zero)) + { + \_SB.PCI0.RP06.HPME () + Notify (\_SB.PCI0.RP06, 0x02) + } + + If ((RP7D == Zero)) + { + \_SB.PCI0.RP07.HPME () + Notify (\_SB.PCI0.RP07, 0x02) + } + + If ((RP8D == Zero)) + { + \_SB.PCI0.RP08.HPME () + Notify (\_SB.PCI0.RP08, 0x02) + } + + Notify (\_SB.PCI0.PEGP, 0x02) + Notify (\_SB.PCI0.PEGP.DEV0, 0x02) + Notify (\_SB.PCI0.PEG1, 0x02) + Notify (\_SB.PCI0.PEG1.DEV0, 0x02) + Notify (\_SB.PCI0.PEG2, 0x02) + Notify (\_SB.PCI0.PEG2.DEV0, 0x02) + Notify (\_SB.PCI0.PEG6, 0x02) + Notify (\_SB.PCI0.PEG6.DEV0, 0x02) + } + + Method (_L01, 0, NotSerialized) + { + If (((RP1D == Zero) && \_SB.PCI0.RP01.HPCS)) + { + If (\_SB.PCI0.RP01.HPEV () == 1) { + Notify (\_SB.PCI0.RP01, 0) + } + } + + If (((RP2D == Zero) && \_SB.PCI0.RP02.HPCS)) + { + If (\_SB.PCI0.RP02.HPEV () == 1) { + Notify (\_SB.PCI0.RP02, 0) + } + } + + If (((RP3D == Zero) && \_SB.PCI0.RP03.HPCS)) + { + If (\_SB.PCI0.RP03.HPEV () == 1) { + Notify (\_SB.PCI0.RP03, 0) + } + } + + If (((RP4D == Zero) && \_SB.PCI0.RP04.HPCS)) + { + If (\_SB.PCI0.RP04.HPEV () == 1) { + Notify (\_SB.PCI0.RP04, 0) + } + } + + If (((RP5D == Zero) && \_SB.PCI0.RP05.HPCS)) + { + If (\_SB.PCI0.RP05.HPEV () == 1) { + Notify (\_SB.PCI0.RP05, 0) + } + } + + If (((RP6D == Zero) && \_SB.PCI0.RP06.HPCS)) + { + If (\_SB.PCI0.RP06.HPEV () == 1) { + Notify (\_SB.PCI0.RP06, 0) + } + } + + If (((RP7D == Zero) && \_SB.PCI0.RP07.HPCS)) + { + If (\_SB.PCI0.RP07.HPEV () == 1) { + Notify (\_SB.PCI0.RP07, 0) + } + } + + If (((RP8D == Zero) && \_SB.PCI0.RP08.HPCS)) + { + If (\_SB.PCI0.RP08.HPEV () == 1) { + Notify (\_SB.PCI0.RP08, 0) + } + } + } +} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 67d883ad485..fa05a4379ec 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -159,8 +160,7 @@ static void pch_power_options(struct device *dev) * * If the option is not existent (Laptops), use Kconfig setting. */ - const unsigned int pwr_on = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); + const unsigned int pwr_on = dasharo_get_power_on_after_fail(); reg16 = pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; diff --git a/src/southbridge/intel/common/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl index 988c8170e98..d97bc1272b1 100644 --- a/src/southbridge/intel/common/acpi/pcie_port.asl +++ b/src/southbridge/intel/common/acpi/pcie_port.asl @@ -5,13 +5,69 @@ OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) Field (RPCS, AnyAcc, NoLock, Preserve) { + Offset (0x10), + L0SE, 1, Offset (0x4c), // Link Capabilities , 24, RPPN, 8, // Root Port Number Offset (0x5A), , 3, - PDC, 1, + PDCX, 1, + , 2, + PDSX, 1, + Offset (0x60), // RSTS - Root Status Register + , 16, + PSPX, 1, // PME Status + Offset (0xDB), // MPC - Miscellaneous Port Configuration Register + , 6, + HPEX, 1, // Hot Plug SCI Enable + PMEX, 1, // Power Management SCI Enable +} + +Field (RPCS, AnyAcc, NoLock, WriteAsZeros) +{ Offset (0xDF), , 6, - HPCS, 1, + HPCS, 1, // Hot Plug SCI Status + PMCS, 1, // Power Management SCI Status +} + +Method (HPME, 0, Serialized) { + If (PMCS == 1) { + Notify (PXSX, 0x2) + PMCS = 1 // clear rootport's PME SCI status + PSPX = 1 // consume one pending PME notification to prevent it from blocking the queue + } +} + +Method (HPEV, 0, Serialized) { + Sleep (0x64) + If (PDCX == 1) + { + PDCX = 1 + HPCS = 1 + If (PDSX == 0) + { + L0SE = 0 + } + Return (1) + } + Else + { + HPCS = 1 + Return (0) + } +} + +Name (_HPP, Package (0x04) { + 0x08, + 0x40, + 1, + 0 +}) + +Device(PXSX) +{ + Name (_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 95eda31c9d2..055202fbf79 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -24,6 +24,14 @@ config IFD_BIN_PATH default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/descriptor.bin" depends on HAVE_IFD_BIN +config IFDTOOL_DISABLE_ME + bool "Set AltMeDisable/HAP bit with ifdtool" + default n + depends on HAVE_IFD_BIN + help + Uses ifdtool to set AltMeDisable/HAP in Intel Flash Descriptor binary + if added to the build. + config HAVE_ME_BIN bool "Add Intel ME/TXE firmware" depends on HAVE_IFD_BIN @@ -107,6 +115,47 @@ config USE_ME_CLEANER comment "Please test coreboot with the original, unmodified ME firmware before using me_cleaner" depends on USE_ME_CLEANER +config HAVE_INTEL_ME_HAP + bool + default n + help + SoC should select this option if it support disablign ME with HAP bit. + +choice + prompt "Default ME state option value" + default INTEL_ME_ENABLED + help + Provides a default for the power state the system should + go into after G3 (power loss). On many boards this can be + overridden by an NVRAM option. + +config INTEL_ME_DISABLED_HECI + bool "ME disabled (soft)" + help + Choose this option if you want to put ME into soft disabled state via + HECI by default. + +config INTEL_ME_DISABLED_HAP + bool "ME disabled (HAP)" + depends on HAVE_INTEL_ME_HAP + help + Choose this option if you want to put ME into HAP disabled state by + default. + +config INTEL_ME_ENABLED + bool "ME enabled" + help + Choose this option if you want to keep ME enabled by default. + You can always set ME to disabled state via setup option + +endchoice + +config INTEL_ME_DEFAULT_STATE + int + default 2 if INTEL_ME_DISABLED_HAP || IFDTOOL_DISABLE_ME + default 1 if INTEL_ME_DISABLED_HECI + default 0 + config ME_CLEANER_ARGS string depends on USE_ME_CLEANER diff --git a/src/southbridge/intel/common/firmware/Makefile.mk b/src/southbridge/intel/common/firmware/Makefile.mk index 1425d5a352d..a7431902c45 100644 --- a/src/southbridge/intel/common/firmware/Makefile.mk +++ b/src/southbridge/intel/common/firmware/Makefile.mk @@ -26,10 +26,14 @@ endif add_intel_firmware: $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) ifeq ($(CONFIG_HAVE_ME_BIN),y) -OBJ_ME_BIN := $(obj)/me.bin - ifneq ($(CONFIG_STITCH_ME_BIN),y) +OBJ_ME_BIN := $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) + +else + +OBJ_ME_BIN := $(obj)/me.bin + $(OBJ_ME_BIN): $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) cp $< $@ @@ -48,6 +52,14 @@ add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_IFDTOOL_DISABLE_ME),y) + printf " IFDTOOL set AltMeDisable/HAP bit\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + --altmedisable 1 \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y) printf " IFDTOOL validate IFD against FMAP\n" $(objutil)/ifdtool/ifdtool \ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 798f2f13876..6a7e13441f3 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -99,8 +100,7 @@ static int power_on_after_fail(void) u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - const unsigned int s5pwr = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); + const unsigned int s5pwr = dasharo_get_power_on_after_fail(); outb(tmp70, 0x70); outb(tmp72, 0x72); @@ -249,12 +249,30 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } +static bool spi_get_wp(void) +{ + return !(pci_read_config8(PCI_DEV(0, 31, 0), 0xdc) & 1); +} + +static void spi_set_wp(bool enable) +{ + uint8_t bios_cntl = pci_read_config8(PCI_DEV(0, 31, 0), 0xdc); + + if (enable) + bios_cntl &= ~1; + else + bios_cntl |= 1; + + pci_write_config8(PCI_DEV(0, 31, 0), 0xdc, bios_cntl); +} + static void southbridge_smi_store(void) { u8 sub_command, ret; em64t101_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); uintptr_t reg_rbx; + bool wp_enabled; if (!io_smi) return; @@ -264,9 +282,16 @@ static void southbridge_smi_store(void) /* Parameter buffer in EBX */ reg_rbx = (uintptr_t)io_smi->rbx; + wp_enabled = spi_get_wp(); + + spi_set_wp(false); + /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)reg_rbx); io_smi->rax = ret; + + if (wp_enabled) + spi_set_wp(true); } static int mainboard_finalized = 0; @@ -375,7 +400,7 @@ static void southbridge_smi_tco(void) bios_cntl = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xdc); - if (bios_cntl & 1) { + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted() && (bios_cntl & 1)) { /* BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS */ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 068062bae0e..66b1eca02ab 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1102,7 +1103,7 @@ void spi_finalize_ops(void) } writew_(optype, cntlr.optype); - spi_set_smm_only_flashing(CONFIG(BOOTMEDIA_SMM_BWP)); + spi_set_smm_only_flashing(is_smm_bwp_permitted()); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) diff --git a/src/superio/ite/it8613e/acpi/superio.asl b/src/superio/ite/it8613e/acpi/superio.asl new file mode 100644 index 00000000000..67d4931e23a --- /dev/null +++ b/src/superio/ite/it8613e/acpi/superio.asl @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8613E SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x1 UARTA Implemented, untested + * 0x4 EC Not implemented + * 0x5 KBC Implemented, untested + * 0x6 MOUSE Implemented, untested + * 0x7 GPIO Not implemented + * 0xa CIR Not implemented + * + + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * IT8613E_SHOW_UARTA If defined, UARTA will be exposed. + * IT8613E_SHOW_KBC If defined, the KBC will be exposed. + * IT8613E_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME IT8613E +#include + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define CONFIGURE_CONTROL CCTL + +Device (SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("ITE IT8613E Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex (CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + CONFIGURE_CONTROL, 8, /* Global configure control */ + + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x01 + #define PNP_ENTER_MAGIC_3RD 0x55 +#if SUPERIO_PNP_BASE == 0x2e + #define PNP_ENTER_MAGIC_4TH 0x55 +#else + #define PNP_ENTER_MAGIC_4TH 0xaa +#endif + #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL + #define PNP_EXIT_SPECIAL_VAL 0x02 + #include + +#ifdef IT8613E_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #include +#endif + +#ifdef IT8613E_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 +#ifdef IT8613E_SHOW_PS2M + #define SUPERIO_KBC_PS2LDN 6 +#endif + #include +#endif +} diff --git a/src/superio/nuvoton/nct6687d/Makefile.mk b/src/superio/nuvoton/nct6687d/Makefile.mk index d4785f726e6..899cf5daec1 100644 --- a/src/superio/nuvoton/nct6687d/Makefile.mk +++ b/src/superio/nuvoton/nct6687d/Makefile.mk @@ -1,3 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later +bootblock-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c +romstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_hwm.c ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += superio.c diff --git a/src/superio/nuvoton/nct6687d/chip.h b/src/superio/nuvoton/nct6687d/chip.h new file mode 100644 index 00000000000..edd0deb23a3 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/chip.h @@ -0,0 +1,361 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT6687D_CHIP_H +#define SUPERIO_NUVOTON_NCT6687D_CHIP_H + +#include + +#define MAX_TEMP_SPEED_LEVELS 7 +#define MAX_TEMP_SRC 4 +#define MAX_NUM_FANS 10 +#define MAX_NUM_SENSORS 32 +#define MAX_WEIGHT_POINTS 8 +#define MAX_DTS_CTL_POINTS 5 + +enum nct6687d_sensor_src_select { + /* TIN sources */ + SENSOR_DISABLE = 0x00, + SENSOR_LOCAL = 0x01, + TD0P_CURRENT_MODE = 0x02, + TD1P_CURRENT_MODE = 0x03, + TD2P_CURRENT_MODE = 0x04, + TD0P_VOLTAGE_MODE = 0x05, + TD1P_VOLTAGE_MODE = 0x06, + TD2P_VOLTAGE_MODE = 0x07, + THERMISTOR14 = 0x08, + THERMISTOR15 = 0x09, + THERMISTOR16 = 0x0A, + THERMISTOR0 = 0x0B, + THERMISTOR1 = 0x0C, + THERMISTOR2 = 0x0D, + THERMISTOR3 = 0x0E, + THERMISTOR4 = 0x0F, + THERMISTOR5 = 0x10, + THERMISTOR6 = 0x11, + THERMISTOR7 = 0x12, + THERMISTOR8 = 0x13, + THERMISTOR9 = 0x14, + THERMISTOR10 = 0x15, + THERMISTOR11 = 0x16, + THERMISTOR12 = 0x17, + THERMISTOR13 = 0x18, + PECI_AGENT0_DOMAIN0 = 0x20, + PECI_AGENT1_DOMAIN0 = 0x21, + PECI_AGENT2_DOMAIN0 = 0x22, + PECI_AGENT3_DOMAIN0 = 0x23, + PECI_AGENT0_DOMAIN1 = 0x24, + PECI_AGENT1_DOMAIN1 = 0x25, + PECI_AGENT2_DOMAIN1 = 0x26, + PECI_AGENT3_DOMAIN1 = 0x27, + PECI_DIMM_TMP0 = 0x28, + PECI_DIMM_TMP1 = 0x29, + PECI_DIMM_TMP2 = 0x2A, + PECI_DIMM_TMP3 = 0x2B, + PCH_CPU = 0x30, + PCH_CHIP = 0x31, + PCH_CHIP_CPU_MAX = 0x32, + PCH_MCH = 0x33, + PCH_DIMM0 = 0x34, + PCH_DIMM1 = 0x35, + PCH_DIMM2 = 0x36, + PCH_DIMM3 = 0x37, + SMBUS_THERMAL_SENSOR0 = 0x38, + SMBUS_THERMAL_SENSOR1 = 0x39, + SMBUS_THERMAL_SENSOR2 = 0x3A, + SMBUS_THERMAL_SENSOR3 = 0x3B, + SMBUS_THERMAL_SENSOR4 = 0x3C, + SMBUS_THERMAL_SENSOR5 = 0x3D, + DIMM_THERMAL_SENSOR0 = 0x3E, + DIMM_THERMAL_SENSOR1 = 0x3F, + DIMM_THERMAL_SENSOR2 = 0x40, + DIMM_THERMAL_SENSOR3 = 0x41, + AMD_TSI_ADDRESS_0x90 = 0x42, + AMD_TSI_ADDRESS_0x92 = 0x43, + AMD_TSI_ADDRESS_0x94 = 0x44, + AMD_TSI_ADDRESS_0x96 = 0x45, + AMD_TSI_ADDRESS_0x98 = 0x46, + AMD_TSI_ADDRESS_0x9A = 0x47, + AMD_TSI_ADDRESS_0x9C = 0x48, + AMD_TSI_ADDRESS_0x9D = 0x49, + VIRTUAL_TEMPIN0 = 0x50, + VIRTUAL_TEMPIN1 = 0x51, + VIRTUAL_TEMPIN2 = 0x52, + VIRTUAL_TEMPIN3 = 0x53, + VIRTUAL_TEMPIN4 = 0x54, + VIRTUAL_TEMPIN5 = 0x55, + VIRTUAL_TEMPIN6 = 0x56, + VIRTUAL_TEMPIN7= 0x57, + /* VIN soruces */ + VCC= 0x60, + VSB= 0x61, + AVSB = 0x62, + VTT = 0x63, + VBAT = 0x64, + VREF = 0x65, + VIN0 = 0x66, + VIN1 = 0x67, + VIN2 = 0x68, + VIN3 = 0x69, + VIN4 = 0x6A, + VIN5 = 0x6B, + VIN6 = 0x6C, + VIN7 = 0x6D, + VIN8 = 0x6E, + VIN9 = 0x6F, + VIN10 = 0x70, + VIN11 = 0x71, + VIN12 = 0x72, + VIN13 = 0x73, + VIN14 = 0x74, + VIN15 = 0x75, + VIN16 = 0x76, +}; + +enum nct6687d_peci_speed { + PECI_2MHZ = 0, + PECI_1200KHZ, + PECI_800KHZ, + PECI_400KHZ, +}; + +enum nct6687d_baud_rate { + BAUD_12_5K = 0, + BAUD_25K, + BAUD_50K, + BAUD_100K, + BAUD_200K, + BAUD_400K, + BAUD_800K, + BAUD_1200K, +}; + +enum nct6687d_fan_mode { + FAN_IGNORE = 0, + FAN_THERMAL_CRUISE, + FAN_SPEED_CRUISE, + FAN_SMART_FAN_IV, + FAN_PID_CONTROL, + FAN_MODE_MANUAL, +}; + +enum nct6687d_tach_pwm_sel { + TACH_PWM0 = 0, + TACH_PWM1, + TACH_PWM2, + TACH_PWM3, + TACH_PWM4, + TACH_PWM5, + TACH_PWM6, + TACH_PWM7, + TACH_PWM8, + TACH_PWM9, + TACH_PWM10, + TACH_PWM11, + TACH_PWM12, + TACH_PWM13, + TACH_PWM14, + TACH_PWM15, + TACH_PWM16, + TACH_PWM17, + TACH_PWM18, + TACH_PWM19, + TACH_PWM20, + TACH_PWM21, + TACH_PWM22, + TACH_PWM23, +}; + +enum nct6687d_fan_unit_sel { + FAN_PWM = 0, + FAN_RPM, +}; + +enum nct6687d_fast_track_weight { + WEIGHT_DIV_1 = 0, + WEIGHT_DIV_2, + WEIGHT_DIV_4, + WEIGHT_DIV_8, + WEIGHT_DIV_16, + WEIGHT_DIV_32, + WEIGHT_DIV_64, +}; + +struct nct6687d_pch_smbus_sensor { + bool sensor_en; + uint8_t sensor_idx; + bool report_one_byte; + uint8_t port_sel; + enum nct6687d_baud_rate baud_rate; + uint8_t sensor_addr; + uint8_t sensor_cmd; +}; + +struct nct6687d_dts_sensor_config { + uint8_t ambient_temp[MAX_DTS_CTL_POINTS]; + uint16_t rpm_start_point[MAX_DTS_CTL_POINTS]; + uint16_t rpm_end_point[MAX_DTS_CTL_POINTS]; + uint8_t temp_start; + uint8_t temp_end; + uint16_t max_speed; + bool peci_adjust; + uint8_t peci_agent_idx; +}; + +struct nct6687d_dts2_sensor_config { + int8_t target_margin; + uint8_t target_margin_tolerance; + int8_t t_control; + int8_t t_control_offset; + uint16_t step_speed; + uint16_t min_speed; + /* Unit is 1s */ + uint8_t delay_time; + uint8_t divisor; +}; + +struct nct6687d_smart_fan_iv_config { + uint8_t temp_src[MAX_TEMP_SRC]; + uint8_t temp_levels[MAX_TEMP_SPEED_LEVELS]; + uint16_t speed_levels[MAX_TEMP_SPEED_LEVELS]; + uint8_t temp_hystheresis; + uint8_t temp_cut_off; + uint8_t cut_off_delay; + /* Time in 100ms units */ + uint8_t step_up_time; + uint8_t step_down_time; +}; + +struct nct6687d_manual_fan_config { + uint8_t manual_duty; +}; + +struct nct6687d_fan_thermal_cruise_config { + bool keep_min_fan_output; + uint8_t target_temp; + uint8_t temp_tolerance; + uint8_t initial_value; + uint8_t stop_value; + /* Time in 100ms units */ + uint8_t stop_time; + uint8_t step_up_time; + uint8_t step_down_time; +}; + +struct nct6687d_fan_speed_cruise_config { + uint16_t target_rpm; + uint16_t rpm_tolerance; + /* Time in 100ms units */ + uint8_t step_up_time; + uint8_t step_down_time; +}; + +struct nct6687d_ambient_floor_fan_config { + /* Units is RPM */ + uint16_t minout_start; + uint16_t minout_end; + uint16_t minout_max; +}; + +struct nct6687d_ambient_floor_config { + uint8_t temp_start; + uint8_t temp_end; +}; + +struct nct6687d_smart_tracking_config { + uint8_t rpm_tolerance_low; + uint8_t rpm_tolerance_mid; + uint8_t rpm_tolerance_high; + + uint16_t speed_boundary_low; + uint16_t speed_boundary_high; + + /* Step tracking setting */ + uint8_t step_up; + uint8_t step_down; + + /* Fast tracking settings */ + uint8_t temp_boundary; + + enum nct6687d_fast_track_weight weight_up_low; + enum nct6687d_fast_track_weight weight_up_mid; + enum nct6687d_fast_track_weight weight_up_high; + enum nct6687d_fast_track_weight weight_down_low; + enum nct6687d_fast_track_weight weight_down_mid; + enum nct6687d_fast_track_weight weight_down_high; + + uint8_t duty_step_low; + uint8_t duty_step_mid; + uint8_t duty_step_high; + + /* Markup tracking setting */ + uint8_t ambient_temp_boundary; + uint8_t weight_val; +}; + + +struct nct6687d_fan_config { + enum nct6687d_fan_mode mode; + enum nct6687d_fan_unit_sel unit_sel; + enum nct6687d_tach_pwm_sel fanin_sel; + enum nct6687d_tach_pwm_sel fanout_sel; + + struct nct6687d_smart_fan_iv_config smart_fan; + struct nct6687d_manual_fan_config manual_fan; + struct nct6687d_fan_thermal_cruise_config thermal_cruise_fan; + struct nct6687d_fan_speed_cruise_config speed_cruise_fan; + + /* Fan ALG_FUNCTRL */ + uint8_t fan_alg_weight; + + uint8_t crit_temp; + uint8_t crit_temp_tolerance; + + uint8_t temp_err_duty; + + bool dts1_en; + bool dts2_en; + bool dts_ub_en; + + /* Fan FUN_CTRL */ + bool smart_tracking_en; + bool fast_tracking_en; + bool markup_tracking_en; + + bool ambient_floor_en; + struct nct6687d_ambient_floor_fan_config amb_floor_fan_cfg; + + uint8_t startup_duty; + uint8_t manual_offset; + uint8_t min_duty; +}; + +struct superio_nuvoton_nct6687d_config { + struct nct6687d_fan_config fans[MAX_NUM_FANS]; + enum nct6687d_sensor_src_select sensors[MAX_NUM_SENSORS]; + + enum nct6687d_peci_speed peci_speed; + + struct nct6687d_pch_smbus_sensor smbus_sensor; + struct nct6687d_dts_sensor_config dts_sensor; + struct nct6687d_dts2_sensor_config dts2_sensor; + + struct nct6687d_ambient_floor_config ambient_floor; + struct nct6687d_smart_tracking_config smart_tracking; + + uint8_t fan_default_val; +}; + +#define FAN1 fans[0] +#define FAN2 fans[1] +#define FAN3 fans[2] +#define FAN4 fans[3] +#define FAN5 fans[4] +#define FAN6 fans[5] +#define FAN7 fans[6] +#define FAN8 fans[7] +#define FAN9 fans[8] +#define FAN10 fans[9] + +void nct6687d_hwm_init(uint16_t hwm_base, const struct superio_nuvoton_nct6687d_config *conf); + +#endif /* SUPERIO_NUVOTON_NCT6687D_CHIP_H */ diff --git a/src/superio/nuvoton/nct6687d/nct6687d_ec.c b/src/superio/nuvoton/nct6687d/nct6687d_ec.c new file mode 100644 index 00000000000..0b25b164b46 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d_ec.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +#include "nct6687d_ec.h" + +void nct6687d_ec_write_page(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value) +{ + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + outb(index, iobase + EC_PORT0_INDEX); + outb(value, iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); +} + +void nct6687d_ec_write_page_ff(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value) +{ + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + /* Extra 0xff to the index register */ + outb(0xff, iobase + EC_PORT0_INDEX); + outb(index, iobase + EC_PORT0_INDEX); + outb(value, iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); +} + +void nct6687d_ec_and_or_page(uint16_t iobase, uint8_t page, uint8_t index, + uint8_t and_mask, uint8_t or_mask) +{ + uint8_t val; + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + outb(index, iobase + EC_PORT0_INDEX); + val = inb(iobase + EC_PORT0_DATA); + val &= and_mask; + val |= or_mask; + outb(val, iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); +} + +void nct6687d_ec_and_or_page_ff(uint16_t iobase, uint8_t page, uint8_t index, + uint8_t and_mask, uint8_t or_mask) +{ + uint8_t val; + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + /* Extra 0xff to the index register */ + outb(0xff, iobase + EC_PORT0_INDEX); + outb(index, iobase + EC_PORT0_INDEX); + val = inb(iobase + EC_PORT0_DATA); + val &= and_mask; + val |= or_mask; + outb(val, iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); +} + +uint8_t nct6687d_ec_read_page(uint16_t iobase, uint8_t page, uint8_t index) +{ + uint8_t value; + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + outb(index, iobase + EC_PORT0_INDEX); + value = inb(iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); + + return value; +} diff --git a/src/superio/nuvoton/nct6687d/nct6687d_ec.h b/src/superio/nuvoton/nct6687d/nct6687d_ec.h new file mode 100644 index 00000000000..d32f32c4678 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d_ec.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT6687D_EC_H +#define SUPERIO_NUVOTON_NCT6687D_EC_H + +#include + +/* Offsets in the EC IO base. Port0 for firmware use, Port1 for software use */ +#define EC_PORT0_PAGE 0 +#define EC_PORT0_INDEX 1 +#define EC_PORT0_DATA 2 +#define EC_PORT0_HOST_IF_EVENT 3 + +#define EC_PORT1_PAGE 4 +#define EC_PORT1_INDEX 5 +#define EC_PORT1_DATA 6 +#define EC_PORT1_HOST_IF_EVENT 7 + +void nct6687d_ec_write_page(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value); +void nct6687d_ec_write_page_ff(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value); +void nct6687d_ec_and_or_page(uint16_t iobase, uint8_t page, uint8_t index, + uint8_t and_mask, uint8_t or_mask); +void nct6687d_ec_and_or_page_ff(uint16_t iobase, uint8_t page, uint8_t index, + uint8_t and_mask, uint8_t or_mask); +uint8_t nct6687d_ec_read_page(uint16_t iobase, uint8_t page, uint8_t index); + +#endif /* SUPERIO_NUVOTON_NCT6687D_EC_H */ diff --git a/src/superio/nuvoton/nct6687d/nct6687d_hwm.c b/src/superio/nuvoton/nct6687d/nct6687d_hwm.c new file mode 100644 index 00000000000..54d37cb20ae --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d_hwm.c @@ -0,0 +1,960 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +#include "chip.h" +#include "nct6687d_hwm.h" + +uint16_t nct6687d_hwm_base = 0; + +static bool check_cond(const bool cond, const char* error) +{ + if (!cond) + printk(BIOS_ERR, "NCT6687D: %s\n", error); + + return !cond; +} + +static inline void print_status_bit(const char* status, const bool cond) +{ + printk(BIOS_DEBUG, "\t%-45s: %s\n", status, cond ? "yes" : "no"); +} + +static void print_fan_engine_status(void) +{ + uint8_t fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + + printk(BIOS_DEBUG, "NCT6687D: Fan Engine Status:\n"); + print_status_bit("PECI configuration adjusted", fan_eng_sts & FAN_PECI_CFG_ADJUSTED); + print_status_bit("All enabled fan channels processed", + fan_eng_sts & FAN_UNFINISHED_FLAG); + print_status_bit("Configuration phase", fan_eng_sts & FAN_CFG_PHASE); + print_status_bit("Configuration invalid", fan_eng_sts & FAN_CFG_INVALID); + print_status_bit("Configuration check done", fan_eng_sts & FAN_CFG_CHECK_DONE); + print_status_bit("Configuration locked", fan_eng_sts & FAN_CFG_LOCK); + printk(BIOS_DEBUG, "Fans in automatic mode driven by %s register\n", + (fan_eng_sts & FAN_DRIVE_BY_DEFAULT_VAL) ? "DEFAULT_VAL" : "MOD_SEL"); +} + +static bool unlock_fan_register_set(void) +{ + uint8_t fan_eng_sts; + bool done = false; + unsigned int i; + + fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + + if (!(fan_eng_sts & FAN_CFG_LOCK) && (fan_eng_sts & FAN_CFG_PHASE)) + return true; + + for (i = 1000; i > 0; i--) { + /* Wait until EC exits config phase and config request is clear */ + if ((hwm_reg_read(FAN_ENGINE_STS_REG) & FAN_CFG_PHASE) == 0 && + (hwm_reg_read(FAN_CFG_CTRL_REG) & FAN_CFG_REQUEST) == 0) { + done = true; + break; + } + mdelay(1); + } + + if (!done) { + printk(BIOS_WARNING, "Timeout waiting for EC to exit config phase or clear" + "config request\n"); + print_fan_engine_status(); + return false; + } + + done = false; + + hwm_reg_write(FAN_CFG_CTRL_REG, FAN_CFG_REQUEST); + + for (i = 1000; i > 0; i--) { + /* Wait until EC unlock the register set */ + if ((hwm_reg_read(FAN_ENGINE_STS_REG) & FAN_CFG_LOCK) == 0) { + done = true; + break; + } + mdelay(1); + } + + if (!done) { + printk(BIOS_WARNING, "Timeout waiting for EC to unlock the fan registers\n"); + print_fan_engine_status(); + return false; + } + + return true; +} + +static void print_last_err(uint8_t error_code) +{ + uint8_t debug_level = BIOS_WARNING; + uint8_t last_err_code = hwm_reg_read(FAN_LAST_ERROR_CODE_REG); + + if (last_err_code == FAN_NO_ERROR) { + printk(BIOS_DEBUG, "No error occurred.\n"); + return; + } + + /* Lower the debug level if it is an error we care about */ + if (last_err_code == error_code) + debug_level = BIOS_ERR; + + switch (last_err_code) { + case FAN_ERR_MODE_SELECT: + printk(debug_level, "Mode Select invalid configuration\n"); + break; + case FAN_ERR_CRIT_TEMP_PROTECT: + printk(debug_level, "Critical Temperature Protection invalid configuration\n"); + break; + case FAN_ERR_ITL_FAN_CONTROL: + printk(debug_level, "Intel DTS Sensor invalid configuration\n"); + break; + case FAN_ERR_SMART_TRACKING: + printk(debug_level, "Smart Tracking invalid configuration\n"); + break; + case FAN_ERR_THERMAL_CRUISE: + printk(debug_level, "Thermal Cruise invalid configuration\n"); + break; + case FAN_ERR_SPEED_CRUISE: + printk(debug_level, "Speed Cruise invalid configuration\n"); + break; + case FAN_ERR_SMART_FAN_IV: + printk(debug_level, "Smart Fan IV invalid configuration\n"); + break; + case FAN_ERR_PID_CONTROL: + printk(debug_level, "PID control invalid configuration\n"); + break; + default: + printk(debug_level, "Unkown fan configuration error %02x\n", last_err_code); + break; + } +} + +static void lock_fan_register_set_and_check(uint8_t error_code) +{ + uint8_t fan_eng_sts; + bool done = false; + unsigned int i; + + fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + + if (fan_eng_sts & FAN_CFG_LOCK || !(fan_eng_sts & FAN_CFG_PHASE)) { + printk(BIOS_DEBUG, "Fan register set already locked or not in config phase\n"); + return; + } + + hwm_reg_write(FAN_CFG_CTRL_REG, FAN_CFG_DONE); + + for (i = 1000; i > 0; i--) { + fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + /* Wait until EC checks the configuration */ + if (fan_eng_sts & FAN_CFG_CHECK_DONE) { + done = true; + break; + } + mdelay(1); + } + + if (!done) { + printk(BIOS_WARNING, "Timeout waiting for configuration check done\n"); + print_fan_engine_status(); + return; + } + + fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + + if (fan_eng_sts & FAN_CFG_INVALID) { + printk(BIOS_WARNING, "NCT6687D: Configuration error ocurred\n"); + print_last_err(error_code); + } + + if (!(fan_eng_sts & FAN_CFG_LOCK)) { + printk(BIOS_WARNING, "NCT6687D: Configuration registers did not lock\n"); + print_fan_engine_status(); + } +} + +static void init_pch_smbus_sensor(const struct nct6687d_pch_smbus_sensor *smbus_sensor) +{ + if (!smbus_sensor->sensor_addr || !smbus_sensor->sensor_cmd) { + printk(BIOS_ERR, "NCT6687D SMBus sensor CMD or ADDR missing!\n"); + return; + } + + /* Enable SMBUS first */ + hwm_reg_write(SMBUS_MASTER_CFG2_REG, 0x04); + hwm_reg_write(SMBUS_MASTER_BAUD_RATE_SEL_REG, SMB_MASTER_BAUD_100K); + hwm_reg_set_bits(SMBUS_MASTER_CFG1_REG, SMB_MASTER_EN); + + hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_BAUD_SEL_MASK, + smbus_sensor->baud_rate & PCH_BAUD_SEL_MASK); + hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_PORT_SEL_MASK, + PCH_THERMAL_PORT(smbus_sensor->port_sel) & PCH_PORT_SEL_MASK); + + if (smbus_sensor->report_one_byte) + hwm_reg_set_bits(PCH_THERMAL_DATA_CFG_REG, PCH_ONE_BYTE_REPORT); + else + hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_ONE_BYTE_REPORT & 0xff, 0); + + + hwm_reg_write(PCH_DEVICE_ADDR_REG, smbus_sensor->sensor_addr); + hwm_reg_write(PCH_THERMAL_CMD_REG, smbus_sensor->sensor_cmd); +} + +static void init_sensors(const struct superio_nuvoton_nct6687d_config *conf) +{ + unsigned int i; + bool peci_en = false; + const enum nct6687d_sensor_src_select *sensors = conf->sensors; + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping sensors programming\n"); + return; + } + + printk(BIOS_DEBUG, "NCT6687D programming sensors\n"); + /* Start monitoring */ + hwm_reg_set_bits(HWM_CONFIG_REG, HWM_EN); + + for (i = 0; i < MAX_NUM_SENSORS; i++) { + hwm_reg_write(SENSOR_CFG_REG(i), sensors[i] & SENSOR_SRC_SEL_MASK); + + if (sensors[i] >= PECI_AGENT0_DOMAIN0 && + sensors[i] <= PECI_AGENT3_DOMAIN1) { + hwm_reg_and_or(PECI_AGENT_EN_REG, ~PECI_AGENT_EN_MASK, + PECI_AGENT_EN(sensors[i] & 0x3)); + peci_en = true; + } + + /* Only PCH SMBus sensor supported right now */ + if (sensors[i] >= PCH_CPU && sensors[i] <= PCH_DIMM3 && + i == conf->smbus_sensor.sensor_idx && + conf->smbus_sensor.sensor_en) { + init_pch_smbus_sensor(&conf->smbus_sensor); + } + } + + if (peci_en) { + hwm_reg_and_or(PECI_CFG_REG, PECI_SPEED_SEL_MASK, + conf->peci_speed & PECI_SPEED_SEL_MASK); + hwm_reg_set_bits(PECI_CFG_REG, PECI_AGENT_INIT | PECI_EN); + } + + lock_fan_register_set_and_check(FAN_NO_ERROR); +} + +static bool intel_dts_sensor_control_point_check(const struct nct6687d_dts_sensor_config *dts, + unsigned int i) +{ + bool failure = false; + + failure |= check_cond(dts->ambient_temp[i] <= 127, + "DTS Sensor Ambient Temperature Levels should be <= 127"); + + if (i < MAX_DTS_CTL_POINTS - 1) { + failure |= check_cond(dts->ambient_temp[i + 1] >= dts->ambient_temp[i], + "DTS Sensor next Ambient Temperature Level must be " + "higher or equal to previous Ambient Temperature Level"); + failure |= check_cond(dts->rpm_start_point[i + 1] > dts->rpm_start_point[i], + "DTS Sensor next RPM Start Point must be higher than " + "previous RPM Start Point"); + failure |= check_cond(dts->rpm_end_point[i + 1] > dts->rpm_end_point[i], + "DTS Sensor next RPM End Point must be higher than " + "previous RPM End Point"); + } + + failure |= check_cond(dts->rpm_end_point[i] > dts->rpm_start_point[i], + "DTS Sensor RPM End Point must be higher than corresponding RPM " + "Start Point"); + + return failure; +} + +static bool intel_dts_sensor_config_check(const struct nct6687d_dts_sensor_config *dts) +{ + bool failure = false; + unsigned int i; + + failure |= check_cond(dts->temp_end > dts->temp_start, + "DTS Sensor Temperture End Point should be > " + "Temperture End Point"); + failure |= check_cond(dts->temp_start <= 127, + "DTS Sensor Temperture Start Point should be <= 127"); + failure |= check_cond(dts->temp_end <= 127, + "DTS Sensor Temperture End Point should be <= 127"); + + if (dts->peci_adjust) { + failure |= check_cond(dts->peci_agent_idx < 8, + "DTS Sensor PECI Agent Index should be < 8"); + } + + for (i = 0; i < MAX_DTS_CTL_POINTS; i++) + failure |= intel_dts_sensor_control_point_check(dts, i); + + return failure; +} + +static void init_intel_dts_sensor(const struct nct6687d_dts_sensor_config *dts) +{ + static int init_once = 0; + unsigned int i; + + if (init_once) + return; + + if (intel_dts_sensor_config_check(dts)) { + printk(BIOS_ERR, "NCT6687D DTS Sensor invalid config, " + "skipping sensor programming\n"); + return; + } + + printk(BIOS_DEBUG, "NCT6687D programming DTS sensor\n"); + + hwm_reg_write(ITL_TEMP_START_POINT_REG, dts->temp_start); + hwm_reg_write(ITL_TEMP_END_POINT_REG, dts->temp_end); + + hwm_reg_write(ITL_RPM_MAX_SPEED_HI_REG, dts->max_speed >> 8); + hwm_reg_write(ITL_RPM_MAX_SPEED_LO_REG, dts->max_speed & 0xff); + + for (i = 0; i < MAX_DTS_CTL_POINTS; i++) { + hwm_reg_write(ITL_AMB_TEMP_START_POINT_REG(i), dts->ambient_temp[i]); + hwm_reg_write(ITL_RPM_START_POINT_HI_REG(i), dts->rpm_start_point[i] >> 8); + hwm_reg_write(ITL_RPM_START_POINT_LO_REG(i), dts->rpm_start_point[i] & 0xff); + hwm_reg_write(ITL_RPM_END_POINT_HI_REG(i), dts->rpm_end_point[i] >> 8); + hwm_reg_write(ITL_RPM_END_POINT_LO_REG(i), dts->rpm_end_point[i] & 0xff); + } + + if (dts->peci_adjust) { + hwm_reg_and_or(ITL_DTS_CFG_REG, ~ITL_DTS_PECI_AGENT_IDX_SEL_MASK, + dts->peci_agent_idx & ITL_DTS_PECI_AGENT_IDX_SEL_MASK); + hwm_reg_set_bits(ITL_DTS_CFG_REG, ITL_DTS_PECI_CFG_ADJUSTMENT); + } + + init_once = 1; +} + +static void init_intel_dts2_sensor(const struct nct6687d_dts2_sensor_config *dts2) +{ + static int init_once = 0; + + if (init_once) + return; + + printk(BIOS_DEBUG, "NCT6687D programming DTS2 sensor\n"); + + hwm_reg_write(DTS2_TARGET_MARGIN_REG, (uint8_t)dts2->target_margin); + hwm_reg_write(DTS2_TCONTROL_REG, (uint8_t)dts2->t_control); + hwm_reg_write(DTS2_TCONTROL_OFFSET_REG, (uint8_t)dts2->t_control_offset); + hwm_reg_write(DTS2_TARGET_TOLERANCE_REG, dts2->target_margin_tolerance); + + hwm_reg_write(DTS2_STEP_SPEED_HI_REG, dts2->step_speed >> 8); + hwm_reg_write(DTS2_STEP_SPEED_LO_REG, dts2->step_speed & 0xff); + hwm_reg_write(DTS2_MIN_SPEED_HI_REG, dts2->min_speed >> 8); + hwm_reg_write(DTS2_MIN_SPEED_LO_REG, dts2->min_speed & 0xff); + + hwm_reg_write(DTS2_DELAY_TIME_COUNTER_REG, dts2->delay_time); + hwm_reg_write(DTS2_DIVISOR_REG, dts2->divisor); + + init_once = 1; +} + +static void lock_sensor_config(void) +{ + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping misc fan config programming\n"); + return; + } + hwm_reg_set_bits(HWM_CONFIG_REG, LOCK_SENSOR_CFG); + lock_fan_register_set_and_check(FAN_NO_ERROR); +} + +static void init_ambient_floor_alg(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + static int init_once = 0; + const struct nct6687d_ambient_floor_fan_config *amb_floor_fan; + const struct nct6687d_ambient_floor_config *amb_floor_cfg = &conf->ambient_floor; + + amb_floor_fan = &conf->fans[idx - 1].amb_floor_fan_cfg; + + printk(BIOS_DEBUG, "NCT6687D initializing ambient floor algorithm\n"); + + if (!init_once) { + hwm_reg_write(AMBIENT_FLOOR_TEMP_START_POINT_REG, amb_floor_cfg->temp_start); + hwm_reg_write(AMBIENT_FLOOR_TEMP_END_POINT_REG, amb_floor_cfg->temp_end); + init_once = 1; + } + + hwm_reg_write(FAN_AMB_FLOOR_MIN_OUT_START_REG(idx), + FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_start)); + hwm_reg_write(FAN_AMB_FLOOR_MIN_OUT_END_REG(idx), + FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_end)); + hwm_reg_write(FAN_AMB_FLOOR_MAX_OUT_REG(idx), + FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_max)); +} + +static void init_smart_tracking_alg(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + static int init_once = 0; + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_smart_tracking_config *smart_track = &conf->smart_tracking; + + printk(BIOS_DEBUG, "NCT6687D initializing smart tracking algorithm\n"); + + if (!init_once) { + hwm_reg_write(FAN_LOW_RPM_SPEED_BOUNDARY_HI_REG, + smart_track->speed_boundary_low >> 8); + hwm_reg_write(FAN_LOW_RPM_SPEED_BOUNDARY_LO_REG, + smart_track->speed_boundary_low & 0xff); + hwm_reg_write(FAN_HIGH_RPM_SPEED_BOUNDARY_HI_REG, + smart_track->speed_boundary_high >> 8); + hwm_reg_write(FAN_HIGH_RPM_SPEED_BOUNDARY_LO_REG, + smart_track->speed_boundary_high & 0xff); + hwm_reg_write(FAN_LOW_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_low); + hwm_reg_write(FAN_MID_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_mid); + hwm_reg_write(FAN_HIGH_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_high); + + hwm_reg_write(FAN_TRACKING_STEP_REG, ((smart_track->step_up & 0xf) << 4) | + (smart_track->step_down & 0xf)); + + hwm_reg_write(FAN_FAST_TRACK_TEMP_BOUNDARY_REG, smart_track->temp_boundary); + + hwm_reg_write(FAN_LOW_RPM_FAST_TRACK_WEIGHT_REG, + ((smart_track->weight_up_low & 7) << 4) | + (smart_track->weight_down_low & 7)); + hwm_reg_write(FAN_MID_RPM_FAST_TRACK_WEIGHT_REG, + ((smart_track->weight_up_mid & 7) << 4) | + (smart_track->weight_down_mid & 7)); + hwm_reg_write(FAN_HIGH_RPM_FAST_TRACK_WEIGHT_REG, + ((smart_track->weight_up_high & 7) << 4) | + (smart_track->weight_down_high & 7)); + + hwm_reg_write(FAN_LOW_RPM_FAST_TRACK_DUTY_STEP_REG, + smart_track->duty_step_low & 0xf); + hwm_reg_write(FAN_MID_RPM_FAST_TRACK_DUTY_STEP_REG, + smart_track->duty_step_mid & 0xf); + hwm_reg_write(FAN_HIGH_RPM_FAST_TRACK_DUTY_STEP_REG, + smart_track->duty_step_high & 0xf); + + hwm_reg_write(FAN_MARKUP_TRACK_AMB_TEMP_BOUNDARY_REG, + smart_track->ambient_temp_boundary); + + hwm_reg_write(FAN_MARKUP_TRACK_WEIGHT_REG, smart_track->weight_val & 7); + + init_once = 1; + } + + if (fan->fast_tracking_en) + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_FAST_TRACK_EN); + + + if (fan->markup_tracking_en) + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MARKUP_TRACK_EN); +} + +static void misc_fan_config(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping misc fan config programming\n"); + return; + } + + if (fan->fan_alg_weight) { + printk(BIOS_DEBUG, "Programming algorithm weight for FAN%d\n", idx); + hwm_reg_and_or(FAN_ALG_ENGINE_WEIGHT_VAL_REG(idx), + ~FAN_ALG_ENGINE_WEIGHT_MASK(idx), + (fan->fan_alg_weight & 0xf) << + FAN_ALG_ENGINE_WEIGHT_SHIFT(idx)); + hwm_reg_set_bits(FAN_ALG_ENGINE_WEIGHT_EN_REG(idx), + FAN_ALG_ENGINE_WEIGHT_CHANNEL_EN(idx)); + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_ALG_EN); + } + + if (fan->crit_temp) { + if (!check_cond(fan->crit_temp >= fan->crit_temp_tolerance, + "Fan Critical Temperature should be >= " + "Critical Temperature Tolerance")) { + printk(BIOS_DEBUG, "Enabling critical temperature for FAN%d\n", idx); + hwm_reg_write(FAN_CRIT_TEMP_CFG_REG(idx), fan->crit_temp & 0x7f); + if (fan->crit_temp_tolerance) + hwm_reg_write(FAN_CRIT_TEMP_TOLERANCE_REG(idx), + fan->crit_temp_tolerance & 0xf); + + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), + FAN_ALG_FUNCTRL_CRIT_TEMP_EN); + } + } + + if (fan->temp_err_duty) { + hwm_reg_write(FAN_TEMP_ERR_DUTY_VAL_REG(idx), fan->temp_err_duty); + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_TEMP_ERR); + } + + if (fan->dts1_en && fan->dts2_en) { + printk(BIOS_ERR, "DTS and DTS2 sensors can't coexist!\n"); + printk(BIOS_ERR, "Skipping DTS configuration\n"); + } else { + if (fan->dts1_en) { + init_intel_dts_sensor(&conf->dts_sensor); + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS1_EN); + } + + if (fan->dts2_en) { + init_intel_dts2_sensor(&conf->dts2_sensor); + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS2_EN); + } + } + + if (fan->dts_ub_en) + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS_UB_EN); + + + if (fan->smart_tracking_en) { + init_smart_tracking_alg(conf, idx); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_SMART_TRACK_EN); + } + + if (conf->fan_default_val && conf->fan_default_val <= 100) + hwm_reg_write(FAN_DEFAULT_VAL_REG, + FAN_PWM_PERCENT_TO_HEX(conf->fan_default_val)); + + /* Some registers for functionalities below are missing for fan 9 and 10 */ + if (idx > 8) { + lock_fan_register_set_and_check(FAN_NO_ERROR); + return; + } + + if (fan->ambient_floor_en) { + init_ambient_floor_alg(conf, idx); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_AMBIENT_FLOOR_EN); + } + + if (fan->startup_duty && fan->startup_duty <= 100) { + hwm_reg_write(FAN_STARTUP_DUTY_REG(idx), + FAN_PWM_PERCENT_TO_HEX(fan->startup_duty)); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_STARTUP_EN); + } + + if (fan->manual_offset) { + hwm_reg_write(FAN_MANUAL_OFFSET_REG(idx), fan->manual_offset); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MANUAL_OFFSET_EN); + } + + if (fan->min_duty && fan->min_duty <= 100) { + hwm_reg_write(FAN_MIN_DUTY_REG(idx), FAN_PWM_PERCENT_TO_HEX(fan->min_duty)); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MINDUTY_EN); + } + + lock_fan_register_set_and_check(FAN_NO_ERROR); +} + +static void set_fan_pins_and_mode(const struct nct6687d_fan_config *fan, unsigned int idx) +{ + enum nct6687d_fan_mode mode = fan->mode; + + /* FAN_IGNORE takes the mapping of manual mode to detect unitialized fans */ + if (mode == FAN_MODE_MANUAL) + mode = 0; + + hwm_reg_and_or(FAN_MODE_SEL_REG(idx), ~FAN_MODE_SEL_MASK, mode & FAN_MODE_SEL_MASK); + hwm_reg_and_or(FANIN_CFG_REG(idx), ~FANIN_PIN_SEL_MASK, + fan->fanin_sel & FANIN_PIN_SEL_MASK); + hwm_reg_set_bits(FANIN_CFG_REG(idx), FANIN_MONITOR_EN); + + hwm_reg_and_or(FANOUT_CFG_REG(idx), ~FANOUT_PIN_SEL_MASK, + fan->fanout_sel & FANOUT_PIN_SEL_MASK); + hwm_reg_set_bits(FANOUT_CFG_REG(idx), FANOUT_EN); +} + +static bool smart_fan_level_check(const struct nct6687d_fan_config *fan, + const struct nct6687d_smart_fan_iv_config *s_fan, + int i) +{ + bool failure = false; + + failure |= check_cond(s_fan->temp_levels[i] <= 127, + "Smart Fan IV Temperature Levels should be <= 127"); + if (i < MAX_TEMP_SPEED_LEVELS - 1) { + failure |= check_cond(s_fan->temp_levels[i + 1] >= s_fan->temp_levels[i], + "Smart Fan IV next Temperature Level must be higher" + " or equal to previous Temperature Level"); + failure |= check_cond(s_fan->speed_levels[i + 1] >= s_fan->speed_levels[i], + "Smart Fan IV next Speed Level must be higher or " + "equal to previous Speed Level"); + } + + if (fan->unit_sel == FAN_PWM) { + failure |= check_cond(s_fan->speed_levels[i] <= 100, + "Smart Fan IV PWM Speed Levels should be <= 100"); + } else if (fan->unit_sel == FAN_RPM) { + failure |= check_cond(s_fan->speed_levels[i] <= 0x3fff, + "Smart Fan IV RPM Speed Levels should be" + "<= 16383 RPM"); + } else { + failure |= check_cond(false, "Smart Fan IV invalid Fan Unit Selection"); + } + + return failure; + +} + +static bool smart_fan_config_check(const struct nct6687d_fan_config *fan, + const struct nct6687d_smart_fan_iv_config *s_fan) +{ + bool failure = false; + unsigned int i; + + for (i = 0; i < MAX_TEMP_SPEED_LEVELS; i++) + failure |= smart_fan_level_check(fan, s_fan, i); + + failure |= check_cond(s_fan->temp_levels[0] >= s_fan->temp_cut_off, + "Smart Fan IV Temperature Level 1 should be >= " + "Temperature Cut Off"); + failure |= check_cond(s_fan->temp_levels[0] >= + (s_fan->temp_cut_off + s_fan->temp_hystheresis), + "Smart Fan IV Temperature Level 1 should be >= " + "Temperature Cut Off + Temperature Hysteresis"); + + return failure; +} + +static void init_smart_fan(const struct superio_nuvoton_nct6687d_config *conf, unsigned int idx) +{ + unsigned int i; + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_smart_fan_iv_config *sfan = &fan->smart_fan; + + if (smart_fan_config_check(fan, sfan)) { + printk(BIOS_ERR, "NCT6687D Smart Fan IV invalid config, " + "skipping fan programming\n"); + return; + } + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping Smart Fan IV config programming\n"); + return; + } + + set_fan_pins_and_mode(fan, idx); + + if (fan->unit_sel == FAN_PWM) + hwm_reg_and_or(FAN_FUNCTION_CTRL(idx), ~FAN_FUN_UNIT_RPM & 0xff, + FAN_FUN_UNIT_PWM_DUTY); + else if (fan->unit_sel == FAN_RPM) + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); + + /* Registers start from MSB */ + for (i = 0; i < MAX_TEMP_SRC; i++) { + hwm_reg_write(FAN_MTZ_DCS_DATA_REG(MAX_TEMP_SRC - 1 - i, idx), + sfan->temp_src[i]); + } + + for (i = 0; i < MAX_TEMP_SPEED_LEVELS; i++) { + if (sfan->temp_levels[i]) + hwm_reg_write(FAN_SF4_TEMP_LVL_REG(idx, i), + sfan->temp_levels[i]); + if (sfan->speed_levels[i]) { + if (fan->unit_sel == FAN_PWM) { + hwm_reg_write(FAN_SF4_PWM_RPM_LVL_HI_REG(idx, i), 0); + hwm_reg_write(FAN_SF4_PWM_RPM_LVL_LO_REG(idx, i), + FAN_PWM_PERCENT_TO_HEX(sfan->speed_levels[i])); + } + + if (fan->unit_sel == FAN_RPM) { + hwm_reg_write(FAN_SF4_PWM_RPM_LVL_HI_REG(idx, i), + sfan->speed_levels[i] >> 8); + hwm_reg_write(FAN_SF4_PWM_RPM_LVL_LO_REG(idx, i), + sfan->speed_levels[i] & 0xff); + } + } + } + + hwm_reg_write(FAN_SF4_TEMP_OFF_HYSTHERESIS_REG(idx), sfan->temp_hystheresis); + hwm_reg_write(FAN_SF4_TEMP_CUT_OFF_REG(idx), sfan->temp_cut_off); + hwm_reg_write(FAN_SF4_TEMP_OFF_DELAY_REG(idx), sfan->cut_off_delay); + + hwm_reg_write(FAN_STEP_UP_TIME_REG(idx), sfan->step_up_time); + hwm_reg_write(FAN_STEP_DOWN_TIME_REG(idx), sfan->step_down_time); + + /* Set fan mode to automatic */ + hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0x00); + + hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); + + lock_fan_register_set_and_check(FAN_ERR_SMART_FAN_IV); + + misc_fan_config(conf, idx); +} + +static void init_manual_fan(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_manual_fan_config *manual_fan = &fan->manual_fan; + + if (manual_fan->manual_duty || manual_fan->manual_duty > 100) { + printk(BIOS_ERR, "NCT6687D: invalid duty cycle for manual fan mode\n"); + return; + } + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping manual fan config programming\n"); + return; + } + + set_fan_pins_and_mode(fan, idx); + + if (fan->unit_sel == FAN_PWM) + hwm_reg_and_or(FAN_FUNCTION_CTRL(idx), ~FAN_FUN_UNIT_RPM & 0xff, + FAN_FUN_UNIT_PWM_DUTY); + else if (fan->unit_sel == FAN_RPM) + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); + + hwm_reg_write(FAN_MANUAL_VALUE_REG(idx), + FAN_PWM_PERCENT_TO_HEX(manual_fan->manual_duty)); + + hwm_reg_set_bits(FAN_MANUAL_EN_REG(idx), FAN_MANUAL_EN(idx)); + + hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); + + lock_fan_register_set_and_check(FAN_NO_ERROR); + + misc_fan_config(conf, idx); +} + +static bool thermal_cruise_config_check(const struct nct6687d_fan_thermal_cruise_config *tc_fan) +{ + bool failure = false; + + failure |= check_cond(tc_fan->step_down_time > 0, + "Thermal Cruise Step-Down Time should be > 0"); + failure |= check_cond(tc_fan->step_up_time > 0, + "Thermal Cruise Step-Up Time should be > 0"); + failure |= check_cond(tc_fan->initial_value > tc_fan->stop_value, + "Thermal Cruise Initial value should be > Stop Value"); + failure |= check_cond(tc_fan->target_temp >= tc_fan->temp_tolerance, + "Thermal Cruise Target Temperature should be" + " >= Temperature Tolerance"); + if (tc_fan->keep_min_fan_output) { + failure |= check_cond(tc_fan->stop_value > 0, + "Thermal Cruise Stop Value should be > 0"); + } else { + failure |= check_cond(tc_fan->stop_time > 0, + "Thermal Cruise Stop Time should be > 0"); + } + + return failure; +} + +static void init_thermal_cruise_fan(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_fan_thermal_cruise_config *tc_fan = &fan->thermal_cruise_fan; + + if (thermal_cruise_config_check(tc_fan)) { + printk(BIOS_ERR, "NCT6687D Thermal Cruise invalid config, " + "skipping fan programming\n"); + return; + } + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping Thermal Cruise fan config programming\n"); + return; + } + + set_fan_pins_and_mode(fan, idx); + + hwm_reg_write(FAN_TC_TARGET_TEMP_REG(idx), + tc_fan->target_temp & FAN_TC_TARGET_TEMP_MASK); + + if (tc_fan->keep_min_fan_output) { + hwm_reg_set_bits(FAN_TC_TARGET_TEMP_REG(idx), FAN_TC_KEEP_MIN_OUTPUT); + hwm_reg_write(FAN_TC_STOP_VALUE_REG(idx), tc_fan->stop_value); + } + + hwm_reg_write(FAN_TC_TARGET_TEMP_TOLERANCE_REG(idx), + tc_fan->temp_tolerance & FAN_TC_TEMP_TOLERANCE_MASK); + + hwm_reg_write(FAN_INITIAL_VALUE_REG(idx), tc_fan->initial_value); + + hwm_reg_write(FAN_TC_STOP_TIME_REG(idx), tc_fan->stop_time); + hwm_reg_write(FAN_TC_STEP_DOWN_TIME_REG(idx), tc_fan->step_up_time); + hwm_reg_write(FAN_TC_STEP_UP_TIME_REG(idx), tc_fan->step_down_time); + + /* Set fan mode to automatic */ + hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0); + + hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); + + lock_fan_register_set_and_check(FAN_ERR_THERMAL_CRUISE); + + misc_fan_config(conf, idx); +} + +static bool speed_cruise_config_check(const struct nct6687d_fan_speed_cruise_config *sc_fan) +{ + bool failure = false; + + failure |= check_cond(sc_fan->target_rpm <= 0x3fff, + "Speed Cruise Target RPM should be <= 16838 RPM"); + failure |= check_cond(sc_fan->target_rpm >= sc_fan->rpm_tolerance, + "Speed Cruise Target RPM should be >= RPM Tolerance"); + failure |= check_cond(sc_fan->step_down_time > 0, + "Speed Cruise Step-Down Time should be > 0"); + failure |= check_cond(sc_fan->step_up_time > 0, + "Speed Cruise Step-Up Time should be > 0"); + + return failure; +} + +static void init_speed_cruise_fan(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_fan_speed_cruise_config *sc_fan = &fan->speed_cruise_fan; + + if (speed_cruise_config_check(sc_fan)) { + printk(BIOS_ERR, "NCT6687D Speed Cruise invalid config, " + "skipping fan programming\n"); + return; + } + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping Speed Cruise fan config programming\n"); + return; + } + + set_fan_pins_and_mode(fan, idx); + + /* Speed cruise should only enable RPM units */ + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); + + hwm_reg_write(FAN_SC_TARGET_RPM_HI_REG(idx), sc_fan->target_rpm >> 8); + hwm_reg_write(FAN_SC_TARGET_RPM_LO_REG(idx), sc_fan->target_rpm & 0xff); + + hwm_reg_write(FAN_SC_TARGET_RPM_TOLERANCE_HI_REG(idx), sc_fan->rpm_tolerance >> 8); + hwm_reg_write(FAN_SC_TARGET_RPM_TOLERANCE_LO_REG(idx), sc_fan->rpm_tolerance & 0xff); + + hwm_reg_write(FAN_SC_STEP_DOWN_TIME_REG(idx), sc_fan->step_up_time); + hwm_reg_write(FAN_SC_STEP_UP_TIME_REG(idx), sc_fan->step_down_time); + + /* Set fan mode to automatic */ + hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0x00); + + hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); + + lock_fan_register_set_and_check(FAN_ERR_SPEED_CRUISE); + + misc_fan_config(conf, idx); +}; + +static void init_one_fan(const struct superio_nuvoton_nct6687d_config *conf, unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + + switch(fan->mode) { + case FAN_THERMAL_CRUISE: + printk(BIOS_DEBUG, "Initializing Thermal Cruise for FAN%d\n", idx); + init_thermal_cruise_fan(conf, idx); + break; + case FAN_SPEED_CRUISE: + printk(BIOS_DEBUG, "Initializing Speed Cruise for FAN%d\n", idx); + init_speed_cruise_fan(conf, idx); + break; + case FAN_SMART_FAN_IV: + printk(BIOS_DEBUG, "Initializing Smart FAN IV for FAN%d\n", idx); + init_smart_fan(conf, idx); + break; + case FAN_PID_CONTROL: + printk(BIOS_WARNING, "NCT6687D: PID Control fan mode not yet supported\n"); + break; + case FAN_MODE_MANUAL: + printk(BIOS_DEBUG, "Initializing manual fan mode for FAN%d\n", idx); + init_manual_fan(conf, idx); + break; + default: + printk(BIOS_ERR, "NCT6687D: unknown fan mode detected!\n"); + } +} + +static void init_fans(const struct superio_nuvoton_nct6687d_config *conf) +{ + unsigned int i; + const struct nct6687d_fan_config *fans = conf->fans; + + for (i = 1; i <= MAX_NUM_FANS; i++) { + if (fans[i - 1].mode == FAN_IGNORE) + continue; + + init_one_fan(conf, i); + } +} + +static void report_ec_info(void) +{ + unsigned int i; + + printk(BIOS_DEBUG, "NCT6687D EC info:\n"); + printk(BIOS_DEBUG, "\tChip ID: %04x\n", + (uint16_t)hwm_reg_read(CHIP_ID0_REG) | + (uint16_t)(hwm_reg_read(CHIP_ID1_REG) << 8)); + printk(BIOS_DEBUG, "\tCustomer ID: %04x\n", + (uint16_t)hwm_reg_read(CUSTOMER_ID0_REG) | + (uint16_t)(hwm_reg_read(CUSTOMER_ID1_REG) << 8)); + printk(BIOS_DEBUG, "\tFW build date: %02d/%02d/20%02d\n", + hwm_reg_read(FW_BUILD_DAY_REG), + hwm_reg_read(FW_BUILD_MONTH_REG), + hwm_reg_read(FW_BUILD_YEAR_REG)); + printk(BIOS_DEBUG, "\tFW build serial number: %d\n", + hwm_reg_read(FW_BUILD_SERIALNUM_REG)); + printk(BIOS_DEBUG, "\tFW version: %d.%d\n", + hwm_reg_read(FW_VER0_REG), + hwm_reg_read(FW_VER1_REG)); + printk(BIOS_DEBUG, "\tProfile version: %d\n", + hwm_reg_read(PROFILE_VER_REG)); + printk(BIOS_DEBUG, "\tROM version: %d.%d.%d.%d\n", + hwm_reg_read(ROM_VER0_REG), hwm_reg_read(ROM_VER1_REG), + hwm_reg_read(ROM_VER2_REG), hwm_reg_read(ROM_VER3_REG)); + printk(BIOS_DEBUG, "\tISP build date: %02d/%02d/20%02d\n", + hwm_reg_read(ISP_BUILD_DAY_REG), + hwm_reg_read(ISP_BUILD_MONTH_REG), + hwm_reg_read(ISP_BUILD_YEAR_REG)); + printk(BIOS_DEBUG, "\tISP build serial number: %d\n", + hwm_reg_read(ISP_BUILD_SERIALNUM_REG)); + printk(BIOS_DEBUG, "\tISP version: %d.%d\n", + hwm_reg_read(ISP_VER0_REG), + hwm_reg_read(ISP_VER1_REG)); + printk(BIOS_DEBUG, "\tOEM version:"); + + for (i = 0; i < OEM_VER_LEN; i++) + printk(BIOS_DEBUG, "%02x", hwm_reg_read(OEM_VER_REG + i)); + + printk(BIOS_DEBUG, "\n"); +} + +void nct6687d_hwm_init(uint16_t hwm_base, const struct superio_nuvoton_nct6687d_config *conf) +{ + nct6687d_hwm_base = hwm_base; + + report_ec_info(); + + init_sensors(conf); + init_fans(conf); + + lock_sensor_config(); + print_fan_engine_status(); +} diff --git a/src/superio/nuvoton/nct6687d/nct6687d_hwm.h b/src/superio/nuvoton/nct6687d/nct6687d_hwm.h new file mode 100644 index 00000000000..0a7b83b7e39 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d_hwm.h @@ -0,0 +1,922 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT6687D_HWM_H +#define SUPERIO_NUVOTON_NCT6687D_HWM_H + +#include +#include + +#include "chip.h" +#include "nct6687d_ec.h" + +/* + * EC page number will be concatenated with the register offset to mark + * which page the register belongs to. + */ +#define EC_PAGE(page) ((page) << 8) +#define EC_PAGE_REG(page, reg) (EC_PAGE(page) + (reg)) + +/* EC page 1 */ +#define SENSOR_READ_HI_REG(x) EC_PAGE_REG(1, 0x00 + 2*(x)) +#define SENSOR_READ_LO_REG(x) EC_PAGE_REG(1, 0x01 + 2*(x)) +#define FAN_RPM_READ_HI_REG(x) EC_PAGE_REG(1, 0x40 + 2*((x) - 1)) +#define FAN_RPM_READ_LO_REG(x) EC_PAGE_REG(1, 0x41 + 2*((x) - 1)) + +#define FAN_DUTY_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0xf0 + ((fan)-8)) \ + : EC_PAGE_REG(1, 0x60 + 2*((fan) - 1))) + +#define SENSOR_MON_STS_REG EC_PAGE_REG(1, 0x70) +#define TEMP_OVERLOAD (1 << 1) +#define VOLT_OVERLOAD (1 << 1) +#define FAN_OVERLOAD (1 << 2) + +/* Errors and statuses */ +#define PROCHOT_MON_STS_REG EC_PAGE_REG(1, 0x71) +#define SENSOR_ERROR_STS_REG(x) EC_PAGE_REG(1, 0x74 + (x)) +#define TMPIN_IDLE_STS_REG(x) EC_PAGE_REG(1, 0x78 + (x)) +#define FANIN_ERROR_STS_REG(x) EC_PAGE_REG(1, 0x7C + (x)) +#define FANOUT_ERROR_STS_REG EC_PAGE_REG(1, 0x7e) +#define FAN_INIT_STS_REG EC_PAGE_REG(1, 0x7f) + +#define HWM_CONFIG_REG EC_PAGE_REG(1, 0x80) +#define SMI_SCI_SEL (1 << 2) +#define LOCK_SENSOR_CFG (1 << 5) +#define HWM_EN (1 << 7) + +#define SENSOR_MON_VCC_DELAY_REG EC_PAGE_REG(1, 0x81) +#define TEMPIN_IDLE_COUNTER_REG EC_PAGE_REG(1, 0x82) +#define VIRTUAL_INPUT_CFG_REG EC_PAGE_REG(1, 0x83) +#define TMPIN_POLLING_RATE_REG EC_PAGE_REG(1, 0x85) +#define VIN_POLLING_RATE_REG EC_PAGE_REG(1, 0x86) +#define FAN_POLLING_RATE_REG EC_PAGE_REG(1, 0x87) + +#define ADC_CLOCKK_DIV_REG EC_PAGE_REG(1, 0x88) +#define ADC_AVG_NUM_REG EC_PAGE_REG(1, 0x89) +#define ADC_SLOPE_HI_REG EC_PAGE_REG(1, 0x8a) +#define ADC_SLOPE_LO_REG EC_PAGE_REG(1, 0x8b) + +#define PROCHOT_CFG_REG EC_PAGE_REG(1, 0x8e) +#define REFRESH_RATE_MASK (3 << 0) +#define REFRESH_RATE_100MS (0 << 0) +#define REFRESH_RATE_200MS (1 << 0) +#define REFRESH_RATE_500MS (2 << 0) +#define REFRESH_RATE_1S (3 << 0) +#define AVG_TIME_MASK (3 << 2) +#define AVG_TIME_1 (0 << 2) +#define AVG_TIME_2 (1 << 2) +#define AVG_TIME_4 (2 << 2) +#define AVG_TIME_8 (3 << 2) +#define MONITOR_MODE_MASK (3 << 4) +#define MONITOR_MODE_CAPTURE (0 << 4) +#define MONITOR_MODE_8BIT (1 << 4) +#define MONITOR_MODE_12BIT (2 << 4) +#define MONITOR_MODE_16BIT (3 << 4) +#define CLK_SRC_40K (0 << 6) +#define CLK_SRC_MCLK (1 << 6) +#define PROCHOT_EN (1 << 7) + +#define PROCHOT_OUT_REG EC_PAGE_REG(1, 0x8f) + +#define VIRTUAL_SENSOR_INPUT_REG(x) EC_PAGE_REG(1, 0x90 + (x)) + +#define SENSOR_CFG_REG(x) EC_PAGE_REG(1, 0xa0 + (x)) +#define FILTER_EN (1 << 7) +#define SENSOR_SRC_SEL_MASK 0x7f + +#define FANIN_CFG_REG(fan) EC_PAGE_REG(1, 0xc0 + ((fan) - 1)) +#define FANIN_PIN_SEL_MASK 0x1f +#define FANIN_PULSE_REV_MASK (3 << 5) +#define FANIN_PULSE_REV_SHIFT 5 +#define FANIN_MONITOR_EN (1 << 7) + +#define FANOUT_CFG_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0xf4 + ((fan) - 9)) \ + : EC_PAGE_REG(1, 0xd0 + ((fan) - 1))) +#define FANOUT_PIN_SEL_MASK 0x1f +#define FANOUT_TYPE_PP (0 << 5) +#define FANOUT_TYPE_OD (1 << 5) +#define FANOUT_INV_EN (1 << 6) +#define FANOUT_EN (1 << 7) + +#define FAN_INIT_RPM_HI_REG(fan) EC_PAGE_REG(1, 0xe0 + 2*((fan) - 1)) +#define FAN_INIT_RPM_LO_REG(fan) EC_PAGE_REG(1, 0xe1 + 2*((fan) - 1)) +#define FAN_INIT_DUTY_VAL_REG(fan) EC_PAGE_REG(1, 0xf0 + ((fan) - 1)) +#define FAN_INIT_MODE_REG EC_PAGE_REG(1, 0xf8) +#define FAN_INIT_MODE_RPM(fan) (1 << ((fan) - 1)) +#define FAN_INIT_MODE_PWM(fan) (0 << ((fan) - 1)) + +#define FAN_RPM_INIT_UNIT_REG EC_PAGE_REG(1, 0xf9) +#define FAN_RPM_INIT_TOLERANCE_REG EC_PAGE_REG(1, 0xfa) +#define FAN_RPM_INIT_STABLE_COUNTER_REG EC_PAGE_REG(1, 0xfb) +#define FAN_RPM_INIT_TIME_COUNTER_REG EC_PAGE_REG(1, 0xfc) + +/* EC Page 2 - GPIO */ + +#define TIN_OFFSET_REG(x) EC_PAGE_REG(2, 0x00 + (x)) + +#define GPI_FALLING_TRIG_EN_HI_REG EC_PAGE_REG(2, 0xb0) +#define GPI_FALLING_TRIG_EN_LO_REG EC_PAGE_REG(2, 0xb1) +#define GPI_RISING_TRIG_EN_HI_REG EC_PAGE_REG(2, 0xb2) +#define GPI_RISING_TRIG_EN_LO_REG EC_PAGE_REG(2, 0xb3) +#define GPI_DATA_HI_REG EC_PAGE_REG(2, 0xb4) +#define GPI_DATA_LO_REG EC_PAGE_REG(2, 0xb5) +#define GPI_SEL_REG(x) EC_PAGE_REG(2, 0xc0 + (x)) +#define GPO_TYPE_HI_REG EC_PAGE_REG(2, 0xd0) +#define GPO_TYPE_LO_REG EC_PAGE_REG(2, 0xd1) +#define GPO_DATA_HI_REG EC_PAGE_REG(2, 0xd4) +#define GPO_DATA_LO_REG EC_PAGE_REG(2, 0xd5) +#define GPO_SEL_REG(x) EC_PAGE_REG(2, 0xe0 + (x)) + +/* EC page 3 */ + +#define SENSOR_INT_CFG_REG(x) EC_PAGE_REG(3, 0x10 + (x)) +#define TMPIN_INT_SEL_MASK (7 << 0) +#define TMPIN_INT_DISABLE (0 << 0) +#define TMPIN_INT_SHUTDOWN_MODE (1 << 0) +#define TMPIN_INT_SYST_FAN_COMP_MODE (2 << 0) +#define TMPIN_INT_CPUT_FAN_COMP_MODE (3 << 0) +#define TMPIN_INT_TWO_TIMES_MODE (4 << 0) +#define TMPIN_INT_ONE_TIME_MODE (5 << 0) +#define TMPIN_INT_OVT_COMP_MODE (6 << 0) +#define TMPIN_INT_OVT_MODE (7 << 0) +#define VIN_INT_EN (1 << 7) + +#define TMPIN_HYSTERSIS_REG(x) EC_PAGE_REG(3, 0x30 + (x)) +#define TMPIN_OVERTEMP_REG(x) EC_PAGE_REG(3, 0x50 + (x)) +#define TIN_SHUTDOWN_VIN_LIMIT_HI_REG(x) EC_PAGE_REG(3, 0x70 + 2*(x)) +#define TIN_SHUTDOWN_VIN_LIMIT_LO_REG(x) EC_PAGE_REG(3, 0x71 + 2*(x)) + +#define FAN_RPM_INT_EN1_REG EC_PAGE_REG(3, 0xb0) +#define FAN_RPM_INT_EN2_REG EC_PAGE_REG(3, 0xb1) + +#define FAN_RPM_LIMIT_HI_REG(fan) EC_PAGE_REG(3, 0xb8 + 2*(fan)) +#define FAN_RPM_LIMIT_LO_REG(fan) EC_PAGE_REG(3, 0xb9 + 2*(fan)) + +/* EC Page 4 - SMBus */ + +#define PCH_ERR_STS_REG EC_PAGE_REG(4, 0x00) +#define TSI_ERR_STS_REG EC_PAGE_REG(4, 0x01) +#define SMBUS_MASTER_ERR_STS_REG EC_PAGE_REG(4, 0x04) +#define SMBUS_THERM_SENSOR_ERR_STS_REG(x) EC_PAGE_REG(4, 0x06 + (x)) +#define SMBUS_DIMM_SENSOR_ERR_STS_REG(x) EC_PAGE_REG(4, 0x0c + (x)) + +#define PCH_THERMAL_DATA_CFG_REG EC_PAGE_REG(4, 0x10) +#define PCH_BAUD_SEL_MASK (7 << 0) +#define PCH_BAUD_12_5K (0 << 0) +#define PCH_BAUD_25K (1 << 0) +#define PCH_BAUD_50K (2 << 0) +#define PCH_BAUD_100K (3 << 0) +#define PCH_BAUD_200K (4 << 0) +#define PCH_BAUD_400K (5 << 0) +#define PCH_BAUD_800K (6 << 0) +#define PCH_BAUD_1200K (7 << 0) +#define PCH_PORT_SEL_MASK (3 << 4) +#define PCH_THERMAL_PORT(x) ((x) << 4) +#define PCH_ONE_BYTE_REPORT (1 << 7) + +#define PCH_DEVICE_ADDR_REG EC_PAGE_REG(4, 0x11) +#define PCH_THERMAL_CMD_REG EC_PAGE_REG(4, 0x12) + +#define TSI_THERMAL_DATA_CFG_REG EC_PAGE_REG(4, 0x14) +#define TSI_BAUD_SEL_MASK (7 << 0) +#define TSI_BAUD_12_5K (0 << 0) +#define TSI_BAUD_25K (1 << 0) +#define TSI_BAUD_50K (2 << 0) +#define TSI_BAUD_100K (3 << 0) +#define TSI_BAUD_200K (4 << 0) +#define TSI_BAUD_400K (5 << 0) +#define TSI_BAUD_800K (6 << 0) +#define TSI_BAUD_1200K (7 << 0) +#define TSI_PORT_SEL_MASK (3 << 4) +#define TSI_THERMAL_PORT(x) ((x) << 4) + +#define SMBUS_SENSOR_CFG_REG(x) EC_PAGE_REG(4, 0x1a + 5*(x)) +#define SMB_BAUD_SEL_MASK (7 << 0) +#define SMB_BAUD_12_5K (0 << 0) +#define SMB_BAUD_25K (1 << 0) +#define SMB_BAUD_50K (2 << 0) +#define SMB_BAUD_100K (3 << 0) +#define SMB_BAUD_200K (4 << 0) +#define SMB_BAUD_400K (5 << 0) +#define SMB_BAUD_800K (6 << 0) +#define SMB_BAUD_1200K (7 << 0) +#define SMB_PORT_SEL_MASK (3 << 4) +#define SMB_SENSOR_PORT(x) ((x) << 4) +#define SMB_SENSOR_DATA_LEN_1B (0 << 6) +#define SMB_SENSOR_DATA_LEN_2B (1 << 6) +#define SMB_SENSOR_DIRECT_ACCESS (1 << 7) + +#define SMBUS_SENSOR_ADDR_REG(x) EC_PAGE_REG(4, 0x1b + 5*(x)) +#define SMBUS_SENSOR_CMD_REG(x) EC_PAGE_REG(4, 0x1c + 5*(x)) +#define SMBUS_SENSOR_DATA_REG(x) EC_PAGE_REG(4, 0x1d + 5*(x)) +#define SMBUS_SENSOR_READ_CMD_REG(x) EC_PAGE_REG(4, 0x1e + 5*(x)) + +#define SMBUS_DIMM_SENSOR_CFG0(x) EC_PAGE_REG(4, 0x3a + 4*(x)) +#define SMB_DIMM_ADDR_MASK 0x07 +#define SMB_DIMM_BAUD_SEL_MASK (7 << 4) +#define SMB_DIMM_BAUD_12_5K (0 << 0) +#define SMB_DIMM_BAUD_25K (1 << 0) +#define SMB_DIMM_BAUD_50K (2 << 0) +#define SMB_DIMM_BAUD_100K (3 << 0) +#define SMB_DIMM_BAUD_200K (4 << 0) +#define SMB_DIMM_BAUD_400K (5 << 0) +#define SMB_DIMM_BAUD_800K (6 << 0) +#define SMB_DIMM_BAUD_1200K (7 << 0) +#define SMBUS_DIMM_SENSOR_EN (1 << 7) + +#define SMBUS_DIMM_SENSOR_CFG1_REG(x) EC_PAGE_REG(4, 0x3b + 4*(x)) +/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ +#define SMD_DIMM_ADDR_MASK 0x07 +#define SMB_PORT_SEL_MASK (3 << 4) +#define SMB_SENSOR_PORT(x) ((x) << 4) + +#define SMBUS_DIMM_SENSOR_CFG2_REG(x) EC_PAGE_REG(4, 0x3c + 4*(x)) +/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ + +#define SMBUS_DIMM_SENSOR_CFG3_REG(x) EC_PAGE_REG(4, 0x3d + 4*(x)) +/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ + +#define SMBUS_MASTER_CFG1_REG EC_PAGE_REG(4, 0x60) +#define SMB_MASTER_POLLRATE_MASK 0x07 +#define SMB_MASTER_POLLRATE_ONCE (0 << 0) +#define SMB_MASTER_POLLRATE_100MS (0 << 0) +#define SMB_MASTER_POLLRATE_200MS (0 << 0) +#define SMB_MASTER_POLLRATE_400MS (0 << 0) +#define SMB_MASTER_POLLRATE_800MS (0 << 0) +#define SMB_MASTER_POLLRATE_1S (0 << 0) +#define SMB_MASTER_POLLRATE_2S (0 << 0) +#define SMB_MASTER_POLLRATE_4S (0 << 0) +#define SMB_MASTER_CLEAR_BUF (1 << 3) +#define SMB_MASTER_HOLD_RDY (1 << 5) +#define SMB_MASTER_START (1 << 6) +#define SMB_MASTER_EN (1 << 7) + +#define SMBUS_MASTER_CFG2_REG EC_PAGE_REG(4, 0x61) +#define SMB_MASTER_PORT_SEL_MASK 0x03 +#define SMB_MASTER_PORT(x) ((x) << 0) +#define SMB_MASTER_PEC_EN (1 << 3) + +#define SMBUS_MASTER_BAUD_RATE_SEL_REG EC_PAGE_REG(4, 0x62) +#define SMB_MASTER_BAUD_SEL_MASK (7 << 4) +#define SMB_MASTER_BAUD_12_5K (0 << 0) +#define SMB_MASTER_BAUD_25K (1 << 0) +#define SMB_MASTER_BAUD_50K (2 << 0) +#define SMB_MASTER_BAUD_100K (3 << 0) +#define SMB_MASTER_BAUD_200K (4 << 0) +#define SMB_MASTER_BAUD_400K (5 << 0) +#define SMB_MASTER_BAUD_800K (6 << 0) +#define SMB_MASTER_BAUD_1200K (7 << 0) + +#define SMBUS_MASTER_PROTOCOL_SEL_REG EC_PAGE_REG(4, 0x63) +#define SMBUS_MASTER_QUICK_WRITE 0x00 +#define SMBUS_MASTER_SEND_BYTE 0x01 +#define SMBUS_MASTER_WRITE_BYTE 0x02 +#define SMBUS_MASTER_WRITE_WORD 0x03 +#define SMBUS_MASTER_BLOCK_WRITE 0x04 +#define SMBUS_MASTER_PROCESS_CALL 0x05 +#define SMBUS_MASTER_BLOCK_WRITE_READ 0x06 +#define SMBUS_MASTER_RECEIVE_BYTE 0x81 +#define SMBUS_MASTER_READ_BYTE 0x82 +#define SMBUS_MASTER_READ_WORD 0x83 +#define SMBUS_MASTER_BLOCK_READ 0x84 + +#define SMBUS_MASTER_BLOCK_WR_LEN_REG EC_PAGE_REG(4, 0x64) +#define SMBUS_MASTER_DEV_ADDR_REG EC_PAGE_REG(4, 0x65) +#define SMBUS_MASTER_CMD_REG EC_PAGE_REG(4, 0x66) + +#define SMBUS_MASTER_WRITE_BUFFER(x) EC_PAGE_REG(4, 0x70 + (x)) +#define SMBUS_MASTER_WRITE_BUFFER_LEN 64 +#define SMBUS_MASTER_READ_BUFFER(x) EC_PAGE_REG(4, 0xb0 + (x)) +#define SMBUS_MASTER_READ_BUFFER_LEN 64 + +/* EC page 5 - PECI */ + +#define PECI_PING_INFO_REG EC_PAGE_REG(5, 0x00) +#define PECI_AGENT_ALIVE(agent) (1 << (agent)) +#define PECI_OVER_SMBUS (1 << 7) + +#define PECI_INFO_STS_REG EC_PAGE_REG(5, 0x01) +#define PECI_AGENT_INFO_RDY(agent) (1 << (agent)) + +#define PECI_DEVICE_INFO_REG EC_PAGE_REG(5, 0x02) +#define PECI_AGENT_TWO_DOMAIN_SUPPORT (1 << 2) + +#define PECI_REVISION_INFO_REG EC_PAGE_REG(5, 0x03) +#define PECI_REV_MINOR_MASK 0x0f +#define PECI_REV_MINOR_SHIFT 0 +#define PECI_REV_MAJOR_MASK 0xf0 +#define PECI_REV_MAJOR_SHIFT 4 + +#define PECI_DOM0_MARGIN_HI_REG(agent) EC_PAGE_REG(5, 0x20 + 2*(agent)) +#define PECI_DOM0_MARGIN_LO_REG(agent) EC_PAGE_REG(5, 0x21 + 2*(agent)) +#define PECI_DOM1_MARGIN_HI_REG(agent) EC_PAGE_REG(5, 0x28 + 2*(agent)) +#define PECI_DOM1_MARGIN_LO_REG(agent) EC_PAGE_REG(5, 0x29 + 2*(agent)) + +#define PECI_DOM0_TEMP_HI_REG(agent) EC_PAGE_REG(5, 0x30 + 2*(agent)) +#define PECI_DOM0_TEMP_LO_REG(agent) EC_PAGE_REG(5, 0x31 + 2*(agent)) +#define PECI_DOM1_TEMP_HI_REG(agent) EC_PAGE_REG(5, 0x38 + 2*(agent)) +#define PECI_DOM1_TEMP_LO_REG(agent) EC_PAGE_REG(5, 0x39 + 2*(agent)) + +#define PECI_TCONTROL_REG(dom, agent) EC_PAGE_REG(5, 0x40 + 4*(dom) + (agent)) +#define PECI_TJMAX_REG(dom, agent) EC_PAGE_REG(5, 0x48 + 4*(dom) + (agent)) + +#define PECI_PCS_ERR_STS_REG EC_PAGE_REG(5, 0x52) +#define PECI_MASTER_ERR_STS_REG EC_PAGE_REG(5, 0x53) + +#define PECI_CFG_REG EC_PAGE_REG(5, 0x60) +#define PECI_SPEED_SEL_MASK (3 << 0) +#define PECI_SPEED_2MHZ (0 << 0) +#define PECI_SPEED_1_2MHZ (1 << 0) +#define PECI_SPEED_800KHZ (2 << 0) +#define PECI_SPEED_400KHZ (3 << 0) +#define PECI_USER_TJMAX_FROM_CPU (0 << 5) +#define PECI_USER_TJMAX_FROM_EC (1 << 5) +#define PECI_AGENT_INIT (1 << 6) +#define PECI_EN (1 << 7) + +#define PECI_AGENT_EN_REG EC_PAGE_REG(5, 0x61) +#define PECI_AGENT_EN_MASK 0xf +#define PECI_AGENT_EN(agent) (1 << (agent)) + +#define PECI_HOSTID_REG EC_PAGE_REG(5, 0x62) +#define PECI_ERR_RETRY_CFG_REG EC_PAGE_REG(5, 0x63) +#define PECI_MARGIN_CFG_REG EC_PAGE_REG(5, 0x64) +#define PECI_MARGIN_POLLRATE_MASK 0x07 +#define PECI_MARGIN_POLLRATE_ONCE (0 << 0) +#define PECI_MARGIN_POLLRATE_100MS (1 << 0) +#define PECI_MARGIN_POLLRATE_200MS (2 << 0) +#define PECI_MARGIN_POLLRATE_400MS (3 << 0) +#define PECI_MARGIN_POLLRATE_800MS (4 << 0) +#define PECI_MARGIN_POLLRATE_1S (5 << 0) +#define PECI_MARGIN_POLLRATE_2S (6 << 0) +#define PECI_MARGIN_POLLRATE_4S (7 << 0) +#define PECI_GET_MARGIN_EN (1 << 7) + +#define PECI_USER_TJMAX_REG(dom, agent) EC_PAGE_REG(5, 0x68 + 4*(dom) + (agent)) +#define PECI_PCS_CFG_REG 0x70 +#define PECI_PCS_POLLRATE_MASK 0x07 +#define PECI_PCS_POLLRATE_ONCE (0 << 0) +#define PECI_PCS_POLLRATE_100MS (1 << 0) +#define PECI_PCS_POLLRATE_200MS (2 << 0) +#define PECI_PCS_POLLRATE_400MS (3 << 0) +#define PECI_PCS_POLLRATE_800MS (4 << 0) +#define PECI_PCS_POLLRATE_1S (5 << 0) +#define PECI_PCS_POLLRATE_2S (6 << 0) +#define PECI_PCS_POLLRATE_4S (7 << 0) +#define PECI_PCS_STOP_ERR (1 << 4) +#define PECI_PCS_HOLD_RDY (1 << 5) +#define PECI_PCS_START (1 << 6) +#define PECI_PCS_EN (1 << 7) + +#define PECI_PCS_CFG2_REG EC_PAGE_REG(5, 0x71) +#define PECI_PCS_AGENT_SEL_MASK 0x03 +#define PECI_PCS_SEL_DOM0 (0 << 4) +#define PECI_PCS_SEL_DOM1 (1 << 4) +#define PECI_PCS_WRITE_PKG_CFG (1 << 7) + +#define PECI_PCS_IDX_REG EC_PAGE_REG(5, 0x72) +#define PECI_PCS_PARAM_LO_REG EC_PAGE_REG(5, 0x73) +#define PECI_PCS_PARAM_HI_REG EC_PAGE_REG(5, 0x74) + +#define PECI_PCS_COMPLETION_CODE_REG EC_PAGE_REG(5, 0x75) +#define PECI_PCS_DATA_VALID 0x40 +#define PECI_PCS_RESP_TIMEOUT_RETRY 0x80 +#define PECI_PCS_RESP_TIMEOUT 0x81 +#define PECI_PCS_INVALID_REQUEST 0x90 +#define PECI_PCS_PECI_CONTROL_HW 0x91 + +#define PECI_PCS_BUF_REG(x) EC_PAGE_REG(5, 0x76 + (x)) +#define PECI_PCS_BUF_LEN 4 + +#define PECI_MASTER_CFG_REG EC_PAGE_REG(5, 0x7a) +#define PECI_MASTER_POLLRATE_MASK 0x07 +#define PECI_MASTER_POLLRATE_ONCE (0 << 0) +#define PECI_MASTER_POLLRATE_100MS (1 << 0) +#define PECI_MASTER_POLLRATE_200MS (2 << 0) +#define PECI_MASTER_POLLRATE_400MS (3 << 0) +#define PECI_MASTER_POLLRATE_800MS (4 << 0) +#define PECI_MASTER_POLLRATE_1S (5 << 0) +#define PECI_MASTER_POLLRATE_2S (6 << 0) +#define PECI_MASTER_POLLRATE_4S (7 << 0) +#define PECI_MASTER_STOP_ERR (1 << 4) +#define PECI_MASTER_HOLD_RDY (1 << 5) +#define PECI_MASTER_START (1 << 6) +#define PECI_MASTER_EN (1 << 7) + +#define PECI_MASTER_CFG2_REG EC_PAGE_REG(5, 0x7b) +#define PECI_MASTER_CPL_CODE_SUPP (1 << 6) +#define PECI_MASTER_AWFCS_EN (1 << 7) + +#define PECI_MASTER_CLIENT_ADDR_REG EC_PAGE_REG(5, 0x7c) +#define PECI_MASTER_CMD_CODE_REG EC_PAGE_REG(5, 0x7d) +#define PECI_MASTER_WRITE_LEN_REG EC_PAGE_REG(5, 0x7e) +#define PECI_MASTER_READ_LEN_REG EC_PAGE_REG(5, 0x7f) + +#define PECI_MASTER_WRITE_BUF(x) EC_PAGE_REG(5, 0x80 + (x)) +#define PECI_MASTER_WRITE_BUF_LEN 12 +#define PECI_MASTER_READ_BUF(x) EC_PAGE_REG(5, 0x90 + (x)) +#define PECI_MASTER_READ_BUF_LEN 12 + +#define PECI_DRAM_TEMP_WR_STS_REG(x) EC_PAGE_REG(5, 0xa0 + (x)) +#define PECI_DIMM_AMB_TEMP_WR_STS_REG(x) EC_PAGE_REG(5, 0xa4 + (x)) +#define PECI_DIMM_TEMP_RD_STS_REG(x) EC_PAGE_REG(5, 0xa8 + (x)) +#define PECI_ACC_ENERGRY_RD_STS_REG(x) EC_PAGE_REG(5, 0xac + (x)) + +#define PECI_DRAM_TEMP_WR_POLL_RATE_REG EC_PAGE_REG(5, 0xb0) +#define PECI_DRAM_POLLRATE_MASK 0x07 +#define PECI_DRAM_POLLRATE_ONCE (0 << 0) +#define PECI_DRAM_POLLRATE_100MS (1 << 0) +#define PECI_DRAM_POLLRATE_200MS (2 << 0) +#define PECI_DRAM_POLLRATE_400MS (3 << 0) +#define PECI_DRAM_POLLRATE_800MS (4 << 0) +#define PECI_DRAM_POLLRATE_1S (5 << 0) +#define PECI_DRAM_POLLRATE_2S (6 << 0) +#define PECI_DRAM_POLLRATE_4S (7 << 0) + +#define PECI_DIMM_AMB_TEMP_WR_POLL_RATE_REG EC_PAGE_REG(5, 0xb1) +#define PECI_DIMM_AMB_POLLRATE_MASK 0x07 +#define PECI_DIMM_AMB_POLLRATE_ONCE (0 << 0) +#define PECI_DIMM_AMB_POLLRATE_100MS (1 << 0) +#define PECI_DIMM_AMB_POLLRATE_200MS (2 << 0) +#define PECI_DIMM_AMB_POLLRATE_400MS (3 << 0) +#define PECI_DIMM_AMB_POLLRATE_800MS (4 << 0) +#define PECI_DIMM_AMB_POLLRATE_1S (5 << 0) +#define PECI_DIMM_AMB_POLLRATE_2S (6 << 0) +#define PECI_DIMM_AMB_POLLRATE_4S (7 << 0) + +#define PECI_ACC_ENERGRY_RD_POLL_RATE_REG EC_PAGE_REG(5, 0xb2) +#define PECI_ACC_ENERGRY_RD_POLLRATE_MASK 0x07 +#define PECI_ACC_ENERGRY_RD_POLLRATE_ONCE (0 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_100MS (1 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_200MS (2 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_400MS (3 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_800MS (4 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_1S (5 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_2S (6 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_4S (7 << 0) + +#define PECI_DRAM_TEMP_WR_CFG1_REG(x) EC_PAGE_REG(5, 0xb8 + 2*(x)) +#define PECI_DRAM_TEMP_WR_CH_IDX_MASK (7 << 0) +#define PECI_DRAM_TEMP_WR_CH_IDX_SHIFT 0 +#define PECI_DRAM_TEMP_WR_DIMM_IDX_MASK (7 << 3) +#define PECI_DRAM_TEMP_WR_DIMM_IDX_SHIFT 3 +#define PECI_DRAM_TEMP_WR_POLLING (1 << 6) +#define PECI_DRAM_TEMP_WR_START (1 << 7) + +#define PECI_DRAM_TEMP_WR_CFG2_REG(x) EC_PAGE_REG(5, 0xb9 + 2*(x)) +#define PECI_DRAM_TEMP_WR_AGENT_IDX_MASK (3 << 1) +#define PECI_DRAM_TEMP_WR_AGENT_IDX_SHIFT 1 +#define PECI_DRAM_TEMP_WR_DOM0 (0 << 6) +#define PECI_DRAM_TEMP_WR_DOM1 (1 << 6) +#define PECI_DRAM_TEMP_WR_CH_SEL (1 << 7) + +#define PECI_DIMM_AMB_TEMP_WR_CFG1_REG(x) EC_PAGE_REG(5, 0xc0 + 2*(x)) +#define PECI_DIMM_AMB_TEMP_WR_CH_IDX_MASK (7 << 0) +#define PECI_DIMM_AMB_TEMP_WR_CH_IDX_SHIFT 0 +#define PECI_DIMM_AMB_TEMP_WR_POLLING (1 << 6) +#define PECI_DIMM_AMB_TEMP_WR_START (1 << 7) + +#define PECI_DIMM_AMB_TEMP_WR_CFG2_REG(x) EC_PAGE_REG(5, 0xc1 + 2*(x)) +#define PECI_DIMM_AMB_TEMP_WR_AGENT_IDX_MASK (3 << 1) +#define PECI_DIMM_AMB_TEMP_WR_AGENT_IDX_SHIFT 1 +#define PECI_DIMM_AMB_TEMP_WR_DOM0 (0 << 6) +#define PECI_DIMM_AMB_TEMP_WR_DOM1 (1 << 6) +#define PECI_DIMM_AMB_TEMP_WR_CH_SEL (1 << 7) + +#define PECI_DIMM_TEMP_RD_CFG1_REG(x) EC_PAGE_REG(5, 0xc8 + (x)) +#define PECI_DIMM_TEMP_RD_AGENT_IDX_MASK (3 << 0) +#define PECI_DIMM_TEMP_RD_AGENT_IDX_SHIFT 0 +#define PECI_DIMM_TEMP_RD_DOM0 (0 << 2) +#define PECI_DIMM_TEMP_RD_DOM1 (1 << 2) +#define PECI_DIMM_TEMP_RD_DIMM_SEL_MASK (3 << 4) +#define PECI_DIMM_TEMP_RD_DIMM0 (0 << 4) +#define PECI_DIMM_TEMP_RD_DIMM1 (1 << 4) +#define PECI_DIMM_TEMP_RD_DIMM0_MAX (2 << 4) +#define PECI_DIMM_TEMP_RD_DIMM1_MAX (3 << 4) +#define PECI_DIMM_TEMP_RD_DIMM_CH0 (0 << 6) +#define PECI_DIMM_TEMP_RD_DIMM_CH1 (1 << 6) + +#define PECI_ACC_ENERGRY_RD_CFG_REG(x) EC_PAGE_REG(5, 0xcc + (x)) +#define PECI_ACC_ENERGRY_RD_AGENT_IDX_MASK (3 << 0) +#define PECI_ACC_ENERGRY_RD_AGENT_IDX_SHIFT 0 +#define PECI_ACC_ENERGRY_RD_DOM0 (0 << 2) +#define PECI_ACC_ENERGRY_RD_DOM1 (1 << 2) +#define PECI_ACC_ENERGRY_RD_REPORT_CURR (0 << 3) +#define PECI_ACC_ENERGRY_RD_REPORT_INCR (1 << 3) +#define PECI_DIMM_TEMP_RD_PWR_PLANE_SEL_MASK (3 << 4) +#define PECI_DIMM_TEMP_RD_PWR_PLANE0 (0 << 4) +#define PECI_DIMM_TEMP_RD_PWR_PLANE1 (1 << 4) +#define PECI_DIMM_TEMP_RD_PKG_PWR_PLANE0 (2 << 4) +#define PECI_DIMM_TEMP_RD_PKG_PWR_PLANE1 (3 << 4) +#define PECI_ACC_ENERGRY_RD_POLLING (1 << 6) +#define PECI_ACC_ENERGRY_RD_START (1 << 7) + +#define PECI_ACC_ENERGRY_RD_VAL_B0_REG(x) EC_PAGE_REG(5, 0xd0 + 4*(x)) +#define PECI_ACC_ENERGRY_RD_VAL_B1_REG(x) EC_PAGE_REG(5, 0xd1 + 4*(x)) +#define PECI_ACC_ENERGRY_RD_VAL_B2_REG(x) EC_PAGE_REG(5, 0xd2 + 4*(x)) +#define PECI_ACC_ENERGRY_RD_VAL_B3_REG(x) EC_PAGE_REG(5, 0xd3 + 4*(x)) + +/* EC Page 6 - EC FW Information and Configuration */ + +#define CHIP_ID0_REG EC_PAGE_REG(6, 0x00) +#define CHIP_ID1_REG EC_PAGE_REG(6, 0x01) +#define CUSTOMER_ID0_REG EC_PAGE_REG(6, 0x02) +#define CUSTOMER_ID1_REG EC_PAGE_REG(6, 0x03) +#define FW_BUILD_YEAR_REG EC_PAGE_REG(6, 0x04) +#define FW_BUILD_MONTH_REG EC_PAGE_REG(6, 0x05) +#define FW_BUILD_DAY_REG EC_PAGE_REG(6, 0x06) +#define FW_BUILD_SERIALNUM_REG EC_PAGE_REG(6, 0x07) +#define FW_VER0_REG EC_PAGE_REG(6, 0x08) +#define FW_VER1_REG EC_PAGE_REG(6, 0x09) +#define PROFILE_VER_REG EC_PAGE_REG(6, 0x0a) +#define ROM_VER0_REG EC_PAGE_REG(6, 0x0c) +#define ROM_VER1_REG EC_PAGE_REG(6, 0x0d) +#define ROM_VER2_REG EC_PAGE_REG(6, 0x0e) +#define ROM_VER3_REG EC_PAGE_REG(6, 0x0f) +#define ISP_BUILD_YEAR_REG EC_PAGE_REG(6, 0x12) +#define ISP_BUILD_MONTH_REG EC_PAGE_REG(6, 0x13) +#define ISP_BUILD_DAY_REG EC_PAGE_REG(6, 0x14) +#define ISP_BUILD_SERIALNUM_REG EC_PAGE_REG(6, 0x15) +#define ISP_VER0_REG EC_PAGE_REG(6, 0x16) +#define ISP_VER1_REG EC_PAGE_REG(6, 0x17) + +#define OEM_VER_REG EC_PAGE_REG(6, 0x18) +#define OEM_VER_LEN 8 + +#define EC_ALIVE_COUNTER_REG EC_PAGE_REG(6, 0x20) + +#define EC_HEARTBEAT_CFG_REG EC_PAGE_REG(6, 0x2e) +#define EC_HEARBEAT_TOGGLE_RATE_MASK 0x0f +#define EC_HEARBEAT_TYPE_OD (0 << 6) +#define EC_HEARBEAT_TYPE_PP (1 << 6) +#define EC_HEARBEAT_EN (1 << 7) + +#define EC_HEARTBEAT_GPSEL_REG EC_PAGE_REG(6, 0x2f) +#define EC_HEARBEAT_GPIO_PIN_MASK 0x0f +#define EC_HEARBEAT_GPIO_PIN_SHIFT 0 +#define EC_HEARBEAT_GPIO_GROUP_MASK 0xf0 +#define EC_HEARBEAT_GPIO_GROUP_SHIFT 4 + +#define EC_MCU_SPEED_REG EC_PAGE_REG(6, 0x38) +#define EC_MCU_SPEED_MCLK_MASK 0x0f +#define EC_MCU_SPEED_MCLK_10KHZ (0 << 0) +#define EC_MCU_SPEED_MCLK_160KHZ (1 << 0) +#define EC_MCU_SPEED_MCLK_1MHZ (2 << 0) +#define EC_MCU_SPEED_MCLK_4MHZ (3 << 0) +#define EC_MCU_SPEED_MCLK_8MHZ (4 << 0) +#define EC_MCU_SPEED_MCLK_16MHZ (5 << 0) +#define EC_MCU_SPEED_MCLK_24MHZ (6 << 0) +#define EC_MCU_SPEED_MCLK_48MHZ (7 << 0) +#define EC_MCU_CACHE_EN (1 << 6) + +#define EC_FLASH_SPEED_REG EC_PAGE_REG(6, 0x39) +#define EC_FLASH_CLK_DIV_MASK (3 << 4) +#define EC_FLASH_CLK_DIV_1 (0 << 4) +#define EC_FLASH_CLK_DIV_2 (1 << 4) +#define EC_FLASH_CLK_DIV_4 (2 << 4) +#define EC_FLASH_CLK_DIV_16 (3 << 4) +#define EC_FLASH_FETCH_MODE_MASK (3 << 6) +#define EC_FLASH_FETCH_MODE_READ (0 << 6) +#define EC_FLASH_FETCH_MODE_FAST_READ (1 << 6) +#define EC_FLASH_FETCH_MODE_DUAL_OUT (2 << 6) +#define EC_FLASH_FETCH_MODE_DUAL_IN_OUT (3 << 6) + +#define EC_FLASH_MANUFACTURE_REG EC_PAGE_REG(6, 0x3a) +#define EC_FLASH_MEMORY_TYPE_REG EC_PAGE_REG(6, 0x3b) +#define EC_FLASH_CAPACITY_REG EC_PAGE_REG(6, 0x3c) + +#define EC_MCU_SPEED_CTL_VSB_REG EC_PAGE_REG(6, 0x40) +#define EC_FLASH_CLK_VSB_DIV_MASK (3 << 0) +#define EC_FLASH_CLK_VSB_DIV_1 (0 << 0) +#define EC_FLASH_CLK_VSB_DIV_2 (1 << 0) +#define EC_FLASH_CLK_VSB_DIV_4 (2 << 0) +#define EC_FLASH_CLK_VSB_DIV_16 (3 << 0) +#define EC_FLASH_FETCH_MODE_VSB_MASK (3 << 2) +#define EC_FLASH_FETCH_MODE_VSB_READ (0 << 2) +#define EC_FLASH_FETCH_MODE_VSB_FAST_READ (1 << 2) +#define EC_FLASH_FETCH_MODE_VSB_DUAL_OUT (2 << 2) +#define EC_FLASH_FETCH_MODE_VSB_DUAL_IN_OUT (3 << 2) +#define EC_MCU_SPEED_MCLK_VSB_MASK (3 << 4) +#define EC_MCU_SPEED_MCLK_VSB_1MHZ (0 << 4) +#define EC_MCU_SPEED_MCLK_VSB_4MHZ (1 << 4) +#define EC_MCU_SPEED_MCLK_VSB_24MHZ (2 << 4) +#define EC_MCU_SPEED_MCLK_VSB_48MHZ (3 << 4) +#define EC_MCU_CACHE_VSB_EN (1 << 6) + +#define EC_MCU_SPEED_CTL_VCC_REG EC_PAGE_REG(6, 0x42) +#define EC_MCU_SPEED_MCLK_VCC_MASK 0x0f +#define EC_MCU_SPEED_MCLK_VCC_10KHZ (0 << 0) +#define EC_MCU_SPEED_MCLK_VCC_160KHZ (1 << 0) +#define EC_MCU_SPEED_MCLK_VCC_1MHZ (2 << 0) +#define EC_MCU_SPEED_MCLK_VCC_4MHZ (3 << 0) +#define EC_MCU_SPEED_MCLK_VCC_8MHZ (4 << 0) +#define EC_MCU_SPEED_MCLK_VCC_16MHZ (5 << 0) +#define EC_MCU_SPEED_MCLK_VCC_24MHZ (6 << 0) +#define EC_MCU_SPEED_MCLK_VCC_48MHZ (7 << 0) +#define EC_MCU_CACHE_VCC_EN (1 << 6) +#define EC_MCU_SPEED_VCC_LOAD_CFG (1 << 7) + +#define EC_FLASH_SPEED_CTL_VCC_REG EC_PAGE_REG(6, 0x43) +#define EC_FLASH_CLK_VCC_DIV_MASK (3 << 2) +#define EC_FLASH_CLK_VCC_DIV_1 (0 << 2) +#define EC_FLASH_CLK_VCC_DIV_2 (1 << 2) +#define EC_FLASH_CLK_VCC_DIV_4 (2 << 2) +#define EC_FLASH_CLK_VCC_DIV_16 (3 << 2) +#define EC_FLASH_FETCH_MODE_VCC_MASK (3 << 4) +#define EC_FLASH_FETCH_MODE_VCC_READ (0 << 4) +#define EC_FLASH_FETCH_MODE_VCC_FAST_READ (1 << 4) +#define EC_FLASH_FETCH_MODE_VCC_DUAL_OUT (2 << 4) +#define EC_FLASH_FETCH_MODE_VCC_DUAL_IN_OUT (3 << 4) +#define EC_FLASH_SPEED_VCC_LOAD_CFG (1 << 7) + +#define EC_FLASH_WREN_CMD_REG EC_PAGE_REG(6, 0x47) + +#define EC_FLASH_WRITE_LOCK_REG EC_PAGE_REG(6, 0x4f) +#define EC_FLASH_WRITE_LOCK (1 << 0) +#define EC_FLASH_WRITE_LOCK_EN (1 << 7) + +/* EC Page 8 - NCT6687D specific, not present in NCT6686D */ + +#define FAN9_FAN10_MANUAL_EN_REG EC_PAGE_REG(8, 0x0f) + +#define FAN_STEP_UP_TIME_REG(fan) EC_PAGE_REG(8, 0x1a + ((fan) - 1)) +#define FAN_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(8, 0x24 + ((fan) - 1)) + +/* These are also included in macros in page 1, 10 and 12 */ +#define FAN9_FUNCTION_CTL_REG EC_PAGE_REG(8, 0xe0) +#define FAN10_FUNCTION_CTL_REG EC_PAGE_REG(8, 0xe1) +#define FAN9_MANUAL_OUTPUT_VAL_REG EC_PAGE_REG(8, 0xe8) +#define FAN10_MANUAL_OUTPUT_VAL_REG EC_PAGE_REG(8, 0xe9) +#define FAN9_DUTY_REG EC_PAGE_REG(8, 0xf0) +#define FAN10_DUTY_REG EC_PAGE_REG(8, 0xf1) +#define FAN9OUT_CFG_REG EC_PAGE_REG(8, 0xf4) +#define FAN10OUT_CFG_REG EC_PAGE_REG(8, 0xf5) + +/* EC Page 9 - Fan Algorithm Function Control */ + +#define FAN_ALG_FUNCTRL_REG(fan) EC_PAGE_REG(9, 0x00 + ((fan) - 1)) +#define FAN_ALG_FUNCTRL_DTS_UB_EN (1 << 2) +#define FAN_ALG_FUNCTRL_DTS2_EN (1 << 3) +#define FAN_ALG_FUNCTRL_DTS1_EN (1 << 4) +#define FAN_ALG_FUNCTRL_TEMP_ERR (1 << 5) +#define FAN_ALG_FUNCTRL_CRIT_TEMP_EN (1 << 6) +#define FAN_ALG_FUNCTRL_ALG_EN (1 << 7) + +/* Main temperature zone decision */ +#define FAN_MTZ_DCS_DATA_REG(x, fan) EC_PAGE_REG(9, 0x10 + (x) + 4*((fan) - 1)) +/* Ambient temperature zone decision */ +#define FAN_ATZ_DCS_DATA_REG(x, fan) EC_PAGE_REG(9, 0x50 + (x) 4*((fan) - 1)) + +#define FAN_INITIAL_VALUE_REG(fan) EC_PAGE_REG(9, 0x90 + ((fan) - 1)) +#define FAN_CRIT_TEMP_CFG_REG(fan) EC_PAGE_REG(9, 0xA0 + ((fan) - 1)) +#define FAN_CRIT_TEMP_TOLERANCE_REG(fan) EC_PAGE_REG(9, 0xB0 + ((fan) - 1)) +#define FAN_TEMP_ERR_DUTY_VAL_REG(fan) EC_PAGE_REG(9, 0xC0 + ((fan) - 1)) + +#define FAN_MODE_SEL_REG(fan) EC_PAGE_REG(9, 0xD0 + ((fan) - 1)) +#define FAN_MODE_SEL_MASK 0xf +#define FAN_MODE_MODE_MANUAL (0 << 0) +#define FAN_MODE_THERMAL_CRUISE (1 << 0) +#define FAN_MODE_SPEED_CRUISE (2 << 0) +#define FAN_MODE_SMART_FAN_IV (3 << 0) +#define FAN_MODE_PID_CONTROL (4 << 0) + +/* EC Page 10 - Fan Function Control & Weight Matrix */ + +#define FAN_MANUAL_EN_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0x0f) \ + : EC_PAGE_REG(10, 0x00)) +#define FAN_MANUAL_EN(fan) (1 << (((fan) - 1) % 8)) + +#define FAN_CFG_CTRL_REG EC_PAGE_REG(10, 0x01) +#define FAN_CFG_DONE (1 << 6) +#define FAN_CFG_REQUEST (1 << 7) + +#define FAN_FUNCTION_CTRL(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0xe0 + ((fan) - 9)) \ + : EC_PAGE_REG(10, 0x08 + ((fan) - 1))) +#define FAN_FUN_MINDUTY_EN (1 << 0) +#define FAN_FUN_MANUAL_OFFSET_EN (1 << 1) +#define FAN_FUN_STARTUP_EN (1 << 2) +#define FAN_FUN_AMBIENT_FLOOR_EN (1 << 3) +#define FAN_FUN_MARKUP_TRACK_EN (1 << 4) +#define FAN_FUN_FAST_TRACK_EN (1 << 5) +#define FAN_FUN_SMART_TRACK_EN (1 << 6) +#define FAN_FUN_UNIT_PWM_DUTY (0 << 7) +#define FAN_FUN_UNIT_RPM (1 << 7) + +/* The unit for below Ambient Floor register is 100 RPM */ +#define FAN_AMB_FLOOR_RPM_TO_REG(rpm) ((rpm) ? (rpm) / 100 : 1) +#define FAN_AMB_FLOOR_MIN_OUT_START_REG(fan) EC_PAGE_REG(10, 0x10 + ((fan) - 1)) +#define FAN_AMB_FLOOR_MIN_OUT_END_REG(fan) EC_PAGE_REG(10, 0x18 + ((fan) - 1)) +#define FAN_AMB_FLOOR_MAX_OUT_REG(fan) EC_PAGE_REG(10, 0x20 + ((fan) - 1)) + +#define FAN_MANUAL_VALUE_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0xe8 + ((fan) - 9)) \ + : EC_PAGE_REG(10, 0x28 + ((fan) - 1))) + +#define FAN_MANUAL_OFFSET_REG(fan) EC_PAGE_REG(10, 0x30 + ((fan) - 1)) +#define FAN_MIN_DUTY_REG(fan) EC_PAGE_REG(10, 0x38 + ((fan) - 1)) +#define FAN_STARTUP_DUTY_REG(fan) EC_PAGE_REG(10, 0x40 + ((fan) - 1)) + +/* Smart Tracking registers */ + +#define FAN_LOW_RPM_SPEED_BOUNDARY_HI_REG EC_PAGE_REG(10, 0x48) +#define FAN_LOW_RPM_SPEED_BOUNDARY_LO_REG EC_PAGE_REG(10, 0x49) +#define FAN_HIGH_RPM_SPEED_BOUNDARY_HI_REG EC_PAGE_REG(10, 0x4a) +#define FAN_HIGH_RPM_SPEED_BOUNDARY_LO_REG EC_PAGE_REG(10, 0x4b) + +#define FAN_LOW_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4c) +#define FAN_MID_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4d) +#define FAN_HIGH_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4e) + +#define FAN_TRACKING_STEP_REG EC_PAGE_REG(10, 0x4f) +#define FAN_TRACK_STEP_DOWN_MASK 0x0f +#define FAN_TRACK_STEP_DOWN_SHIFT 0 +#define FAN_TRACK_STEP_UP_MASK 0x0f +#define FAN_TRACK_STEP_UP_SHIFT 4 + +#define FAN_FAST_TRACK_TEMP_BOUNDARY_REG EC_PAGE_REG(10, 0x50) + +/* Below definitions are dividers for fast tracking weight registers */ +#define FAN_FAST_TRACK_WEIGHT_DIV_1 1 +#define FAN_FAST_TRACK_WEIGHT_DIV_2 2 +#define FAN_FAST_TRACK_WEIGHT_DIV_4 3 +#define FAN_FAST_TRACK_WEIGHT_DIV_8 4 +#define FAN_FAST_TRACK_WEIGHT_DIV_16 5 +#define FAN_FAST_TRACK_WEIGHT_DIV_32 6 +#define FAN_FAST_TRACK_WEIGHT_DIV_64 7 + +/* Below definitions are shifts and masks for fast tracking weight registers */ +#define FAN_FAST_TRACK_WEIGHT_DOWN_MASK 0x07 +#define FAN_FAST_TRACK_WEIGHT_DOWN_SHIFT 0 +#define FAN_FAST_TRACK_WEIGHT_UP_MASK 0x07 +#define FAN_FAST_TRACK_WEIGHT_UP_SHIFT 4 + +#define FAN_LOW_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x51) +#define FAN_MID_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x52) +#define FAN_HIGH_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x53) + +/* Below definitions are shifts and masks for fast tracking duty step registers */ +#define FAN_FAST_TRACK_DUTY_STEP_MASK 0x0f +#define FAN_FAST_TRACK_DUTY_STEP_SHIFT 0 + +#define FAN_LOW_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x54) +#define FAN_MID_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x55) +#define FAN_HIGH_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x56) + +#define FAN_MARKUP_TRACK_AMB_TEMP_BOUNDARY_REG EC_PAGE_REG(10, 0x57) +#define FAN_MARKUP_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x58) +#define FAN_MARKUP_TRACK_WEIGHT_MASK 0x07 +#define FAN_MARKUP_TRACK_WEIGHT_SHIFT 0 + +/* Intel Sensor Based (DTS) Fan Control registers */ + +#define ITL_TEMP_START_POINT_REG EC_PAGE_REG(10, 0x59) +#define ITL_TEMP_END_POINT_REG EC_PAGE_REG(10, 0x5a) +#define ITL_AMB_TEMP_START_POINT_REG(x) EC_PAGE_REG(10, 0x5b + (x)) + +#define ITL_RPM_START_POINT_HI_REG(x) EC_PAGE_REG(10, 0x60 + 2*(x)) +#define ITL_RPM_START_POINT_LO_REG(x) EC_PAGE_REG(10, 0x61 + 2*(x)) +#define ITL_RPM_END_POINT_HI_REG(x) EC_PAGE_REG(10, 0x6a + 2*(x)) +#define ITL_RPM_END_POINT_LO_REG(x) EC_PAGE_REG(10, 0x6a + 2*(x)) +#define ITL_RPM_MAX_SPEED_HI_REG EC_PAGE_REG(10, 0x74) +#define ITL_RPM_MAX_SPEED_LO_REG EC_PAGE_REG(10, 0x75) + +#define ITL_DTS_CFG_REG EC_PAGE_REG(10, 0x76) +#define ITL_DTS_PECI_AGENT_IDX_SEL_MASK 0x0f +#define ITL_DTS_PECI_AGENT_IDX_SEL_SHIFT 0 +#define ITL_DTS_PECI_CFG_ADJUSTMENT (1 << 7) + +#define AMBIENT_FLOOR_TEMP_START_POINT_REG EC_PAGE_REG(10, 0x77) +#define AMBIENT_FLOOR_TEMP_END_POINT_REG EC_PAGE_REG(10, 0x78) + +/* DTS 2.0 sensor registers */ + +#define DTS2_TARGET_MARGIN_REG EC_PAGE_REG(10, 0x59) +#define DTS2_TCONTROL_REG EC_PAGE_REG(10, 0x5a) +#define DTS2_TCONTROL_OFFSET_REG EC_PAGE_REG(10, 0x5b) +#define DTS2_TARGET_TOLERANCE_REG EC_PAGE_REG(10, 0x5c) +#define DTS2_DIVISOR_REG EC_PAGE_REG(10, 0x5d) +#define DTS2_STEP_SPEED_HI_REG EC_PAGE_REG(10, 0x5e) +#define DTS2_STEP_SPEED_LO_REG EC_PAGE_REG(10, 0x5f) +#define DTS2_MIN_SPEED_HI_REG EC_PAGE_REG(10, 0x60) +#define DTS2_MIN_SPEED_LO_REG EC_PAGE_REG(10, 0x61) +#define DTS2_DELAY_TIME_COUNTER_REG EC_PAGE_REG(10, 0x62) + +/* Weight Matrix Configuration */ + +#define FAN_ALG_ENGINE_WEIGHT_EN_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(10, 0xC1 + 8*((fan) - 9)) \ + : EC_PAGE_REG(10, 0x80 + 8*((fan) - 1))) +#define FAN_ALG_ENGINE_WEIGHT_CHANNEL_EN(fan) (1 << (((fan) - 1) % 8)) + +#define FAN_ALG_ENGINE_WEIGHT_VAL_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(10, 0xC3 + ((fan) - 9)/2 + 8*((fan) - 9)) \ + : EC_PAGE_REG(10, 0x84 + ((fan) - 1)/2 + 8*((fan) - 1))) +#define FAN_ALG_ENGINE_WEIGHT_MASK(fan) (0xf << (4 * (((fan) - 1) % 2))) +#define FAN_ALG_ENGINE_WEIGHT_SHIFT(fan) (4 * (((fan) - 1) % 2)) + +/* EC Page 11 - Thermal Cruise, Speed Cruise, Smart Fan IV */ + +#define FAN_PWM_PERCENT_TO_HEX(x) ((x) * 255 / 100) + + +/* For x larger than 10, the registers are placed in page 12 */ +/* Thermal Cruise (TC) Registers */ + +#define FAN_TC_TARGET_TEMP_TOLERANCE_REG(fan) EC_PAGE_REG(11, 0x00 + 24*((fan) - 1)) +#define FAN_TC_TEMP_TOLERANCE_MASK 0xf +#define FAN_TC_TEMP_TOLERANCE_SHIFT 0 + +#define FAN_TC_TARGET_TEMP_REG(fan) EC_PAGE_REG(11, 0x01 + 24*((fan) - 1)) +#define FAN_TC_TARGET_TEMP_MASK 0x7f +#define FAN_TC_TARGET_TEMP_SHIFT 0 +#define FAN_TC_KEEP_MIN_OUTPUT (1 << 7) + +#define FAN_TC_STOP_VALUE_REG(fan) EC_PAGE_REG(11, 0x02 + 24*((fan) - 1)) + +#define FAN_TC_TIME_TO_SECONDS(x) ((x)*10) +#define FAN_TC_STOP_TIME_REG(fan) EC_PAGE_REG(11, 0x03 + 24*((fan) - 1)) +#define FAN_TC_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(11, 0x04 + 24*((fan) - 1)) +#define FAN_TC_STEP_UP_TIME_REG(fan) EC_PAGE_REG(11, 0x05 + 24*((fan) - 1)) + +/* Speed Cruise (SC) Registers */ + +#define FAN_SC_TARGET_RPM_HI_REG(fan) EC_PAGE_REG(11, 0x00 + 24*((fan) - 1)) +#define FAN_SC_TARGET_RPM_LO_REG(fan) EC_PAGE_REG(11, 0x01 + 24*((fan) - 1)) +#define FAN_SC_TARGET_RPM_TOLERANCE_HI_REG(fan) EC_PAGE_REG(11, 0x02 + 24*((fan) - 1)) +#define FAN_SC_TARGET_RPM_TOLERANCE_LO_REG(fan) EC_PAGE_REG(11, 0x03 + 24*((fan) - 1)) + +#define FAN_SC_TIME_TO_SECONDS(x) ((x)*10) +#define FAN_SC_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(11, 0x04 + 24*((fan) - 1)) +#define FAN_SC_STEP_UP_TIME_REG(fan) EC_PAGE_REG(11, 0x05 + 24*((fan) - 1)) + +/* Smart Fan IV (SF4) Registers */ + +#define FAN_SF4_TEMP_LVL_REG(fan, level) EC_PAGE_REG(11, 0x00 + (level) + 24*((fan) - 1)) +#define FAN_SF4_PWM_RPM_LVL_HI_REG(fan, level) EC_PAGE_REG(11, 0x07 + (level)*2 + 24*((fan) - 1)) +#define FAN_SF4_PWM_RPM_LVL_LO_REG(fan, level) EC_PAGE_REG(11, 0x08 + (level)*2 + 24*((fan) - 1)) +#define FAN_SF4_TEMP_OFF_HYSTHERESIS_REG(fan) EC_PAGE_REG(11, 0x15 + 24*((fan) - 1)) +#define FAN_SF4_TEMP_CUT_OFF_REG(fan) EC_PAGE_REG(11, 0x16 + 24*((fan) - 1)) +#define FAN_SF4_TEMP_OFF_DELAY_REG(fan) EC_PAGE_REG(11, 0x17 + 24*((fan) - 1)) + +/* EC Page 12 - Fan Function Control */ + +#define FAN_ENGINE_STS_REG EC_PAGE_REG(12, 0xf8) +#define FAN_PECI_CFG_ADJUSTED (1 << 1) +#define FAN_UNFINISHED_FLAG (1 << 2) +#define FAN_CFG_PHASE (1 << 3) +#define FAN_CFG_INVALID (1 << 4) +#define FAN_CFG_CHECK_DONE (1 << 5) +#define FAN_CFG_LOCK (1 << 6) +#define FAN_DRIVE_BY_MOD_SEL (0 << 7) +#define FAN_DRIVE_BY_DEFAULT_VAL (1 << 7) + +#define FAN_LAST_ERROR_CODE_REG EC_PAGE_REG(12, 0xf9) +#define FAN_NO_ERROR 0x00 +#define FAN_ERR_MODE_SELECT 0x01 +#define FAN_ERR_CRIT_TEMP_PROTECT 0x02 +#define FAN_ERR_ITL_FAN_CONTROL 0x04 +#define FAN_ERR_SMART_TRACKING 0x05 +#define FAN_ERR_THERMAL_CRUISE 0x10 +#define FAN_ERR_SPEED_CRUISE 0x20 +#define FAN_ERR_SMART_FAN_IV 0x40 +#define FAN_ERR_PID_CONTROL 0x50 + +#define FAN_CHANNEL_EN_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(12, 0xfb) \ + : EC_PAGE_REG(12, 0xfc)) +#define FAN_CHANNEL_EN(fan) (1 << (((fan) - 1) % 8)) + +#define FAN_DEFAULT_VAL_REG EC_PAGE_REG(12, 0xfd) + +extern uint16_t nct6687d_hwm_base; + +static __always_inline void hwm_reg_and_or(uint16_t page_reg, uint8_t and_mask, uint8_t or_mask) +{ + assert(nct6687d_hwm_base != 0); + nct6687d_ec_and_or_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, + and_mask, or_mask); +} + +static __always_inline void hwm_reg_set_bits(uint16_t page_reg, uint8_t bits) +{ + assert(nct6687d_hwm_base != 0); + nct6687d_ec_and_or_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, + ~bits, bits); +} + +static __always_inline void hwm_reg_write(uint16_t page_reg, uint8_t value) +{ + assert(nct6687d_hwm_base != 0); + nct6687d_ec_write_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, value); +} + +static __always_inline uint8_t hwm_reg_read(uint16_t page_reg) +{ + assert(nct6687d_hwm_base != 0); + return nct6687d_ec_read_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff); +} + +#endif /* SUPERIO_NUVOTON_NCT6687D_HWM_H */ diff --git a/src/superio/nuvoton/nct6687d/superio.c b/src/superio/nuvoton/nct6687d/superio.c index c28092736f4..ef9e323dd9c 100644 --- a/src/superio/nuvoton/nct6687d/superio.c +++ b/src/superio/nuvoton/nct6687d/superio.c @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include #include #include +#include "chip.h" #include "nct6687d.h" #define MAINBOARD_POWER_OFF 0 @@ -21,35 +23,98 @@ #define NCT6687D_ACPI_POWER_PREV_STATE (2 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT) #define NCT6687D_ACPI_POWER_USER_DEFINED (3 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT) +/* 0xe7 register definitions */ +#define NCT6687D_ACPI_ON_PSOUT_MASK 0x10 +#define NCT6687D_ACPI_ON_PSOUT_SHIFT 4 +#define NCT6687D_ACPI_ON_PSOUT_DIS (0 << NCT6687D_ACPI_ON_PSOUT_SHIFT) +#define NCT6687D_ACPI_ON_PSOUT_EN (1 << NCT6687D_ACPI_ON_PSOUT_SHIFT) + +static void nct6687d_configure_power_fail_state(struct device *dev) +{ + uint8_t reg_eb, reg_e7; + uint8_t power_status; + /* Set power state after power fail */ + power_status = dasharo_get_power_on_after_fail(); + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + reg_eb = pnp_read_config(dev, 0xeb); + reg_e7 = pnp_read_config(dev, 0xe7); + reg_eb &= ~NCT6687D_ACPI_POWER_LOSS_CONTROL_MASK; + reg_e7 &= ~NCT6687D_ACPI_ON_PSOUT_MASK; + + if (power_status == MAINBOARD_POWER_ON) { + reg_eb |= NCT6687D_ACPI_POWER_ALWAYS_ON; + reg_e7 |= NCT6687D_ACPI_ON_PSOUT_EN; + } else if (power_status == MAINBOARD_POWER_KEEP) { + reg_eb |= NCT6687D_ACPI_POWER_PREV_STATE; + reg_e7 |= NCT6687D_ACPI_ON_PSOUT_EN; + } + + pnp_write_config(dev, 0xeb, reg_eb); + pnp_write_config(dev, 0xe7, reg_e7); + pnp_exit_conf_mode(dev); + + printk(BIOS_INFO, "set power %s after power fail\n", + power_status ? "on" : "off"); +} + +static void nct6687d_configure_ps2_wake(struct device *dev) +{ + uint8_t reg; + struct device *ps2_dev = dev_find_slot_pnp(dev->path.pnp.port, NCT6687D_KBC); + + if (!ps2_dev || !ps2_dev->enabled) + return; + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + reg = pnp_read_config(dev, 0xe0); + reg |= 0x01; /* Any character from the keybaord can wake up the system */ + reg &= 0xed; /* Clear MSXKEY and MSRKEY to allow either left or right click to wake */ + pnp_write_config(dev, 0xe0, reg); + + reg = pnp_read_config(dev, 0xe6); + reg |= 0x80; /* Set ENMDAT to allow either left or right click to wake */ + pnp_write_config(dev, 0xe6, reg); + + reg = pnp_read_config(dev, 0xe7); + reg &= 0x3f; /* Disable 2nd and 3rd set of wake-up key combinations */ + reg |= 0x20; /* Enable Win98 dedicated wake up key */ + pnp_write_config(dev, 0xe7, reg); + + reg = pnp_read_config(dev, 0xe4); + reg |= 0xc0; /* Enable keyboard and mouse wake via PSOUT# */ + reg |= 0x08; /* Enable keyboard wake with any key */ + pnp_write_config(dev, 0xe4, reg); + + pnp_exit_conf_mode(dev); +} + static void nct6687d_init(struct device *dev) { + const struct superio_nuvoton_nct6687d_config *conf; + const struct resource *res; + if (!dev->enabled) return; - uint8_t byte; - uint8_t power_status; switch (dev->path.pnp.device) { - /* TODO: Might potentially need code for EC, GPIOs, etc. */ case NCT6687D_KBC: pc_keyboard_init(PROBE_AUX_DEVICE); break; case NCT6687D_ACPI: - /* Set power state after power fail */ - power_status = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); - pnp_enter_conf_mode(dev); - pnp_set_logical_device(dev); - byte = pnp_read_config(dev, 0xeb); - byte &= ~NCT6687D_ACPI_POWER_LOSS_CONTROL_MASK; - if (power_status == MAINBOARD_POWER_ON) - byte |= NCT6687D_ACPI_POWER_ALWAYS_ON; - else if (power_status == MAINBOARD_POWER_KEEP) - byte |= NCT6687D_ACPI_POWER_PREV_STATE; - pnp_write_config(dev, 0xeb, byte); - pnp_exit_conf_mode(dev); - printk(BIOS_INFO, "set power %s after power fail\n", - power_status ? "on" : "off"); + nct6687d_configure_power_fail_state(dev); + nct6687d_configure_ps2_wake(dev); break; + case NCT6687D_EC: + conf = dev->chip_info; + res = probe_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + nct6687d_hwm_init(res->base, conf); } } diff --git a/src/superio/smsc/sch5545/acpi/superio.asl b/src/superio/smsc/sch5545/acpi/superio.asl index 06ef7b018be..e3c9be77a66 100644 --- a/src/superio/smsc/sch5545/acpi/superio.asl +++ b/src/superio/smsc/sch5545/acpi/superio.asl @@ -288,7 +288,6 @@ Device(SIO1) { PMS1 = (Local0 | 0x18) Local0 = PMES PMES = (Local0 | 1) - Local0 = PME1 If (KBFG) { @@ -337,23 +336,16 @@ Device(SIO1) { /* SIO wake method */ Method (SIOW, 1, NotSerialized) { - If (Arg0 == 1) - { - GPKM () - ENTER_CONFIG_MODE (1) - Local0 = OPT0 - OPT0 = (Local0 & 0x9F) - EXIT_CONFIG_MODE () - } - - If (Arg0 == 0x03) + If (Arg0 == 0x03 || Arg0 == 1) { GPKM () ENTER_CONFIG_MODE (1) Local0 = OPT0 OPT0 = (Local0 & 0x9F) - OPT2 |= 1 - OPT2 &= 0xFE + If (Arg0 == 0x03) { + OPT2 |= 1 + OPT2 &= 0xFE + } EXIT_CONFIG_MODE () } } diff --git a/src/vendorcode/Makefile.mk b/src/vendorcode/Makefile.mk index 36a13bb6f67..3bf1ad22a08 100644 --- a/src/vendorcode/Makefile.mk +++ b/src/vendorcode/Makefile.mk @@ -5,3 +5,4 @@ subdirs-y += siemens subdirs-y += cavium subdirs-y += eltan subdirs-y += mediatek +subdirs-y += dasharo diff --git a/src/vendorcode/amd/pi/Makefile.mk b/src/vendorcode/amd/pi/Makefile.mk index 446e9d47794..46797224489 100644 --- a/src/vendorcode/amd/pi/Makefile.mk +++ b/src/vendorcode/amd/pi/Makefile.mk @@ -106,6 +106,7 @@ CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_postcar:= $(CC_postcar) -I$(src)/southbridge/amd/pi/hudson -I$(AGESA_ROOT)/binaryPI CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_smm := $(CC_smm) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_64 := $(CC_x86_64) $(AGESA_INC) $(AGESA_CFLAGS) @@ -165,9 +166,11 @@ ramstage-libs += $(agesa_output_path)/libagesa.a ####################################################################### -cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME) -$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE) -$(CONFIG_AGESA_CBFS_NAME)-type := raw -$(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) +AGESA_CBFS_FILE=$(call strip_quotes,$(CONFIG_AGESA_CBFS_NAME)) + +cbfs-files-y += $(AGESA_CBFS_FILE) +$(AGESA_CBFS_FILE)-file := $(CONFIG_AGESA_BINARY_PI_FILE) +$(AGESA_CBFS_FILE)-type := raw +$(AGESA_CBFS_FILE)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) endif diff --git a/src/vendorcode/dasharo/Kconfig b/src/vendorcode/dasharo/Kconfig new file mode 100644 index 00000000000..9eb23f90836 --- /dev/null +++ b/src/vendorcode/dasharo/Kconfig @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if GENERATE_SMBIOS_TABLES + +config BIOS_VENDOR + default "3mdeb" + +endif + +comment "Dasharo" + +menu "Dasharo Configuration" + +config DASHARO_PREFER_S3_SLEEP + bool "Prefer S3 suspend over S0ix" + depends on HAVE_ACPI_RESUME + default n if PAYLOAD_EDK2 + default y + help + Enables S3 sleep state as default in the coreboot and EDK2 UEFI Payload. + +config DASHARO_FIRMWARE_UPDATE_MODE + bool "Enable Firmware Update Mode in the project" + default y if PAYLOAD_EDK2 + help + Enables Frimware Update Flow in coreboot and shows the FUM option in + Dasharo menu. + +endmenu + diff --git a/src/vendorcode/dasharo/Makefile.mk b/src/vendorcode/dasharo/Makefile.mk new file mode 100644 index 00000000000..7bc03c60a2b --- /dev/null +++ b/src/vendorcode/dasharo/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -Isrc/vendorcode/dasharo/include/ + +smm-y += options.c +all-y += options.c + +ramstage-y += smbios.c diff --git a/src/vendorcode/dasharo/include/dasharo/options.h b/src/vendorcode/dasharo/include/dasharo/options.h new file mode 100644 index 00000000000..f4220647e13 --- /dev/null +++ b/src/vendorcode/dasharo/include/dasharo/options.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DASHARO_OPTIONS_H +#define DASHARO_OPTIONS_H + +#include +#include + +#define SLEEP_TYPE_OPTION_S0IX 0 +#define SLEEP_TYPE_OPTION_S3 1 + +#define FAN_CURVE_OPTION_SILENT 0 +#define FAN_CURVE_OPTION_PERFORMANCE 1 +#define FAN_CURVE_OPTION_OFF 2 + +#define FAN_CURVE_OPTION_DEFAULT FAN_CURVE_OPTION_SILENT + +#define SLEEP_TYPE_OPTION_S0IX 0 +#define SLEEP_TYPE_OPTION_S3 1 + +#define CAMERA_ENABLED_OPTION 1 +#define CAMERA_DISABLED_OPTION 0 + +#define CAMERA_ENABLEMENT_DEFAULT CAMERA_ENABLED_OPTION + +#define BATTERY_START_THRESHOLD_DEFAULT 95 +#define BATTERY_STOP_THRESHOLD_DEFAULT 98 + +#define ALL_CORES_ACTIVE 0xff + +enum cse_disable_mode { + ME_MODE_ENABLE = 0, + ME_MODE_DISABLE_HECI = 1, + ME_MODE_DISABLE_HAP = 2, + /* Not a variable value, but serves a purpose of disabling ME in boot flow */ + ME_MODE_DISABLE_HMRFPO = 10 +}; + +enum usb_port_power_opt { + USB_PORT_ON_WHEN_POWERED = 0, + USB_PORT_ALWAYS_ON = 1, +}; + +enum dgpu_state { + IGPU_ONLY = 0, + NVIDIA_OPTIMUS = 1, + DGPU_ONLY = 2, +}; + +struct watchdog_config { + bool wdt_enable; + uint16_t wdt_timeout; +} __packed; + +struct fan_point { + uint8_t temp; + uint8_t duty; +} __packed; + +struct fan_curve { + struct fan_point point1; + struct fan_point point2; + struct fan_point point3; + struct fan_point point4; +} __packed; + +struct battery_config { + uint8_t start_threshold; + uint8_t stop_threshold; +} __packed; + +/* Attempts to wipe the SMMSTORE region in order to reset EFI options. + * UEFIPayload will populate it with default values upon boot. + * + * Result: + * - CB_SUCCESS - Success + * - CB_ERR - Failure, including partial wipe + */ +enum cb_err dasharo_reset_options(void); + +/* Looks up "power_on_after_fail" option and Dasharo/"PowerFailureState" + * variable. + * + * Result (same as MAINBOARD_POWER_STATE_*): + * - 0 - stay powered OFF + * - 1 - power ON + * - 2 - restore previous state + */ +uint8_t dasharo_get_power_on_after_fail(void); + +/* Looks up Dasharo/"UsbPortPower" variable. + * + * Result: + * - 0 - Only when powered on (default) + * - 1 - Always Enabled + */ +uint8_t dasharo_get_usb_port_power(void); + +/* Looks up Dasharo/"PCIeResizeableBarsEnabled" variable if resizable PCIe BARs + * support was enabled at compile-time. + * + * Result: + * - true - resizeable PCIe BARs are supported and enabled + * - false - resizeable PCIe BARs are disabled or not supported + */ +bool dasharo_resizeable_bars_enabled(void); + +/* Looks Dasharo/"LockBios" variable if bootmedia lock was enabled at compile + * time. + * + * Result: + * - true - bootmedia lock is supported and enabled + * - false - bootmedia lock is disabled or not supported + */ +bool is_vboot_locking_permitted(void); + +/* Looks Dasharo/"IommuConfig" variable if early DMA protection lock was + * enabled at compile time. + * + * Result: + * - true - DMA protection is supported and enabled + * - false - DMA protection is disabled or not supported + */ +bool dma_protection_enabled(void); + +/* Looks Dasharo/"MeMode" variable if ME should be enabeld or disabled. + * + * Result: + * - 0 - ME enabled + * - 1 - ME soft disabled + * - 2 - ME HAP disabled + */ +uint8_t cse_get_me_disable_mode(void); + +/* Looks Dasharo/"SmmBwp" variable if SMM BIOS Write Protection was + * enabled at compile time. + * + * Result: + * - true - DMA protection is supported and enabled + * - false - DMA protection is disabled or not supported + */ +bool is_smm_bwp_permitted(void); + +/* Looks Dasharo/"WatchdogCOnfig" variable if OC Watchdog was + * enabled at compile time. + * + * Result: + * - true - DMA protection is supported and enabled + * - false - DMA protection is disabled or not supported + */ +void get_watchdog_config(struct watchdog_config *wdt_cfg); + +/* Looks Dasharo/"WatchdogCOnfig" variable if PS/2 controller should be + * enabled. The function should be called from mainboard code to disable + * appropriate PNP device in devicetree. + * + * Result: + * - true - PS/2 controller enabled + * - false - PS/2 controller disabled + */ +bool get_ps2_option(void); + +/* Looks Dasharo/"SleepType" variable to check which sleep type should be + * enabled. + * + * Result: + * - 0 - S0ix + * - 1 - S3 + */ +uint8_t get_sleep_type_option(void); + +/* Looks Dasharo/"FanCurveOption" variable to check which fan curve EC should + * apply. + * + * + * Result: + * - 0 - Silent profile + * - 1 - Performance profile + */ +uint8_t get_fan_curve_option(void); + +/* Looks Dasharo/"EnableCamera" variable to checkif camera USB port should be + * emabled. + * + * Result: + * - true - camera enabled + * - false - camera disabled + */ +bool get_camera_option(void); + +/* Looks Dasharo/"EnableWifiBt" variable to check if WiFi and Bluetooth should + * be enabled. + * + * Result: + * - true - Wireless radios enabled + * - false - Wireless radios disabled + */ +bool get_wireless_option(void); + +/* Looks Dasharo/"BatteryConfig" variable to check battery configuration + * (charge thresholds) + * + * Arguments: + * - bat_cfg - battery configuration parameters + */ +void get_battery_config(struct battery_config *bat_cfg); + +/* Looks Dasharo/"Type2SN" variable to check if Serial Number was saved. + * + * Arguments: + * - serial_number - pointer where the serial number should be returned + * Result: + * - true - Serial Number present in EFI variables + * - false - Serial Number not present in EFI variables + */ +bool get_serial_number_from_efivar(char *serial_number); + +/* Looks Dasharo/"Type1UUID" variable to check if system UUID was saved. + * + * Arguments: + * - uuid - pointer where the UUID should be returned + * Result: + * - true - System UUID present in EFI variables + * - false - SystemUUID not present in EFI variables + */ +bool get_uuid_from_efivar(uint8_t *uuid); + +/* Looks up Dasharo/"MemoryProfile" variable to know which memory profile to + * enable. + * + * Result (values of FSP_M_CONFIG::SpdProfileSelected): + * - 0 - Default SPD Profile + * - 1 - Custom Profile + * - 2 - XMP Profile 1 + * - 3 - XMP Profile 2 + * - 4 - XMP Profile 3 + * - 5 - XMP User Profile 4 + * - 6 - XMP User Profile 5 + */ +uint8_t dasharo_get_memory_profile(void); + +/* Looks up PciePwrMgmt field in APU/"ApuConfig" to know whether to enable + * Clock Power Management, ASPM L0s and L1 features on PCI Express ports. + * + * Result: + * - true - PM features on PCI express ports are enabled + * - false - PM features on PCI express ports are disabled + */ +bool dasharo_apu_pcie_pm_enabled(void); + +/* Looks up WatchdogEnable and WatchdogTimeout fields in APU/"ApuConfig" to + * know whether to enable watchdog on boot and what period to use. + * + * Result: + * - = 0 - watchdog is disabled + * - > 0 - watchdog is enabled and should be configured to reboot after + * returned number of seconds has passed + */ +uint16_t dasharo_apu_watchdog_timeout(void); + +/* Looks up CorePerfBoost field in APU/"ApuConfig" to know whether to enable + * CPU boost. + * + * Result: + * - true - CPU boost should be enabled on boot + * - false - CPU boost should not be enabled on boot + */ +bool dasharo_apu_cpu_boost_enabled(void); + +/* Looks Dasharo/"CoreActiveCount" variable to check how many cores should be + * active. + * + * + * Result: + * - Number of active cores + */ +uint8_t get_active_core_count_option(void); + +/* Looks Dasharo/"SmallCoreActiveCount" variable to check how many small cores + * should be active. + * + * + * Result: + * - Number of active cores + */ +uint8_t get_active_small_core_count_option(void); + +/* Looks Dasharo/"HyperThreading" variable to check Hyper-Threading should be + * enabled. + * + * + * Result: + * - true - Hyper-Threading enabled + * - false - Hyper-Threading disabled + */ +bool get_hyper_threading_option(void); + +/* Looks up Dasharo/"CpuThrottlingOffset" variable to return the CPU + * TCC offset temperature. + * + * Arguments: + * - tcc_offset - default platform value of TCC offset + * Result: + * returns uint8 - TCC offset from Tjmax + */ +uint8_t get_cpu_throttling_offset(uint8_t tcc_offset); + +/* + * Get dGPU mode option state + * + * + * Result: + * - 0 - iGPU only + * - 1 - NVIDIA Optimus (iGPU + dGPU) + * - 2 - dGPU only + */ +enum dgpu_state dasharo_dgpu_state(void); + +/* Looks Dasharo/"IBECC" variable to check In-Band ECC should be + * enabled. + * + * Arguments: + * - default - default platform value of IBECC + * Result: + * - true - In-Band ECC enabled + * - false - In-Band ECC disabled + */ +bool get_ibecc_option(bool ibecc_default); + +#endif /* DASHARO_OPTIONS_H */ diff --git a/src/vendorcode/dasharo/options.c b/src/vendorcode/dasharo/options.c new file mode 100644 index 00000000000..872e3e237b7 --- /dev/null +++ b/src/vendorcode/dasharo/options.c @@ -0,0 +1,614 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_CSE) +#include +#endif + +_Static_assert(sizeof(bool) == 1, "Size of bool, must be 1"); + +/* Keeping field names as in EDK to make things easier to follow, types are + * different though. */ +struct apu_config_t { + bool CorePerfBoost; + bool WatchdogEnable; + uint16_t WatchdogTimeout; /* in seconds */ + bool PciePwrMgmt; +} __packed; + +static const EFI_GUID dasharo_system_features_guid = { + 0xd15b327e, 0xff2d, 0x4fc1, { 0xab, 0xf6, 0xc1, 0x2b, 0xd0, 0x8c, 0x13, 0x59 } +}; + +static const EFI_GUID dasharo_apu_features_guid = { + 0x6f4e051b, 0x1c10, 0x422a, { 0x98, 0xcf, 0x96, 0x2e, 0x78, 0x36, 0x5c, 0x74 } +}; + +/* Value of *var is not changed on failure, so it's safe to initialize it with + * a default before the call. */ +static enum cb_err read_u8_var(const char *var_name, uint8_t *var) +{ + struct region_device rdev; + + if (CONFIG(SMMSTORE_V2) && !smmstore_lookup_region(&rdev)) { + uint8_t tmp; + uint32_t size = sizeof(tmp); + enum cb_err ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, + var_name, &tmp, &size); + if (ret == CB_SUCCESS) { + if (size == sizeof(tmp)) { + *var = tmp; + return CB_SUCCESS; + } + + printk(BIOS_WARNING, + "dasharo: EFI variable \"%s\" of wrong size (%d instead of 1)\n", + var_name, size); + } + } + + return CB_ERR; +} + +/* Value of *var is not changed on failure, so it's safe to initialize it with + * a default before the call. */ +static enum cb_err read_bool_var(const char *var_name, bool *var) +{ + uint8_t tmp; + + if (read_u8_var(var_name, &tmp) == CB_SUCCESS) { + *var = tmp != 0; + return CB_SUCCESS; + } + + return CB_ERR; +} + +/* Never fails, just returns defaults on error. */ +static struct apu_config_t get_apu_config(void) +{ + static bool init_done; + static struct apu_config_t cfg; + + if (init_done) + return cfg; + + /* Start with defaults as in EDK. */ + struct apu_config_t val = { + .CorePerfBoost = true, + .WatchdogEnable = false, + .WatchdogTimeout = 60, + .PciePwrMgmt = false, + }; + + cfg = val; + + struct region_device rdev; + if (CONFIG(SMMSTORE_V2) && !smmstore_lookup_region(&rdev)) { + uint32_t size = sizeof(val); + enum cb_err ret = efi_fv_get_option(&rdev, + &dasharo_apu_features_guid, + "ApuConfig", &val, &size); + /* Deliberately allowing mismatched size of structure to allow + * compatible changes. All known fields are initialized and + * extra fields are irrelevant. */ + if (ret == CB_SUCCESS) + cfg = val; + } + + init_done = true; + return cfg; +} + +enum cb_err dasharo_reset_options(void) +{ + struct region_device rdev; + ssize_t res; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return CB_ERR; + + res = rdev_eraseat(&rdev, 0, region_device_sz(&rdev)); + if (res != region_device_sz(&rdev)) + return CB_ERR; + + return CB_SUCCESS; +} + +uint8_t dasharo_get_power_on_after_fail(void) +{ + uint8_t power_status; + + power_status = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + + /* When present, EFI variable has higher priority. */ + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("PowerFailureState", &power_status); + + return power_status; +} + +uint8_t dasharo_get_usb_port_power(void) +{ + uint8_t usb_port_power = USB_PORT_ON_WHEN_POWERED; + + /* When present, EFI variable has higher priority. */ + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("UsbPortPower", &usb_port_power); + + if (usb_port_power > USB_PORT_ALWAYS_ON) + return USB_PORT_ON_WHEN_POWERED; + + return usb_port_power; +} + +bool dasharo_resizeable_bars_enabled(void) +{ + static bool enabled = false; + static bool read_once = false; + + if (!CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS)) + return false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) { + if (!read_once) + read_bool_var("PCIeResizeableBarsEnabled", &enabled); + /* + * This variable would be read for each PCIe device. + * Avoid it by reading the variable only once. + */ + read_once = true; + } else { + /* If no variables are not enabled, follow Kconfig */ + return true; + } + + return enabled; +} + +bool is_vboot_locking_permitted(void) +{ + bool lock = true; + bool fum = false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("FirmwareUpdateMode", &fum); + else + return !CONFIG(BOOTMEDIA_LOCK_NONE); + + /* Disable lock if in Firmware Update Mode */ + if (CONFIG(DASHARO_FIRMWARE_UPDATE_MODE) && fum) + return false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("LockBios", &lock); + + return lock; +} + +bool dma_protection_enabled(void) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + struct iommu_config { + bool iommu_enable; + bool iommu_handoff; + } __packed iommu_var; + uint32_t size; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return false; + + size = sizeof(iommu_var); + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "IommuConfig", + &iommu_var, &size); + + if (ret != CB_SUCCESS) + return false; + + return iommu_var.iommu_enable; +} + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_CSE) +static void disable_me_hmrfpo(uint8_t *var) +{ + int hmrfpo_sts = cse_hmrfpo_get_status(); + + if (hmrfpo_sts == -1) { + printk (BIOS_DEBUG, "ME HMRFPO Get Status failed\n"); + goto hmrfpo_error; + } + + printk (BIOS_DEBUG, "ME HMRFPO status: "); + switch (hmrfpo_sts) { + case 0: + printk (BIOS_DEBUG, "DISABLED\n"); + if (cse_hmrfpo_enable() != CB_SUCCESS) + goto hmrfpo_error; + else + do_global_reset(); /* No return */ + break; + case 1: + printk (BIOS_DEBUG, "LOCKED\n"); + goto hmrfpo_error; + case 2: + printk (BIOS_DEBUG, "ENABLED\n"); + /* Override ME disable method to not switch ME mode */ + *var = ME_MODE_DISABLE_HMRFPO; + /* TODO: disable HMRFPO here if not in FUM? Reboot disables HMRFPO. */ + break; + default: + printk (BIOS_DEBUG, "UNKNOWN\n"); + goto hmrfpo_error; + } + + return; + +hmrfpo_error: + /* Try other available methods if something goes wrong */ + *var = CONFIG(HAVE_INTEL_ME_HAP) ? ME_MODE_DISABLE_HAP + : ME_MODE_DISABLE_HECI; +} + +uint8_t cse_get_me_disable_mode(void) +{ + uint8_t var = CONFIG_INTEL_ME_DEFAULT_STATE; + bool fum = false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) { + read_bool_var("FirmwareUpdateMode", &fum); + read_u8_var("MeMode", &var); + } + + /* + * Disable ME via HMRPFO if in Firmware Update Mode + * Don't do it if capsules are supported, as capsule updates are not + * currently compatible with HMRFPO + */ + if (CONFIG(DASHARO_FIRMWARE_UPDATE_MODE) && fum && !(CONFIG(DRIVERS_EFI_UPDATE_CAPSULES))) { + /* Check if already in HMRFPO mode */ + if (cse_is_hfs1_com_secover_mei_msg()) + return ME_MODE_DISABLE_HMRFPO; + else + disable_me_hmrfpo(&var); + } + + return var; +} + +enum dgpu_state dasharo_dgpu_state(void) +{ + uint8_t dgpu_state = NVIDIA_OPTIMUS; + /* + * 0 - IGPU_ONLY + * 1 - NVIDIA_OPTIMUS (iGPU+dGPU) + * 2 - DGPU_ONLY + */ + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("DGPUState", &dgpu_state); + + return dgpu_state; +} + +#else +uint8_t cse_get_me_disable_mode(void) +{ + return 0; +} +#endif + +bool is_smm_bwp_permitted(void) +{ + bool smm_bwp = false; + bool fum = false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("FirmwareUpdateMode", &fum); + + /* Disable SMM BWP if in Firmware Update Mode */ + if (CONFIG(DASHARO_FIRMWARE_UPDATE_MODE) && fum) + return false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("SmmBwp", &smm_bwp); + else + return CONFIG(BOOTMEDIA_SMM_BWP); + + return smm_bwp; +} + +void get_watchdog_config(struct watchdog_config *wdt_cfg) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + uint32_t size; + + wdt_cfg->wdt_enable = CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE); + wdt_cfg->wdt_timeout = CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return; + + size = sizeof(*wdt_cfg); + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "WatchdogConfig", + wdt_cfg, &size); + + if (ret != CB_SUCCESS || size != sizeof(*wdt_cfg)) { + wdt_cfg->wdt_enable = CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE); + wdt_cfg->wdt_timeout = CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS; + } +} + +bool get_ps2_option(void) +{ + bool ps2_en = true; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("Ps2Controller", &ps2_en); + + return ps2_en; +} + +uint8_t get_sleep_type_option(void) +{ + uint8_t sleep_type = CONFIG(DASHARO_PREFER_S3_SLEEP) ? SLEEP_TYPE_OPTION_S3 + : SLEEP_TYPE_OPTION_S0IX; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("SleepType", &sleep_type); + + return sleep_type; +} + +uint8_t get_fan_curve_option(void) +{ + uint8_t fan_curve = FAN_CURVE_OPTION_SILENT; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("FanCurveOption", &fan_curve); + + return fan_curve; +} + +bool get_camera_option(void) +{ + bool cam_en = CAMERA_ENABLED_OPTION; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("EnableCamera", &cam_en); + + return cam_en; +} + +bool get_wireless_option(void) +{ + bool wireless_en = true; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("EnableWifiBt", &wireless_en); + + return wireless_en; +} + +void get_battery_config(struct battery_config *bat_cfg) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + uint32_t size; + + bat_cfg->start_threshold = BATTERY_START_THRESHOLD_DEFAULT; + bat_cfg->stop_threshold = BATTERY_STOP_THRESHOLD_DEFAULT; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return; + + size = sizeof(*bat_cfg); + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "BatteryConfig", + bat_cfg, &size); + + if (ret != CB_SUCCESS || size != sizeof(*bat_cfg)) { + bat_cfg->start_threshold = BATTERY_START_THRESHOLD_DEFAULT; + bat_cfg->stop_threshold = BATTERY_STOP_THRESHOLD_DEFAULT; + } +} + +#define MAX_SERIAL_LENGTH 0x100 + +bool get_serial_number_from_efivar(char *serial_number) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + uint32_t size; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return false; + + size = MAX_SERIAL_LENGTH; + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "Type2SN", serial_number, &size); + + if (ret != CB_SUCCESS || size > MAX_SERIAL_LENGTH) + return false; + + serial_number[size] = '\0'; + + return true; +} + + +bool get_uuid_from_efivar(uint8_t *uuid) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + uint32_t size; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return false; + + size = UUID_LEN; + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "Type1UUID", uuid, &size); + if (ret != CB_SUCCESS || size != UUID_LEN) + return false; + + return true; +} + +uint8_t dasharo_get_memory_profile(void) +{ + /* Using default SPD/JEDEC profile by default. */ + uint8_t profile = 0; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("MemoryProfile", &profile); + + return profile; +} + +bool dasharo_apu_pcie_pm_enabled(void) +{ + return get_apu_config().PciePwrMgmt; +} + +uint16_t dasharo_apu_watchdog_timeout(void) +{ + struct apu_config_t cfg = get_apu_config(); + return cfg.WatchdogEnable ? cfg.WatchdogTimeout : 0; +} + +bool dasharo_apu_cpu_boost_enabled(void) +{ + return get_apu_config().CorePerfBoost; +} + + +uint8_t get_active_core_count_option(void) +{ + uint8_t count = ALL_CORES_ACTIVE; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("CoreActiveCount", &count); + + return count; +} + +uint8_t get_active_small_core_count_option(void) +{ + uint8_t count = ALL_CORES_ACTIVE; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("SmallCoreActiveCount", &count); + + return count; +} + +bool get_hyper_threading_option(void) +{ + bool ht_en; + + ht_en = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("HyperThreading", &ht_en); + + return ht_en; +} + +uint8_t get_cpu_throttling_offset(uint8_t tcc_offset) +{ + uint8_t offset = tcc_offset; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("CpuThrottlingOffset", &offset); + + return offset; +} + +bool get_ibecc_option(bool ibecc_default) +{ + bool ibecc_en = ibecc_default; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("IBECC", &ibecc_en); + + return ibecc_en; +} + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 + +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A + +#define SI_DESC_REGION "SI_DESC" +/* From MTL it is larger, but we still just need the first 4K */ +#define SI_DESC_SIZE 0x1000 + +/* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */ +static bool is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_ERR, "Flash Descriptor is not valid\n"); + return 0; + } + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) + return 0; + + return 1; +} + +/* + * This function sets an EFI variable to signal to EDK2 whether the descriptor + * is locked, which affects the visibility and functionality of certain features + */ +static void set_descriptor_lockdown_option(void *unused) +{ + uint8_t si_desc_buf[SI_DESC_SIZE]; + struct region_device desc_rdev, smmstore_rdev; + uint8_t descriptor_writeable; + + if (!CONFIG(INTEL_DESCRIPTOR_MODE_CAPABLE) || !CONFIG(SMMSTORE)) + return; + + if (smmstore_lookup_region(&smmstore_rdev)) + return; + + if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + return; + } + + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return; + } + + descriptor_writeable = is_descriptor_writeable(si_desc_buf); + + printk(BIOS_DEBUG, "Descriptor is %swriteable\n", descriptor_writeable ? "" : "not "); + + efi_fv_set_option(&smmstore_rdev, + &dasharo_system_features_guid, + "DescriptorWriteable", + &descriptor_writeable, + sizeof(descriptor_writeable)); +} +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, set_descriptor_lockdown_option, NULL); diff --git a/src/vendorcode/dasharo/smbios.c b/src/vendorcode/dasharo/smbios.c new file mode 100644 index 00000000000..407a3cde8a5 --- /dev/null +++ b/src/vendorcode/dasharo/smbios.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const char *smbios_mainboard_bios_version(void) +{ + + if (CONFIG(PAYLOAD_SEABIOS)) { + if (strlen(CONFIG_LOCALVERSION) != 0) + return "Dasharo (coreboot+SeaBIOS) " CONFIG_LOCALVERSION; + else + return "Dasharo (coreboot+SeaBIOS)"; + } + + if (CONFIG(PAYLOAD_EDK2)) { + if (strlen(CONFIG_LOCALVERSION) != 0) + return "Dasharo (coreboot+UEFI) " CONFIG_LOCALVERSION; + else + return "Dasharo (coreboot+UEFI)"; + } + + if (strlen(CONFIG_LOCALVERSION) != 0) + return "Dasharo " CONFIG_LOCALVERSION; + + return "Dasharo"; +} diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 1fd81dce669..28b5e0e6353 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -12,7 +12,8 @@ config UDK_2017_BINDING select UDK_BASE config UDK_202005_BINDING - def_bool n + bool "UDK 202005 BINDING" + default n select UDK_BASE config UDK_202111_BINDING diff --git a/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FirmwareVersionInfo.h new file mode 100644 index 00000000000..4a9053c551f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FirmwareVersionInfo.h @@ -0,0 +1,61 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + @par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" +#define INTEL_FVI_SMBIOS_TYPE 0xDD + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FspProducerDataHeader.h new file mode 100644 index 00000000000..f7861710aff --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FspProducerDataHeader.h @@ -0,0 +1,79 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include + +#define BUILD_TIME_STAMP_SIZE 12 +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/MemInfoHob.h new file mode 100644 index 00000000000..ff57176221b --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/MemInfoHob.h @@ -0,0 +1,326 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryS3Data2Guid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DDR5_CH 2 +#define MAX_DIMM 2 +// Must match definitions in +// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 4 +#endif + +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#ifndef MAX_RCOMP_TARGETS +#define MAX_RCOMP_TARGETS 5 +#endif + +#ifndef MAX_ODT_ENTRIES +#define MAX_ODT_ENTRIES 11 +#endif + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT32 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. + UINT8 Resv[2]; ///< Resv +} MRC_CH_TIMING; + +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. + UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; + UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS]; + UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES]; + CONTROLLER_INFO Controller[MAX_NODE]; + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + BOOLEAN IsIbeccEnabled; + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows + UINT16 PprRepairFails; ///< PPR: Counts of repair failure + UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h deleted file mode 100644 index 42b5cc20d52..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h +++ /dev/null @@ -1,94 +0,0 @@ -/** @file - -Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _CXL_NODE_HOB_ -#define _CXL_NODE_HOB_ - -#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } } - -#ifndef MAX_CXL_HDM_RANGES -#define MAX_CXL_HDM_RANGES 0x2 // Maximum number of CXL HDM ranges per CXL end device. -#endif - -#ifndef MAX_CXL_PER_SOCKET -#define MAX_CXL_PER_SOCKET 8 -#endif - -#define CXL_NODE_ATTR_MEM BIT0 -#define CXL_NODE_ATTR_PERSISTENT BIT1 -#define CXL_NODE_ATTR_MEM_HW_INIT BIT2 -#define CXL_NODE_ATTR_ACCELERATOR BIT3 - -typedef UINT32 CXL_NODE_ATTR; - -#pragma pack(1) - -// -// CDAT DSEMTS EFI Memory Type and Attribute -// -typedef enum { - CxlEfiConventionalMemory = 0x0, - CxlEfiConventionalMemorySp = 0x1, - CxlEfiReservedMemoryType = 0x2, - MaxCxlEfiMemType -} CXL_EFI_MEM_TYPE; - -typedef struct { - UINT32 RdLatency; - UINT32 WrLatency; - UINT32 RdBandwidth; - UINT32 WrBandwidth; -} CXL_PERF_DATA; - -typedef struct { - UINT64 SerialNumber; - UINT16 VendorId; - CXL_NODE_ATTR Attr; - UINT32 Address; - UINT32 Size; - UINT8 Ways; - UINT8 SocketBitmap; - CXL_EFI_MEM_TYPE EfiMemType; - CXL_PERF_DATA InitiatorPerfData; // Performance data between device egress and initiator. - CXL_PERF_DATA TargetPerfData; // Performance data of entire target memory region. - CXL_PERF_DATA InitiatorTargetPerfData; // performance data between initiator and the device memory. -} CXL_NODE_INFO; - -typedef struct { - UINT8 CxlNodeCount; - // - // CXL node info for UEFI memory map and ACPI tables construction - // - CXL_NODE_INFO CxlNodeInfo[MAX_CXL_PER_SOCKET * MAX_CXL_HDM_RANGES]; -} CXL_NODE_SOCKET; - -#pragma pack() - -#endif //#ifndef _CXL_NODE_HOB_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h deleted file mode 100644 index f99c3bc36b0..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h +++ /dev/null @@ -1,17 +0,0 @@ -/** @file - Intel FSP definition from Intel Firmware Support Package External - Architecture Specification v2.2. - @copyright - Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#ifndef _FSP_EAS_H_ -#define _FSP_EAS_H_ - -#include -#include -#include -#include - -#endif // _FSP_EAS_H_ \ No newline at end of file diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h deleted file mode 100644 index ecc2d6fdf7d..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h +++ /dev/null @@ -1,84 +0,0 @@ -/** @file - -Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _FSP_ERROR_INFO_HOB_H_ -#define _FSP_ERROR_INFO_HOB_H_ - -#include -#include -#include -#include - -#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }} - -#pragma pack(1) - -typedef struct { - /// - /// GUID HOB header. - /// - EFI_HOB_GUID_TYPE GuidHob; - - /// - /// ReportStatusCode () type identifier. - /// - EFI_STATUS_CODE_TYPE Type; - - /// - /// ReportStatusCode () value. - /// - EFI_STATUS_CODE_VALUE Value; - - /// - /// ReportStatusCode () Instance number. - /// - UINT32 Instance; - - /// - /// Optional GUID which may be used to identify - /// which internal component of the FSP was - /// executing at the time of the error. - /// - EFI_GUID CallerId; - - /// - /// GUID identifying the nature of the fatal error. - /// - EFI_GUID ErrorType; - - /// - /// EFI_STATUS code describing the error encountered. - /// - UINT32 Status; -} FSP_ERROR_INFO_HOB; - -#pragma pack() - -#endif //#ifndef _FSP_ERROR_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h deleted file mode 100644 index ce86ce8a9a5..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2022, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F445055525053 /* 'SPRUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F445055525053 /* 'SPRUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F445055525053 /* 'SPRUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h deleted file mode 100644 index bfd8d7dce48..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h +++ /dev/null @@ -1,1308 +0,0 @@ -/** @file - -Copyright (c) 2022, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include -#include - -#pragma pack(1) - - -/** FSP-M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Customer Revision - The Customer can set this revision string for their own purpose. -**/ - UINT8 CustomerRevision[32]; - -/** Offset 0x0060 - Bus Ratio - Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO -**/ - UINT8 BusRatio[8]; - -/** Offset 0x0068 - D2K Credit Config - Set the D2K Credit Config - 1: Min, 2: Med(Default), 3: Max. - 1:Min, 2:Med, 3:Max -**/ - UINT8 D2KCreditConfig; - -/** Offset 0x0069 - Snoop Throttle Config - Set the Snoop Throttle Config - 0: DIS(Default), 1: Min, 2: Med, 3: Max. - 0:DIS, 1:Min, 2:Med, 3:Max -**/ - UINT8 SnoopThrottleConfig; - -/** Offset 0x006A - Legacy VGA Soc - Socket that claims the legacy VGA range -**/ - UINT8 LegacyVgaSoc; - -/** Offset 0x006B - Legacy VGA Stack - Stack that claims the legacy VGA range -**/ - UINT8 LegacyVgaStack; - -/** Offset 0x006C - Pcie P2P Performance Mode - Determine if to enable PCIe P2P Performance Mode - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 P2pRelaxedOrdering; - -/** Offset 0x006D - UPI Debug Print Level - UPI Debug Print Level Bitmask - 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8: - Detail, 0x0F: All(Default). - 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All -**/ - UINT8 DebugPrintLevel; - -/** Offset 0x006E - NumaEn - NumaEn - 1: Enable Numa(Default), 0: Disable Numa. - 0:Disable, 1:Enable -**/ - UINT8 NumaEn; - -/** Offset 0x006F - SNC - Enable or Disable SNC - 0: Disable, 2: Snc2, 4: Snc4, 0x0F: Auto(Default). - 0: Disable, 2: Snc2, 4: Snc4, 0x0F: Auto -**/ - UINT8 SncEn; - -/** Offset 0x0070 - UMA Clustering - Set UMA Clusters - 0: Disable, 2: Two Clusters, 4: Four Clusters(Default). - 0:Disable, 2:Two Clusters, 4:Four Clusters -**/ - UINT8 UmaClustering; - -/** Offset 0x0071 - IODC Mode - IODC Mode - 0: Disable, 1: Auto(Default), 2: Push, 3: AllocFlow, 4: NonAlloc, - 5: WCILF. - 0:Disable, 1:Auto, 2:Push, 3:AllocFlow, 4:NonAlloc, 5:WCILF -**/ - UINT8 IoDcMode; - -/** Offset 0x0072 - Degrade Precedence - Setup Degrade Precedence - 0: Topology(Default), 1: Feature. - 0:Topology, 1:Feature -**/ - UINT8 DegradePrecedence; - -/** Offset 0x0073 - Degrade 4 Socket Preference - Setup Degrade 4 Socket Preference - 0: Fully Connect(Default), 1: Dual Link Ring. - 0:Fully Connect, 1:Dual Link Ring -**/ - UINT8 Degrade4SPreference; - -/** Offset 0x0074 - Directory Mode - Enable or Disable Directory Mode - 0: Disable, 1: Enable, 2: Auto(Default). - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 DirectoryModeEn; - -/** Offset 0x0075 - XPT Prefetch Enable - Enable or Disable XPT Prefetch - 0: Disable, 1: Enable, 2: Auto(Default). - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 XptPrefetchEn; - -/** Offset 0x0076 - KTI Prefetch Enable - Enable or Disable KTI Prefetch - 0: Disable, 1: Enable, 2: Auto(Default). - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 KtiPrefetchEn; - -/** Offset 0x0077 - XPT Remote Prefetch Enable - Enable or Disable XPT Remote Prefetch Enable - 0: Disable, 1: Enable, 2: Auto(Default). - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 XptRemotePrefetchEn; - -/** Offset 0x0078 - KTI FPGA - Enable or Disable KTI FPGA -**/ - UINT8 KtiFpgaEnable[8]; - -/** Offset 0x0080 - DDRT QoS Mode - DDRT QoS - 0: Mode 0(Default), 1: Mode 1, 2: Mode 2. - 0:Mode 0, 1:Mode 1, 2:Mode 2 -**/ - UINT8 DdrtQosMode; - -/** Offset 0x0081 - KTI Link Speed Mode - Choose KTI Link Speed Mode - 0: Slow, 1: Full(Default). - 0:Slow, 1:Full -**/ - UINT8 KtiLinkSpeedMode; - -/** Offset 0x0082 - KTI Link Speed - Setup KTI Link Speed - 0: 128GT, 1: 144GT, 2: 160GT, 3: 200GT, 0x7F: Max KTI - Link Speed (Default), 0x8F: Frequency Per Link. - 0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link -**/ - UINT8 KtiLinkSpeed; - -/** Offset 0x0083 - KTI Link L0p - Enable or Disable KTI Link L0p - 0: Disable, 1: Enable, 2: Auto(Default). - 0:Disable, 1:Enable, 2: Auto -**/ - UINT8 KtiLinkL0pEn; - -/** Offset 0x0084 - KTI Link L1 - Enable or Disable KTI Link L1 - 0: Disable, 1: Enable, 2: Auto(Default). - 0:Disable, 1:Enable, 2: Auto -**/ - UINT8 KtiLinkL1En; - -/** Offset 0x0085 - Kti Link Speed Per Port - Setup KTI Link Speed to be allocated for each port - 0: 128GT, 1: 144GT, 2: 160GT, - 3: 200GT, 0x7f: Max KTI Link Speed(Default). - 0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7f:Max KTI Link Speed -**/ - UINT8 KtiLinkSpeedPerPort[48]; - -/** Offset 0x00B5 - DfxL0p Enable - Indicates the DfxL0p Enable to be allocated for each port - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 DfxL0pEnable[48]; - -/** Offset 0x00E5 - DfxL1 Enable - Indicates the DfxL1 Enable to be allocated for each port - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 DfxL1Enable[48]; - -/** Offset 0x0115 - KTI Failover - Enable or Disable KTI Failover - 0: Disable, 1: Enable, 2: Auto(Default). - 0:Disable, 1:Enable, 2: Auto -**/ - UINT8 KtiFailoverEn; - -/** Offset 0x0116 - KTI LB Enable - Enable or Disable KTI LB - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 KtiLbEn; - -/** Offset 0x0117 - KTI CRC Mode - Select KTI CRC Mode - 0: 16bit(Default), 1: 32bit, 2: Auto. - 0:16bit, 1:32bit, 2:Auto -**/ - UINT8 KtiCrcMode; - -/** Offset 0x0118 - KTI CPU Socket Hotplug - Enable or Disable KTI CPU Socket Hotplug - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 KtiCpuSktHotPlugEn; - -/** Offset 0x0119 - KTI CPU Socket HotPlug Topology - Select KTI CPU Socket HotPlug Topology - 0: 4Socket(Default), 1: 8Socket. - 0:4Socket, 1:8Socket -**/ - UINT8 KtiCpuSktHotPlugTopology; - -/** Offset 0x011A - KTI SKU Mismatch Check - Enable or Disable KTI SKU Mismatch Check - 0: Disable, 1 :Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 KtiSkuMismatchCheck; - -/** Offset 0x011B - TOR Threshold - Loctorem threshold Normal - Select TOR Threshold - Loctorem threshold Normal - 0: Disable, 1: Auto(Default), - 2: Low, 3: Medium, 4: High. - 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High -**/ - UINT8 TorThresLoctoremNorm; - -/** Offset 0x011C - TOR threshold - Loctorem threshold empty - Select TOR threshold - Loctorem threshold empty - 0: Disable, 1: Auto(Default), - 2: Low, 3: Medium, 4:High. - 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High -**/ - UINT8 TorThresLoctoremEmpty; - -/** Offset 0x011D - TSC Sync in Sockets - Enable or Disable TSC Sync in Sockets - 0: Disable, 1: Enable(Default), 2: Auto. - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 TscSyncEn; - -/** Offset 0x011E - HA A to S directory optimization - Enable or Disable HA A to S directory optimization - 0: Disable, 1: Enable, 2: - Auto(Default). - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 StaleAtoSOptEn; - -/** Offset 0x011F - LLC Deadline Allocation - Enable or Disable LLC Deadline Allocation - 0: Disable, 1: Enable(Default), 2: Auto. - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 LLCDeadLineAlloc; - -/** Offset 0x0120 - MBA BW Calibration Profiles - Choice of MBA BW throttling curve - 0: Linear BW shaping, 1: Biased BW shaping, - 2: Legacy BW shaping, 3: Auto(Default). - 0:Linear BW shaping, 1:Biased BW shaping, 2:Legacy BW shaping, 3:Auto -**/ - UINT8 MbeBWCalChoice; - -/** Offset 0x0121 - Split Lock - Enable or Disable Split Lock - 0: Disable(Default), 1: Enable, 2: Auto. - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 SplitLock; - -/** Offset 0x0122 - Affinitize M2Iosf to Upi for 2-Socket - Affinitize M2IOSF traffic to proper UPI links to improve 2-Socket P2P perf - 0: - Disable, 1: Enable, 2: Auto(Default). - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 M2iosfToUpiAffinity; - -/** Offset 0x0123 - MMCFG Base Address - Setup MMCFG Base Address - 0: 1G, 1: 1.5G, 2: 1.75G, 3: 2G, 4: 2.25G, 5: 3G, 6: - Auto(Default). - 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto -**/ - UINT8 mmCfgBase; - -/** Offset 0x0124 - MMCFG Size - Select MMCFG Size - 0: 64M, 1: 128M, 2: 256M, 3: 512M, 4: 1G, 5: 2G, 6: Auto(Default). - 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6:Auto -**/ - UINT8 mmCfgSize; - -/** Offset 0x0125 -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x0128 - MMIO High Base Address - MMIO High Base Address, a hex number for Bit[51:32] -**/ - UINT32 mmiohBase; - -/** Offset 0x012C - CPU Physical Address Limit - CPU Physical Address Limit - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 CpuPaLimit; - -/** Offset 0x012D -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x012E - MMIO High Size - MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space - per CPU. Range 1-1024 -**/ - UINT16 mmiohSize; - -/** Offset 0x0130 - isocEn - Enable or Disable isocEn - 0: Disable(Default), 1: Enable, 2: Auto. - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 isocEn; - -/** Offset 0x0131 - DCA - Enable or Disable DCA - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 dcaEn; - -/** Offset 0x0132 -**/ - UINT8 UnusedUpdSpace2[2]; - -/** Offset 0x0134 - BoardTypeBitmask - BoardTypeBitmask -**/ - UINT32 BoardTypeBitmask; - -/** Offset 0x0138 - AllLanesPtr - Pointer to array of ALL_LANES_EPARAM_LINK_INFO -**/ - UINT32 AllLanesPtr; - -/** Offset 0x013C - PerLanePtr - Pointer to array of PER_LANE_EPARAM_LINK_INFO -**/ - UINT32 PerLanePtr; - -/** Offset 0x0140 - AllLanesSizeOfTable - Number of elements in AllLanesPtr array. -**/ - UINT32 AllLanesSizeOfTable; - -/** Offset 0x0144 - PerLaneSizeOfTable - Number of elements in PerLanePtr array. -**/ - UINT32 PerLaneSizeOfTable; - -/** Offset 0x0148 - WaitTimeForPSBP - Enable or Disable WaitTimeForPSBP -**/ - UINT32 WaitTimeForPSBP; - -/** Offset 0x014C - WaSerializationEn - Enable or Disable WaSerializationEn - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 WaSerializationEn; - -/** Offset 0x014D - KtiInEnableMktme - Enable or Disable KtiInEnableMktme - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 KtiInEnableMktme; - -/** Offset 0x014E - HIOP STACK DISABLE - Enables/Disables given HIOP STACK. Default is AUTO no stack is disabled. 1 - The - stacks indicated by the bit locations are disabled. 0 - The stacks indicated by - the bit locations are not modified. The stack order is abstracted each bit 0 = - stack 0 ... bit n = stack n. The bit setting for each stack can be overriden by - BIOS based on part-knob compatibility. The array size must be MAX_SOCKET x UINT32. -**/ - UINT8 StackDisableBitMap[32]; - -/** Offset 0x016E - CFRS3mProvision - Enable or Disable Provision S3M CFR - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 CFRS3mProvision; - -/** Offset 0x016F - CFRS3mManualCommit - Enable or Disable Manual Commit S3M FW CFR - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 CFRS3mManualCommit; - -/** Offset 0x0170 - CFRPucodeProvision - Enable or Disable Provision PUcode CFR - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 CFRPucodeProvision; - -/** Offset 0x0171 - CFRPucodeManualCommit - Enable or Disable Manual Commit PUcode CFR - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 CFRPucodeManualCommit; - -/** Offset 0x0172 -**/ - UINT8 UnusedUpdSpace3[2]; - -/** Offset 0x0174 - CFRImagePtr - Pointer to array of CFR Image -**/ - UINT32 CFRImagePtr; - -/** Offset 0x0178 - Processor VmxEnable Function - Enable(Default) or Disable Processor VmxEnable Function - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 VmxEnable; - -/** Offset 0x0179 - Processor X2apic Function - Enable(Default) or Disable Processor X2apic Function - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 X2apic; - -/** Offset 0x017A - Processor HyperThreading Function - Enable(Default) or Disable Processor HyperThreading Function - 1: Disable, 0: - Enable(Default). - 1:Disable, 0:Enable -**/ - UINT8 ProcessorHyperThreadingDisable; - -/** Offset 0x017B - Processor Dynamic Intel Speed Select (ISS) Function - Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function - - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 ProcessorDynamicIssEnable; - -/** Offset 0x017C - Enables Intel(R) TXT - Enable or Disable(Default) Enables Intel(R) TXT - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 ProcessorLtsxEnable; - -/** Offset 0x017D - DDR frequency limit - Select DDR frequency limit, 0x00: Auto(Default), 0x13:DDR_3200, 0x16:DDR_3600, - 0x19:DDR_4000, 0x1C:DDR_4400, 0x1D:DDR_4800, 0x1E:DDR_5200, 0x1F:DDR_5600 -**/ - UINT8 DdrFreqLimit; - -/** Offset 0x017E - Memory Serial Debug Message Level - Select Memory Serial Debug Message Level - 0: Disable, 1: Minimum, 2: Normal, 3: - Maximum(Default), 4: Auto. - 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto -**/ - UINT8 serialDebugMsgLvl; - -/** Offset 0x017F - IIO ConfigIOU0 - ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) -**/ - UINT8 IioConfigIOU0[8]; - -/** Offset 0x0187 - IIO ConfigIOU1 - ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) -**/ - UINT8 IioConfigIOU1[8]; - -/** Offset 0x018F - IIO ConfigIOU2 - ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) -**/ - UINT8 IioConfigIOU2[8]; - -/** Offset 0x0197 - IIO ConfigIOU3 - ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) -**/ - UINT8 IioConfigIOU3[8]; - -/** Offset 0x019F - IIO ConfigIOU4 - ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) -**/ - UINT8 IioConfigIOU4[8]; - -/** Offset 0x01A7 - IIO ConfigIOU5 - ConfigIOU[MAX_SOCKET][5]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) -**/ - UINT8 IioConfigIOU5[8]; - -/** Offset 0x01AF - IIO ConfigIOU6 - ConfigIOU[MAX_SOCKET][6]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) -**/ - UINT8 IioConfigIOU6[8]; - -/** Offset 0x01B7 -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x01B8 - IIO PCIE Config Table Ptr - Pointer to array of UPD_IIO_PCIE_PORT_CONFIG -**/ - UINT32 IioPcieConfigTablePtr; - -/** Offset 0x01BC - IIO PCIE Config Table Number - Number of elements in IioPcieConfigTablePtr array, socket number as unit. -**/ - UINT32 IioPcieConfigTableNumber; - -/** Offset 0x01C0 - IIO DeEmphasis Array Ptr - Pointer to array of DeEmphasis -**/ - UINT32 DeEmphasisPtr; - -/** Offset 0x01C4 - IIO DeEmphasis Array Number - Number of elements in DeEmphasis array. -**/ - UINT32 DeEmphasisNumber; - -/** Offset 0x01C8 - IIO PCIe Common Clock Array Ptr - Pointer to array of PCIe Common Clock -**/ - UINT32 PcieCommonClockPtr; - -/** Offset 0x01CC - IIO PCIe Common Clock Array Number - Number of elements in PCIe Common Clock array. -**/ - UINT32 PcieCommonClockNumber; - -/** Offset 0x01D0 - VT-d Support - Enable or Disable VT-d Support - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 VtdSupport; - -/** Offset 0x01D1 - PCIe ACSCTL - Enable/Disable overwrite of PCI Access Control Services Control register in PCI - root ports - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 VtdPciAcsCtlWaEn; - -/** Offset 0x01D2 -**/ - UINT8 UnusedUpdSpace5[2]; - -/** Offset 0x01D4 - IIO PCIe Port Hide Array Ptr - Pointer to array of Hide or visible for IIO Pcie Port. -**/ - UINT32 PEXPHIDEPtr; - -/** Offset 0x01D8 - IIO PCIe Port Hide Array Number - Number of elements in IIO PCIe Port Hide Array. -**/ - UINT32 PEXPHIDENumber; - -/** Offset 0x01DC - PcieHotPlugEnable - Enable or disable Pcie hot plug enable feature - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 PcieHotPlugEnable; - -/** Offset 0x01DD -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x01DE - DelayAfterPCIeLinkTraining - Custom delay after PCI-E link training on IIO ports -**/ - UINT16 DelayAfterPCIeLinkTraining; - -/** Offset 0x01E0 - IIO PCI bus resource Ptr - Pointer to array of socket PCI bus resource. -**/ - UINT32 PciBusResConfigPtr; - -/** Offset 0x01E4 - IIO PCI IO/MMIO base and limits resource Ptr - Pointer to array of socket PCI IO/MMIO resource. -**/ - UINT32 PciBaseLimitsResConfigPtr; - -/** Offset 0x01E8 - PCH PCIE PLL Ssc - Pointer to array of socket PCI IO/MMIO resource. -**/ - UINT8 PchPciePllSsc; - -/** Offset 0x01E9 - MeUmaEnable - Enable or disable ME UMA feature - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 MeUmaEnable; - -/** Offset 0x01EA - SerialIoUartDebugEnable - Enable or Disable SerialIo Uart debug library in FSP - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 SerialIoUartDebugEnable; - -/** Offset 0x01EB -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x01EC - ISA Serial Base selection - Select ISA Serial Base address could be initialized by boot loader - 0x2F8: 0x2F8, - 0x3F8: 0x3F8(Default). - 0x2F8:0x2F8, 0x3F8:0x3F8 -**/ - UINT16 SerialIoUartDebugIoBase; - -/** Offset 0x01EE - MemRefreshWaterMark - Enable or Disable MemRefreshWaterMark in FSP - 0: Auto(Default), 1: Enable, - 2: Disable. - 0:Auto, 1:Enable, 2:Disable -**/ - UINT8 PanicWm; - -/** Offset 0x01EF - promoteMrcWarnings - Enable or Disable MRC promote warning in FSP - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 promoteMrcWarnings; - -/** Offset 0x01F0 - promoteWarnings - Enable(Default) or Disable Promote warning in FSP - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 promoteWarnings; - -/** Offset 0x01F1 - serialDebugMsgLvlTrainResults - Enable or Disable Promote warning in FSP - 0:Disable(Default), 8:Enable. - 0:Disable, 8:Enable -**/ - UINT8 serialDebugMsgLvlTrainResults; - -/** Offset 0x01F2 - MemTest - Enable(Default) or Disable memory test during normal boot in FSP - 0: Disable, - 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 HwMemTest; - -/** Offset 0x01F3 -**/ - UINT8 UnusedUpdSpace8; - -/** Offset 0x01F4 - MemTest Loops - Number of memory test loops during normal boot, set to 0 to run memtest infinitely - in FSP - 1 (Default). - minimum = 0, maximum = 65535 -**/ - UINT16 MemTestLoops; - -/** Offset 0x01F6 -**/ - UINT8 UnusedUpdSpace9[2]; - -/** Offset 0x01F8 - Adv MemTest Options - This option is a bit mask[19:0]: All 0 = disabled: bit-0=XMATS8, bit-1=XMATS16, - bit-2=Reserved, bit-3=Reserved, bit-4=WCMATS8, bit-5=WCMCH8, bit-6=Reserved, bit-7=MARCHCM64, - bit-8=Reserved, bit-9=Reserved, bit-10=Reserved, bit-11=TWR, bit-12=DATARET, bit-13=MATS8TC1, - bit-14=MATS8TC2, bit-15=MATS8TC3, bit-16=SK-HYNIX, bit-17=SAMSUNG, bit-18=MICRON-RMW, - bit-19=SCRAM_X2 in FSP. -**/ - UINT32 AdvMemTestOptions; - -/** Offset 0x01FC - SmartTestKey - Number of SmartTest Key -**/ - UINT32 SmartTestKey; - -/** Offset 0x0200 - Adv MemTest Pause - Specify a pause delay between 0 to 256000 in units of usec. This is a time period - where refresh is disabled between write and read sequences in FSP. -**/ - UINT32 AdvMemTestCondPause; - -/** Offset 0x0204 - Adv MemTest tREFI - Specify tREFI (refresh rate) timing between 1850 to 7800 in nsec. -**/ - UINT16 AdvMemTestCondTrefi; - -/** Offset 0x0206 - Adv MemTest tWR - Specify tWR timing between 48 to 96 in units of tCK in FSP. -**/ - UINT8 AdvMemTestCondTwr; - -/** Offset 0x0207 -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x0208 - Adv MemTest PMIC VDD Level - Specify PMIC VDD level in units of mV in FSP. -**/ - UINT16 AdvMemTestCondPmicVdd; - -/** Offset 0x020A - Adv MemTest Conditions - Auto = set test conditions based on test type; Manual = specify global test conditions; - Disable = Do not apply test conditions in FSP - 0: Disable, 1: Auto(Default), - 2: Manual. - 0:Disable, 1:Auto, 2:Manual -**/ - UINT8 AdvMemTestCondition; - -/** Offset 0x020B - Adv MemTest Reset Failure Tracking List - Enable/disable Reset of the Row Failure Tracking List after each Adv MemTest option. - Useful for testing performance of multiple options in FSP - 0: Disable(Default), - 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 AdvMemTestResetList; - -/** Offset 0x020C - MemTest On Cold Fast Boot - Enable - Enables memory test during cold fast boot. Disable - Disables this feature. - Auto - Sets it to the MRC default setting; current default is Disable in FSP - - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnColdFastBoot; - -/** Offset 0x020D - Attempt Fast Boot - Enable - Portions of memory reference code will be skipped when possible to increase - boot speed on warm boots. Disable - Disables this feature. Auto - Sets it to the - MRC default setting - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 AttemptFastBoot; - -/** Offset 0x020E - MemTest On Cold Fast Boot - Enable - Enables memory test during cold fast boot. Disable - Disables this feature. - Auto - Sets it to the MRC default setting - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 AttemptFastBootCold; - -/** Offset 0x020F - Multithreaded Memory Training - Selects the number of processor sockets to train in parallel. - 0: All sockets - operate in parallel(Default). 1: At any time only one socket is executing. - 2: At any time only two socket are executing. 4: At any time only four socket are - executing in FSP. - 0:All Processor Sockets, 1:One Socket at a Time (No Multithreading), 2:Two Sockets - at a Time, 4:Four Sockets at a Time -**/ - UINT8 AllowedSocketsInParallel; - -/** Offset 0x0210 - Auto-Reset on mem Training Error - Enable/Disable Auto-Reset on mem Training Error in FSP - 0:Disable(Default), - 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 AutoResetOnMemErr; - -/** Offset 0x0211 - Rank Margin Tool - Enable/Disable the Rank Margin Tool in FSP - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 EnableRMT; - -/** Offset 0x0212 - RMT on Fast Cold Boot - Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP - 0:Disable(Default), - 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 EnableRMTonFCB; - -/** Offset 0x0213 - Execute Jedecinit before RMT - Execute Jedecinit before Rank Margin Tool in FSP - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 JedecInitBeforeRMT; - -/** Offset 0x0214 - Backside Margining - Enable/Disable margin test on the register or buffer backside in FSP - 0:Disable(Default), - 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 RMTBacksideMargining; - -/** Offset 0x0215 - CmdAll - Step size of CmdAll. Auto: 1. Supported values: 1,2,4,8 in FSP - 1:Auto(Default), - 2:2, 4:4, 8:8. - 1:Auto, 2:2, 4:4, 8:8 -**/ - UINT8 RMTCmdAll; - -/** Offset 0x0216 - RMT Debug Messages - Enable/Disable the RMT debug messages in FSP - 2:Disable(Default), 5:Enable. - 2:Disable, 5:Enable -**/ - UINT8 RMTDebugMessages; - -/** Offset 0x0217 - RMT Display Tables - Enable/Disable displaying results as tables in FSP - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 RMTDisplayTables; - -/** Offset 0x0218 - RMT Loop Count - Exponential loop count for single rank test in FSP. -**/ - UINT8 RMTLoopCount; - -/** Offset 0x0219 -**/ - UINT8 UnusedUpdSpace11[3]; - -/** Offset 0x021C - Test Signal Bit Mask For RMT - Test signal bit mask for RMT in FSP. -**/ - UINT32 TestSignalBitMaskRMT; - -/** Offset 0x0220 - RMT Per Bit Margining - Enable/Disable Per Bit Margining in FSP - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 RMTPerBitMargining; - -/** Offset 0x0221 - RMT Per CA Lane Margining - Enable/Disable Per CA Lane Margining in FSP - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 RMTPerCaLaneMargining; - -/** Offset 0x0222 - RMT Display Plots - Enable/Disable the display of per-bit results as plots in FSP - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 RMTPerDisplayPlots; - -/** Offset 0x0223 - RMT RxDqs - Step size of RxDqs. Auto: 1. Supported values: 1,2,4,8 in FSP - 1:Auto,(Default) - 2:2, 4:4, 8:8. - 1:Auto, 2:2, 4:4, 8:8 -**/ - UINT8 RMTRxDqs; - -/** Offset 0x0224 - RMT RxVref - Step size of RxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - 1:Auto,(Default) - 2:2, 4:4, 8:8. - 1:Auto, 2:2, 4:4, 8:8 -**/ - UINT8 RMTRxVref; - -/** Offset 0x0225 - RMT Scrambler - Enable or Disable scrambler during RMT test in FSP - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 RMTScrambler; - -/** Offset 0x0226 - RMT Step Size Override - Enable or Disable overriding the default step sizes in FSP - 0:Disable(Default), - 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 RMTStepSizeOverride; - -/** Offset 0x0227 - RMT TxDq - Step size of TxDq. Auto: 1. Supported values: 1,2,4,8 in FSP - 1:Auto(Default), - 2:2, 4:4, 8:8. - 1:Auto, 2:2, 4:4, 8:8 -**/ - UINT8 RMTTxDq; - -/** Offset 0x0228 - RMT TxVref - Step size of TxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - 1:Auto(Default), - 2:2, 4:4, 8:8. - 1:Auto, 2:2, 4:4, 8:8 -**/ - UINT8 RMTTxVref; - -/** Offset 0x0229 - DDR5 ECS - Enable/Disable DDR5 Error Check and Scrub (ECS) in FSP - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 ErrorCheckScrub; - -/** Offset 0x022A - Enforce Memory POR - 0:Enforce POR - Enforces Plan Of Record restrictions for DDR5 frequency and voltage - programming. 2:Disable - Disables this feature and user is able to run at higher - frequencies, specified in the DDR Frequency Limit field (limited by processor support)(Default). - 0:Enforce POR, 2:Disabled -**/ - UINT8 EnforceDdrMemoryFreqPor; - -/** Offset 0x022B - Enforce Population POR - Enable Memory Population POR Enforcement. Selecting Enforce Validated Populations - will only allow populations that have been validated in FSP - 0:Disable(Default), - 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 EnforcePopulationPor; - -/** Offset 0x022C - DDR PPR Type - Selects DDR Post Package Repair Type - 2: Hard PPR, 1: Soft PPR (Default), - 0: Disabled. - 0:Disabled, 2:Hard PPR, 1:Soft PPR -**/ - UINT8 pprType; - -/** Offset 0x022D - Force PPR On All Dram for UCE - Force PPR on all dram for UCE in FSP - 0:Disable(Default), 1:Enable. - 0:Disabled, 1:Enabled -**/ - UINT8 ForcePprOnAllDramUce; - -/** Offset 0x022E -**/ - UINT8 UnusedUpdSpace12[2]; - -/** Offset 0x0230 - pprAddrVariablePtr - Pointer to array of PPR_ADDR_VARIABLE -**/ - UINT32 PprAddrVariablePtr; - -/** Offset 0x0234 - Allow Memory Test Correctable Error - Enable - Logs error and allows correctable errors during memory test(DIMM Rank not - removed). Disable - Logs error and removes DIMM Rank. Auto - Sets it to the MRC - default setting; current default is Enable in FSP - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 allowCorrectableMemTestError; - -/** Offset 0x0235 - Memory I/O Health Check - Memory I/O Health Check - 0: Auto, 1: Manual, 2: Disable (Default). Select - option Auto for default values. Manual for new values. Disable for disabling feature - in FSP - 0:Auto, 1:Manual, 2:Disable(Default). - 0:Auto, 1:Manual, 2:Disable -**/ - UINT8 MemIOHealthCheck; - -/** Offset 0x0236 - RxDqsDelay Left Edge - Offset for RxDqsDelay Left Edge in FSP. -**/ - UINT8 CriticalRxDqsDelayLeftEdge; - -/** Offset 0x0237 - RxDqsDelay Right Edge - Offset for RxDqsDelay Right in FSP. -**/ - UINT8 CriticalRxDqsDelayRightEdge; - -/** Offset 0x0238 - RxVref Left Edge - Offset for RxVref Left Edge in FSP. -**/ - UINT8 CriticalRxVrefLeftEdge; - -/** Offset 0x0239 - RxVref Right Edge - Offset for RxVref Right Edge in FSP. -**/ - UINT8 CriticalRxVrefRightEdge; - -/** Offset 0x023A - TxDqDelay Left Edge - Offset for TxDqDelay Left Edge in FSP. -**/ - UINT8 CriticalTxDqDelayLeftEdge; - -/** Offset 0x023B - TxDqDelay Right Edge - Offset for TxDqDelay Right Edge in FSP. -**/ - UINT8 CriticalTxDqDelayRightEdge; - -/** Offset 0x023C - TxVref Left Edge - Offset for TxDqDelay Left Edge in FSP. -**/ - UINT8 CriticalTxVrefLeftEdge; - -/** Offset 0x023D - TxVref Right Edge - Offset for TxDqDelay Right Edge in FSP. -**/ - UINT8 CriticalTxVrefRightEdge; - -/** Offset 0x023E - Reboot On Critical Failure - Reboot System on Critical failure to do Memory Training in FSP - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 ResetOnCriticalError; - -/** Offset 0x023F - Number of Times to Reboot and Retrain - Number of times to Reboot System on Critical failure to do Memory Training in FSP. -**/ - UINT8 CriticalRetries; - -/** Offset 0x0240 - Memory I/O Health Check Loop Count - CPGC Test Loop Count for Memory IO Health Test -**/ - UINT8 MemIOHealthLoopCount; - -/** Offset 0x0241 - Telemetry RxDqsDelay Left Edge - Offset for Telemetry RxDqsDelay Left Edge in FSP. -**/ - UINT8 TelemetryRxDqsDelayLeftEdge; - -/** Offset 0x0242 - Telemetry RxDqsDelay Right Edge - Offset for Telemetry RxDqsDelay Right Edge in FSP. -**/ - UINT8 TelemetryRxDqsDelayRightEdge; - -/** Offset 0x0243 - Telemetry RxVref Left Edge - Offset for Telemetry RxDqsDelay Left Edge in FSP. -**/ - UINT8 TelemetryRxVrefLeftEdge; - -/** Offset 0x0244 - Telemetry RxVref Right Edge - Offset for Telemetry RxDqsDelay Right Edge in FSP. -**/ - UINT8 TelemetryRxVrefRightEdge; - -/** Offset 0x0245 - Telemetry TxDqDelay Left Edge - Offset for Telemetry TxDqDelay Left Edge in FSP. -**/ - UINT8 TelemetryTxDqDelayLeftEdge; - -/** Offset 0x0246 - Telemetry TxDqDelay Right Edge - Offset for Telemetry TxDqDelay Right Edge in FSP. -**/ - UINT8 TelemetryTxDqDelayRightEdge; - -/** Offset 0x0247 - Volatile Memory Mode - Selects 1LM or 2LM mode for volatile memory. For 2LM memory mode, system will try - to configure 2LM but if system is unable to configure 2LM, volatile memory mode - will fall back to 1LM in FSP - 0: 1LM(Default), 1: 2LM, 2: MIX 1LM2LM. - 0: 1LM, 1: 2LM, 2: MIX 1LM2LM -**/ - UINT8 volMemMode; - -/** Offset 0x0248 - Dynamic ECC Mode Selection - Enable/Disable Dynamic ECC Mode Selection in FSP - 0:Disable, 1:Enable(Default), - 2:Enable + Allow 128b ECC. - 0:Disable, 1:Enable, 2:Enable + Allow 128b ECC -**/ - UINT8 DynamicEccModeSel; - -/** Offset 0x0249 - Memory Patrol Scrub - Memory Patrol Scrub - 0:Disable, 1:Enable during FspMemoryInit(), 2:Enable during - NotifyPhase(EnumInitPhaseReadyToBoot) (Default). - 0:Disable, 1:Enable during FspMemoryInit(), 2:Enable during EnumInitPhaseReadyToBoot -**/ - UINT8 PatrolScrub; - -/** Offset 0x024A - Memory Patrol Scrub - Memory Patrol Scrub - 0:Disable (Default), 1:Enable at ReadyToBootFsp(). - 0:Disable, 1:Enable Enable at ReadyToBootFsp() -**/ - UINT8 PatrolScrubNotify; - -/** Offset 0x024B - Patrol Scrub Interval - Patrol Scrub Interval in FSP. -**/ - UINT8 PatrolScrubDuration; - -/** Offset 0x024C - Patrol Scrub Address Mode - Selects the address mode between 1: System Physical Address (Default), 0:Reverse - Address in FSP. - 0:Reverse Address, 1:System Physical Address -**/ - UINT8 PatrolScrubAddrMode; - -/** Offset 0x024D - Memory Thermal Throttling Mode - Memory Configure Memory Thermal Throttling Mode in FSP - 0:Disable, 2:CLTT_ENABLE(Default), - 3:CLTT_PECI_ENABLE. - 0:Disable, 2:CLTT_ENABLE, 3:CLTT_PECI_ENABLE -**/ - UINT8 thermalthrottlingsupport; - -/** Offset 0x024E - Memory Correctable Error Threshold - Memory Correctable Error Threshold (1 - 32767) used for sparing and leaky bucket in FSP. -**/ - UINT16 spareErrTh; - -/** Offset 0x0250 - WR CRC feature Control - Enable/Disable Write CRC in FSP - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 WrCRC; - -/** Offset 0x0251 - Adaptive Refresh Management Level - Selects Adaptive Refresh Management(ARFM) Level when refresh management(RFM) is - required. 0:Default - RAAIMT, RAAMMT, RAADEC(Default); 1:Level A - RAAIMT-A, - RAAMMT-A, RAADEC-A; 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C, - RAAMMT-C, RAADEC-C - 0:Default - RAAIMT; RAAMMT; RAADEC, 1:Level A - RAAIMT-A; RAAMMT-A; RAADEC-A, 2:Level - B - RAAIMT-B; RAAMMT-B; RAADEC-B, 3:Level C - RAAIMT-C; RAAMMT-C; RAADEC-C -**/ - UINT8 AdaptiveRefreshMgmtLevel; - -/** Offset 0x0252 - MEMHOT INPUT Control - Enable/Disable MEMHOT INPUT in FSP - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 MemHotIn; - -/** Offset 0x0253 - MEMHOT OUTPUT Mode - MEMHOT OUTPUT Mode in FSP - 0:Disable, 1:Enable only temphi(Default), 2:Enable - temphi & mid, 3:Enable temphi & mid & low. - 0:Disable, 1:Enable only temphi, 2:Enable temphi & mid, 3:Enable temphi & mid & low -**/ - UINT8 MemhotOutputOnlyOpt; - -/** Offset 0x0254 - CxlType3LegacyEn - Enable or disable CXL type 3 device using CXL type 2 flow - 0:Disable(Default), 1:Enable. - 0:Disable, 1:Enable -**/ - UINT8 DfxCxlType3LegacyEn; - -/** Offset 0x0255 - DfxPmicSecureMode - 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode(Default). - 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode -**/ - UINT8 DfxPmicSecureMode; - -/** Offset 0x0256 - IIO PcieSubSystemMode0 - PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, - 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, 0x01:IIO_MODE_GEN5(Default) -**/ - UINT8 IioPcieSubSystemMode0[8]; - -/** Offset 0x025E - IIO PcieSubSystemMode1 - PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, - 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, 0x01:IIO_MODE_GEN5(Default) -**/ - UINT8 IioPcieSubSystemMode1[8]; - -/** Offset 0x0266 - IIO PcieSubSystemMode2 - PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, - 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, 0x01:IIO_MODE_GEN5(Default) -**/ - UINT8 IioPcieSubSystemMode2[8]; - -/** Offset 0x026E - IIO PcieSubSystemMode3 - PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, - 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, 0x01:IIO_MODE_GEN5(Default) -**/ - UINT8 IioPcieSubSystemMode3[8]; - -/** Offset 0x0276 - IIO PcieSubSystemMode4 - PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, - 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, 0x01:IIO_MODE_GEN5(Default) -**/ - UINT8 IioPcieSubSystemMode4[8]; - -/** Offset 0x027E - IIO PcieSubSystemMode5 - PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, - 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, 0x01:IIO_MODE_GEN5(Default) -**/ - UINT8 IioPcieSubSystemMode5[8]; - -/** Offset 0x0286 - IIO PcieSubSystemMode6 - PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, - 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, 0x01:IIO_MODE_GEN5(Default) -**/ - UINT8 IioPcieSubSystemMode6[8]; - -/** Offset 0x028E - CXL Header Bypass - Enable/Disable the CXL header bypass in FSP - 0:Disabled(Default), 1:Enabled. - 0:Disable, 1:Enable -**/ - UINT8 DfxCxlHeaderBypass; - -/** Offset 0x028F - CXL Security Level - CXL Security Level
\n - 0: Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device - attached memory ranges in the WB address space.
\n - 1: Partially Trusted - CXL Device can get access on CXL.$ for device attached memory - ranges only;
\n - 2: Untrusted - All requests on CXL.$ will be aborted by the Host.
\n - 3: Auto - Currently identical to Fully Trusted. (Default) - 0:Fully Trusted, 1:Partially Trusted, 2:Untrusted, 3:Auto -**/ - UINT8 DfxCxlSecLvl; - -/** Offset 0x0290 -**/ - UINT32 DfxCxlDebugModePtr; - -/** Offset 0x0294 -**/ - UINT32 DfxCxlDebugModeNumber; - -/** Offset 0x0298 - Lock Chipset - Lock or Unlock chipset in FSP - 0:Disabled(Default), 1:Enabled. - 0:Disable, 1:Enable -**/ - UINT8 LockChipset; - -/** Offset 0x0299 - MSR Lock Control - Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to - remove lock bits - 0:Disabled(Default), 1:Enabled. - 0:Disable, 1:Enable -**/ - UINT8 ProcessorMsrLockControl; - -/** Offset 0x029A - DFX Enable - When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP - 0:Disabled(Default), - 1:Enabled. - 0:Disable, 1:Enable -**/ - UINT8 DFXEnable; - -/** Offset 0x029B - DFX Disable Bios Done - When Enabled, suppresses notifying processor via MSR 151h that boot initialization - is finished in FSP - 0:Disabled(Default), 1:Enabled. - 0:Disable, 1:Enable -**/ - UINT8 DfxDisableBiosDone; - -/** Offset 0x029C - Processor Package C State - Package C State - 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) - state, 7: No Limit, 0xFF: Auto (Default) - 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) state, - 7: No Limit, 0xFF: Auto -**/ - UINT8 CpuPmPackageCState; - -/** Offset 0x029D - Enhanced Intel SpeedStep(R) Tech - Enhanced Intel SpeedStep(R) Tech - 1: Enable(Default), 0: Disable. - 0:Disabled, 1:Enabled -**/ - UINT8 CpuPmEistEnable; - -/** Offset 0x029E - C1E - C1E - 1: Enable(Default), 0: Disable. -**/ - UINT8 CpuPmC1eEnable; - -/** Offset 0x029F - Intel SST-PP - Intel SST-PP Select allows user to choose level - 0xFF: Choose lowest level hardware - supported(Default), 0: Level 0, 3: Level 3, 4: Level 4. -**/ - UINT8 CpuPmIssTdpLevel; - -/** Offset 0x02A0 - Activate SST-BF - SST-BF - 0: Disable (Default), 1: Enabled. - 0:Disabled, 1:Enabled -**/ - UINT8 CpuPmProcessorActivePbf; - -/** Offset 0x02A1 -**/ - UINT8 UnusedUpdSpace13[7]; - -/** Offset 0x02A8 - Socket 0 Core Disable Bitmask - Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0. NOTE: Any core - disabled by user will force static SST-PP. -**/ - UINT64 CpuPmCoreDisableBitmask0; - -/** Offset 0x02B0 - Socket 1 Core Disable Bitmask - Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1. NOTE: Any core - disabled by user will force static SST-PP. -**/ - UINT64 CpuPmCoreDisableBitmask1; - -/** Offset 0x02B8 -**/ - UINT8 ReservedMemoryInitUpd[16]; -} FSPM_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSPM_CONFIG FspmConfig; - -/** Offset 0x02C8 -**/ - UINT8 UnusedUpdSpace14[6]; - -/** Offset 0x02CE -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h deleted file mode 100644 index 79e09295af3..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h +++ /dev/null @@ -1,286 +0,0 @@ -/** @file - -Copyright (c) 2022, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/** FSP-S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Processor VmxEnable Function - Processor VmxEnable Function - 1: Enable(Default), 0: Disable Processor VmxEnable Function. - 0: Disable, 1: Enable -**/ - UINT8 VmxEnable; - -/** Offset 0x0021 - Processor TurboMode Function - Processor TurboMode Function - 1: Enable(Default), 0: Disable Processor TurboMode Function. - 0: Disable, 1: Enable -**/ - UINT8 TurboMode; - -/** Offset 0x0022 - Processor Safer Mode Extensions Function - Processor Safer Mode Extensions Function - 0: Disable(Default), 1: Enable - Processor Safer Mode Extensions Function. - 0: Disable, 1: Enable -**/ - UINT8 ProcessorSmxEnable; - -/** Offset 0x0023 - SstCp - SstCp - 1: Enable, 0: Disable SstCp(Default). - 0: Disable, 1: Enable -**/ - UINT8 SstCpSetting; - -/** Offset 0x0024 - SstCp Capable Status - SST-CP Capable Status in system - 0: Disable(Default), 1: Enable. - 0: Disable, 1: Enable -**/ - UINT8 SstCpCapableSystem; - -/** Offset 0x0025 -**/ - UINT8 UnusedUpdSpace0[1]; - -/** Offset 0x0026 - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x0030 - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x003A - PchAdrEn - PchAdr - 0: PLATFORM POR(Default), 1: FORCE ENABLE, 2:FORCE DISABLE. - 0: PLATFORM POR, 1: FORCE ENABLE, 2: FORCE DISABLE -**/ - UINT8 PchAdrEn; - -/** Offset 0x003B - EnableTme - EnableTme - 0: Disabled(Default), 1: Enabled, 2:Software Controlled. - 0: Disabled, 1: Enabled, 2:Software Controlled -**/ - UINT8 EnableTme; - -/** Offset 0x003C - EnableTmeBypass - EnableTmeBypass - 0: Disabled(Default), 1: Enabled. - 0: Disabled, 1: Enabled -**/ - UINT8 EnableTmeBypass; - -/** Offset 0x003D - SgxFactoryReset - SgxFactoryReset - 0: Disabled(Default), 1: Enabled. - 0: Disabled, 1: Enabled -**/ - UINT8 SgxFactoryReset; - -/** Offset 0x003E - EnableSgx - EnableSgx - 0: Disabled(Default), 1: Enabled. - 0: Disabled, 1: Enabled -**/ - UINT8 EnableSgx; - -/** Offset 0x003F - SgxPackageInfoInBandAccess - SgxPackageInfoInBandAccess - 0: Disabled(Default), 1: Enabled. - 0: Disabled, 1: Enabled -**/ - UINT8 SgxPackageInfoInBandAccess; - -/** Offset 0x0040 - SgxQoS - SgxQoS - 0: Disabled, 1: Enabled(Default). - 0: Disabled, 1: Enabled -**/ - UINT8 SgxQoS; - -/** Offset 0x0041 - EpochUpdate - EpochUpdate - 1: Change to New Random Owner EPOCHs, 2: Manual User Defined Owner - EPOCHs(Default). - 1: Change to New Random Owner EPOCHs, 2: Manual User Defined Owner EPOCHs -**/ - UINT8 EpochUpdate; - -/** Offset 0x0042 - SgxLeWr - SgxLeWr - 0: Disabled(Default), 1: Enabled. - 0: Disabled, 1: Enabled -**/ - UINT8 SgxLeWr; - -/** Offset 0x0043 - SgxDebugMode - SgxDebugMode - 0: Disabled(Default), 1: Enabled. - 0: Disabled, 1: Enabled -**/ - UINT8 SgxDebugMode; - -/** Offset 0x0044 - SgxAutoRegistrationAgent - SgxAutoRegistrationAgent - 0: Disabled(Default), 1: Enabled. - 0: Disabled, 1: Enabled -**/ - UINT8 SgxAutoRegistrationAgent; - -/** Offset 0x0045 - DfxSgxRegistrationServerSelect - DfxSgxRegistrationServerSelect - 0: SBX(Default), 1: PRX, 2:AUTO, 3:LIV, - 4:SW Defined Server. - 0: SBX, 1: PRX, 2:AUTO, 3:LIV, 4:SW Defined Server -**/ - UINT8 DfxSgxRegistrationServerSelect; - -/** Offset 0x0046 - Processor Enable Monitor MWAIT - Processor Enable Monitor MWAIT - 1: Enable(Default), 0: Disable Processor - Monitor MWAIT. - 0: Disabled, 1: Enabled -**/ - UINT8 CpuPmMonitorMWait; - -/** Offset 0x0047 - Processor C6 - Processor C6 - 1: Enable(Default), 0: Disable Processor C6 (ACPI C3) report to OS. - 0: Disabled, 1: Enabled -**/ - UINT8 CpuPmC6Enable; - -/** Offset 0x0048 - Hardware P-States - Hardware P-States - 0: Disable: Hardware chooses a P-state based on OS Request - (Legacy P-States), 1:Native Mode:Hardware chooses a P-state based on OS guidance(Default), - 2:Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance), 3:Native - Mode with No Legacy Support. - 0: Disable, 1: Native Mode, 2: Out of Band Mode, 3: Native Mode with No Legacy Support -**/ - UINT8 CpuPmProcessorHWPMEnable; - -/** Offset 0x0049 - Power Performance Tuning - Power Performance Tuning - 0: OS Controls EPB (Default), 1: BIOS Controls - EPB, 2: PECI Controls EPB. - 0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB -**/ - UINT8 CpuPmPwrPerfTuning; - -/** Offset 0x004A - Configure SST-BF - Allow (Default)/Disallow BIOS to configure SST-BF High Priority Cores so that SW - does not have to configure - 0:Disable, 1:Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 CpuPmProcessorConfigurePbf; - -/** Offset 0x004B - CF9 Global Reset Promotion - CF9 Global Reset Promotion - 1: Enable promoting CF9 reset to global, 0: Disable - promoting CF9 reset to global(Default). - 0: Disabled, 1: Enabled -**/ - UINT8 MeGrPromotionEnabled; - -/** Offset 0x004C - Global Reset Lock - Global Reset Lock - 1: Enable locking the joint ME and host reset capability(Default), - 0: Disable locking the joint ME and host reset capability. - 0: Disabled, 1: Enabled -**/ - UINT8 MeGrLockEnabled; - -/** Offset 0x004D - Delayed Authentication Mode - Enable or disable Delayed Authentication Mode - 0: Disable(Default), 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 DelayedAuthenticationMode; - -/** Offset 0x004E - Delayed Authentication Mode Override - Enable or disable Delayed Authentication Mode Override - 0: Disable(Default), - 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 DelayedAuthenticationModeOverride; - -/** Offset 0x004F - Core Bios Done Message - Enable or disable Core Bios Done message sent to ME - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 CoreBiosDoneEnabled; - -/** Offset 0x0050 - End Of Post Message - Enable or disable sending END_OF_POST message to ME - 0: Disable, 1: Send in PEI, - 2: Send in DXE(Default). - 0:Disable, 1:Send in PEI, 2:Send in DXE -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x0051 - HMRFPO_LOCK Message - Enable or disable sending HMRFPO_LOCK message to ME - 0: Disable, 1: Enable(Default). - 0:Disable, 1:Enable -**/ - UINT8 MeHmrfpoLockEnabled; - -/** Offset 0x0052 - HMRFPO_ENABLE Message - Enable or disable sending HMRFPO_ENABLE message to ME - 0: Disable(Default), - 1: Enable. - 0:Disable, 1:Enable -**/ - UINT8 MeHmrfpoEnableEnabled; - -/** Offset 0x0053 -**/ - UINT8 UnusedUpdSpace1[1]; - -/** Offset 0x0054 -**/ - UINT8 ReservedSiliconInitUpd[16]; -} FSPS_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPS_CONFIG FspsConfig; - -/** Offset 0x0064 -**/ - UINT8 UnusedUpdSpace2[2]; - -/** Offset 0x0066 -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h deleted file mode 100644 index b8874112f83..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h +++ /dev/null @@ -1,109 +0,0 @@ -/** @file - -Copyright (c) 2022, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** FSP-T Core UPD -**/ -typedef struct { - -/** Offset 0x0020 -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0024 -**/ - UINT32 MicrocodeRegionLength; - -/** Offset 0x0028 -**/ - UINT32 CodeRegionBase; - -/** Offset 0x002C -**/ - UINT32 CodeRegionLength; - -/** Offset 0x0030 -**/ - UINT8 Reserved1[16]; -} FSPT_CORE_UPD; - -/** FSP-T Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Disable Port80 output in FSP-T - Select Port80 Control in FSP-T - 0:VPD-Style, 1:Enable Port80 Output (Default), - 2:Disable Port80 Output, refer to FSP Integration Guide for details. - 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output -**/ - UINT8 FsptPort80RouteDisable; - -/** Offset 0x0041 -**/ - UINT8 ReservedTempRamInitUpd[31]; -} FSPT_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSPT_CONFIG FsptConfig; - -/** Offset 0x0060 -**/ - UINT8 UnusedUpdSpace0[6]; - -/** Offset 0x0066 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h deleted file mode 100644 index 567d934952d..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h +++ /dev/null @@ -1,145 +0,0 @@ -/** @file - -Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _IIO_PCIE_CONFIG_UPD_H_ -#define _IIO_PCIE_CONFIG_UPD_H_ - -#ifndef MAX_SOCKET -#define MAX_SOCKET 4 -#endif - -#ifndef MAX_LOGIC_IIO_STACK -#define MAX_LOGIC_IIO_STACK 14 -#endif - -#ifndef MAX_IIO_PORTS_PER_SOCKET -#define MAX_IIO_PORTS_PER_SOCKET 57 -#endif - -#ifndef MAX_IOU_PER_SOCKET -#define MAX_IOU_PER_SOCKET 7 -#endif - -#define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD - -#pragma pack(1) - -typedef struct { - UINT8 SLOTEIP[MAX_IIO_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17) - UINT8 SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) - UINT8 SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) - UINT8 SLOTPIP[MAX_IIO_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) - UINT8 SLOTAIP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) - UINT8 SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2) - UINT8 SLOTPCP[MAX_IIO_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1) - UINT8 SLOTABP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) - UINT8 SLOTIMP[MAX_IIO_PORTS_PER_SOCKET]; - UINT8 SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET]; - UINT8 SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET]; - UINT16 SLOTPSP[MAX_IIO_PORTS_PER_SOCKET]; - BOOLEAN VppEnabled[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj - UINT8 VppPort[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj - UINT8 VppAddress[MAX_IIO_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj - UINT8 MuxAddress[MAX_IIO_PORTS_PER_SOCKET]; // SMBUS address of MUX //no setup option defined - UINT8 ChannelID[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- channel 0, 01 -- channel 1 //no setup option defined - - UINT8 PciePortEnable[MAX_IIO_PORTS_PER_SOCKET]; - UINT8 PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD - UINT8 HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET]; // to suppress /display the PCIe port menu - UINT8 PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET]; - UINT8 RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET]; - UINT8 ConfigIOU[MAX_IOU_PER_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) - UINT8 PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port - UINT8 VMDEnabled[MAX_VMD_STACKS_PER_SOCKET]; - UINT8 VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET]; - UINT8 VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET]; - UINT8 PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET]; - UINT8 PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5. - UINT8 DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9. - UINT8 PcieGlobalAspm; - UINT8 PcieMaxReadRequestSize; -} UPD_IIO_PCIE_PORT_CONFIG; - -typedef struct { - struct { - UINT8 Segment; ///< Remember segment, if it changes reset everything - UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack - } Socket[MAX_SOCKET]; -} SYSTEM_PCI_BUS_CONFIGURATION; - -typedef struct { - UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions) - UINT64 Limit; ///< Limit (last valid) address of a range -} PCIE_BASE_LIMIT; - -typedef struct { - UINT32 MmioLSize; - UINT64 MmioHSize; -} CXL11_LIMITS; - -typedef struct { - PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity - PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity - PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity -} PCI_BASE_LIMITS; - -typedef struct { - PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of all PCIe resources for the socket - PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket - CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket -} SOCKET_PCI_BASE_LIMITS; - -typedef struct { - // - // Save basic system configuration parameters along with the resource map to detect a change. - // Remember low and high I/O memory range when saving recource configuration. It is used to verify - // whether system memory map changed. Remember also stacks configured when creating the map. - // If anything changed reset the system PCI resource configuration. - // - UINT64 MmioHBase; - UINT64 MmioHGranularity; - UINT32 MmioLBase; - UINT32 MmioLLimit; - UINT32 MmioLGranularity; - UINT16 IoBase; - UINT16 IoLimit; - UINT16 IoGranularity; - UINT32 StackPresentBitmap[MAX_SOCKET]; - // - // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options - // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook - // which updates the KTI resource map. - // - SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket -} SYSTEM_PCI_BASE_LIMITS; - -#pragma pack() - -#endif // _IIO_PCIE_CONFIG_UPD_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h deleted file mode 100644 index 8d4c0192dbe..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h +++ /dev/null @@ -1,253 +0,0 @@ -/** @file - -Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _IIO_UNIVERSAL_DATA_HOB_H_ -#define _IIO_UNIVERSAL_DATA_HOB_H_ - -#define IIO_UNIVERSAL_DATA_GUID { \ - 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ - 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ -} - -#ifndef MAX_SOCKET -#define MAX_SOCKET 4 -#endif - -#if (MAX_SOCKET == 1) - #define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition. -#else - #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition -#endif //(MAX_SOCKET == 1) - -#ifndef MAX_IMC -#define MAX_IMC 4 // Maximum memory controllers per socket -#endif - -#ifndef MAX_MC_CH -#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP) -#endif - -#ifndef MAX_CH -#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16) -#endif - -#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes - -#ifndef MAX_IIO_PORTS_PER_SOCKET -#define MAX_IIO_PORTS_PER_SOCKET 57 -#endif - -#ifndef MAX_IIO_STACK -#define MAX_IIO_STACK 12 -#endif - -#define MAX_LOGIC_IIO_STACK 14 - -#define MAX_COMPUTE_DIE 1 -#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers) - -#pragma pack(1) - -typedef struct _UINT64_STRUCT { - UINT32 lo; - UINT32 hi; -} UINT64_STRUCT, *PUINT64_STRUCT; - -#ifndef MMIO_BARS_ENUM -#define MMIO_BARS_ENUM -typedef enum { - TYPE_SCF_BAR = 0, - TYPE_PCU_BAR, - TYPE_MEM_BAR0, - TYPE_MEM_BAR1, - TYPE_MEM_BAR2, - TYPE_MEM_BAR3, - TYPE_MEM_BAR4, - TYPE_MEM_BAR5, - TYPE_MEM_BAR6, - TYPE_MEM_BAR7, - TYPE_SBREG_BAR, - TYPE_MAX_MMIO_BAR -} MMIO_BARS; -#endif - -typedef struct { - UINT8 Device; - UINT8 Function; -} IIO_PORT_INFO; - -typedef struct { - UINT8 Major; - UINT8 Minor; - UINT8 Revision; - UINT16 BuildNumber; -} RC_VERSION; - -//--------------------------------------------------------------------------------------// -// Structure definitions for Universal Data Store (UDS) -//--------------------------------------------------------------------------------------// -typedef struct { - UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) - UINT8 PeerSocId; // Socket ID - UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO) - UINT8 PeerPort; // Port of the peer socket -} QPI_PEER_DATA; - -typedef struct { - UINT8 Valid; - UINT32 MmioBar[TYPE_MAX_MMIO_BAR]; - UINT8 PcieSegment; - UINT64_STRUCT SegMmcfgBase; - UINT32 StackPresentBitmap; - UINT16 CxlPresentBitmap; - UINT16 Cxl20CapableBitmap; - UINT8 TotM3Kti; - UINT8 TotCha; - UINT32 ChaList[MAX_CHA_MAP]; - UINT32 SocId; - QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info -} QPI_CPU_DATA; - -typedef struct { - UINT8 Valid; - UINT8 SocId; - QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info -} QPI_IIO_DATA; - -typedef struct { - IIO_PORT_INFO PortInfo[MAX_IIO_PORTS_PER_SOCKET]; -} IIO_DMI_PCIE_INFO; - -typedef struct _STACK_RES { - UINT8 Personality; - UINT8 BusBase; // Base of Bus configured for this stack - UINT8 BusLimit; // Limit of Bus configured for this stack - UINT16 IoBase; // Base of IO configured for this stack - UINT16 IoLimit; // Limit of IO configured for this stack - UINT32 IoApicBase; - UINT32 IoApicLimit; - UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map - UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map - UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map - UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map - UINT8 PciResourceBusBase; // Base of Bus resource available for PCI devices - UINT8 PciResourceBusLimit; // Limit of Bus resource available for PCI devices - UINT16 PciResourceIoBase; // Base of IO resource available for PCI devices - UINT16 PciResourceIoLimit; // Limit of IO resource available for PCI devices - UINT32 PciResourceMem32Base; // Base of low MMIO resource available for PCI devices - UINT32 PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices - UINT64 PciResourceMem64Base; // Base of high MMIO resource available for PCI devices - UINT64 PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices - UINT32 VtdBarAddress; // NOTE: Obsolete, not used in next gen platforms -} STACK_RES; - -typedef struct { - UINT8 Valid; - UINT8 SocketID; // Socket ID of the IIO (0..3) - UINT8 BusBase; - UINT8 BusLimit; - UINT16 PciResourceIoBase; - UINT16 PciResourceIoLimit; - UINT32 IoApicBase; - UINT32 IoApicLimit; - UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map - UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map - UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map - UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map - STACK_RES StackRes[MAX_LOGIC_IIO_STACK]; - IIO_DMI_PCIE_INFO PcieInfo; // NOTE: Obsolete, not used in next gen platforms -} IIO_RESOURCE_INSTANCE; - -typedef struct { - UINT16 PlatGlobalIoBase; // Global IO Base - UINT16 PlatGlobalIoLimit; // Global IO Limit - UINT32 PlatGlobalMmio32Base; // Global Mmiol base - UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit - UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [43:0] - UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0] - QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU - QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO - UINT32 MemTsegSize; - UINT64 PciExpressBase; - UINT32 PciExpressSize; - UINT32 MemTolm; - IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; - UINT8 numofIIO; - UINT8 MaxBusNumber; - UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. for CpuSv - UINT8 EVMode; - UINT8 SkuPersonality[MAX_SOCKET]; - UINT16 IoGranularity; - UINT32 MmiolGranularity; - UINT64_STRUCT MmiohGranularity; - UINT8 RemoteRequestThreshold; //5370389 - UINT32 UboxMmioSize; - UINT32 MaxAddressBits; -} PLATFORM_DATA; - -typedef struct { - UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode) - UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT) - UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC - UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM - UINT8 IsocEnable; - UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB - UINT8 DmiVc1; - UINT8 DmiVcm; - UINT32 CpuPCPSInfo; - UINT8 cpuSubType; - UINT8 SystemRasType; - UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC - UINT16 tolmLimit; - RC_VERSION RcVersion; - BOOLEAN MsrTraceEnable; - UINT8 DdrXoverMode; // DDR 2.2 Mode - // For RAS - UINT8 bootMode; - UINT8 OutClusterOnDieEn; // Whether RC enabled COD support - UINT8 OutSncEn; - UINT8 OutNumOfCluster; - UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; - UINT16 LlcSizeReg; - UINT8 chEnabled[MAX_SOCKET][MAX_CH]; - UINT8 memNode[MC_MAX_NODE]; - UINT8 IoDcMode; - UINT8 DfxRstCplBitsEn; - UINT8 BitsUsed; //For 5 Level Paging -} SYSTEM_STATUS; - -typedef struct { - PLATFORM_DATA PlatformData; - SYSTEM_STATUS SystemStatus; - UINT32 OemValue; -} IIO_UDS; -#pragma pack() - -#endif //#ifndef _IIO_UNIVERSAL_DATA_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h deleted file mode 100644 index 0d1cdb9f0cc..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h +++ /dev/null @@ -1,373 +0,0 @@ -/** @file - -Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _MEMORY_MAP_DATA_HOB_H_ -#define _MEMORY_MAP_DATA_HOB_H_ - -#define MEMORY_MAP_HOB_GUID \ - { \ - 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \ - } - -#ifndef MAX_SOCKET -#define MAX_SOCKET 4 -#endif - -#ifndef MAX_IMC -#define MAX_IMC 4 // Maximum memory controllers per socket -#endif - -#ifndef MAX_MC_CH -#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP) -#endif - -#ifndef MAX_CH -#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16) -#endif - -#define MAX_CXL_AMT 0 - -#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE -#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM -#endif - -#ifndef MAX_SPARE_RANK -#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel -#endif - -#ifndef MAX_HBM_IO -#define MAX_HBM_IO 4 -#endif - -#ifndef MAX_DIMM -#define MAX_DIMM 2 // Max DIMM per channel -#endif - -#ifndef MAX_RANK_DIMM -#define MAX_RANK_DIMM 2 -#endif - -#ifndef MAX_DRAM_CLUSTERS -#define MAX_DRAM_CLUSTERS 4 -#endif - -#ifndef MAX_SAD_RULES -#define MAX_SAD_RULES 16 -#endif - -#ifndef MAX_FPGA_REMOTE_SAD_RULES -#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform -#endif - -#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number - -#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket -#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets - -// NGN -#define NGN_MAX_SERIALNUMBER_STRLEN 4 -#define NGN_MAX_PARTNUMBER_STRLEN 30 -#define NGN_FW_VER_LEN 4 -#define NGN_LOG_TYPE_NUM 2 -#define NGN_LOG_LEVEL_NUM 2 - -/** - * Memory channel index conversion macros. - * - * We got two types of memory channel indexes: - * - socket channel - indexes 0..MAX_CH, used in [socket][channel] indexing - * - IMC channel - indexes 0..MAX_MC_CH, used in [socket][IMC][channel] indexing - * The below defined macros convert one channel index to the other one. - */ -#define MEM_SKTCH_TO_IMC(SktCh) ((SktCh) / MAX_MC_CH) -#define MEM_SKTCH_TO_IMCCH(SktCh) ((SktCh) % MAX_MC_CH) -#define MEM_IMCCH_TO_SKTCH(Imc, Ch) ((Imc) * MAX_MC_CH + (Ch)) - -#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26) -#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16) -#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6) -#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4) -#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26) -#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16) -#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6) - -typedef UINT8 CXL_INTLV_SET_KEY; - -#define FSP_RESERVED1_LEN 77 -#define FSP_RESERVED2_LEN 2174 -#define FSP_RESERVED3_LEN 21 -#define FSP_RESERVED4_LEN 130 -#define FSP_RESERVED5_LEN 10 -#define FSP_RESERVED6_LEN 800 -#pragma pack(1) - -typedef enum { - DIMM_RANK_MAP_OUT_UNKNOWN = 0, - DIMM_RANK_MAP_OUT_MEM_DECODE, - DIMM_RANK_MAP_OUT_POP_POR_VIOLATION, - DIMM_RANK_MAP_OUT_RANK_DISABLED, - DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE, - DIMM_RANK_MAP_OUT_MAX -} DIMM_RANK_MAP_OUT_REASON; - -struct RankDevice { - UINT8 enabled; // 0 = disabled, 1 = enabled - UINT8 logicalRank; // Logical Rank number (0 - 7) - UINT16 rankSize; // Units of 64 MB -}; - -struct PersisentDpaMap -{ - UINT32 perRegionDPAOffset; - UINT32 SPALimit; -}; - -typedef struct firmwareRev { - UINT8 majorVersion; - UINT8 minorVersion; - UINT8 hotfixVersion; - UINT16 buildVersion; -} FIRMWARE_REV; - -typedef struct DimmDevice { - UINT8 Present; - BOOLEAN Enabled; - UINT8 DcpmmPresent; // 1 - This is a DCPMM - UINT8 X4Present; - UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16) - UINT8 NumRanks; - UINT8 keyByte; - UINT8 actKeyByte2; // Actual module type reported by SPD - UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width - UINT8 dimmTs; // Thermal sensor data. - UINT16 VolCap; // Volatile capacity (AEP DIMM only) - UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only) - UINT16 DimmSize; - UINT32 NVmemSize; - UINT16 SPDMMfgId; // Module Mfg Id from SPD - UINT16 VendorID; - UINT16 DeviceID; - UINT16 RevisionID; - UINT32 perRegionDPA; // DPA of PMEM that Nfit needs - struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map - UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number - UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number - UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17 - struct firmwareRev FirmwareVersion; // Firmware revision - struct RankDevice rankList[MAX_RANK_DIMM]; - UINT16 InterfaceFormatCode; - UINT16 SubsystemVendorID; - UINT16 SubsystemDeviceID; - UINT16 SubsystemRevisionID; - UINT16 FisVersion; // Firmware Interface Specification version - UINT8 DimmSku; // Dimm SKU info - UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM - UINT16 manufacturingDate; // Date the NVDIMM was manufactured - INT32 commonTck; - UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source - BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present - UINT8 CidBitMap; // SubRankPer CS for DIMM device - UINT16 SPDRegVen; // Register Vendor ID in SPD - DIMM_RANK_MAP_OUT_REASON MapOutReason; -} MEMMAP_DIMM_DEVICE_INFO_STRUCT; - -struct ChannelDevice { - UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled - UINT8 Features; // Bit mask of features to enable or disable - UINT8 MaxDimm; // Number of DIMM - UINT8 NumRanks; // Number of ranks on this channel - UINT8 chFailed; - UINT8 ngnChFailed; - UINT8 Is9x4DimmPresent; // 9x4 dimm present indicator - UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare - UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare - UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size - UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled - UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1) - UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1) - MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM]; -}; - -struct memcontroller { - UINT32 MemSize; -}; - -typedef enum { - MemTypeNone = 0, - MemType1lmDdr, - MemType1lmAppDirect, - MemType1lmAppDirectReserved, - MemType1lmCtrl, - MemType1lmHbm, - MemTypeNxm, - MemType2lmDdrCacheMemoryMode, - MemType2lmDdrWbCacheAppDirect, - MemType2lmHbmCacheDdr, - MemType2lmHbmCacheMemoryMode, - MemTypeCxlAccVolatileMem, - MemTypeCxlAccPersistentMem, - MemTypeFpga, - MemTypeCxlExpVolatileMem, - MemTypeCxlExpPersistentMem, - MemTypeCxl2lmDdrCacheMem, - MemTypeCxlHetero, - MemTypeMax -} MEM_TYPE; - -typedef struct SADTable { - UINT8 Enable; // Rule enable - MEM_TYPE type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges. - UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options - UINT32 Base; // Base of the current SAD entry - UINT32 Limit; // Limit of the current SAD entry - UINT8 ways; // Interleave ways for SAD - UINT8 channelInterBitmap[MAX_AMT]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved - UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved - UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM. - UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT. - UINT16 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket. - UINT16 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM. - BOOLEAN local; // 0 - Remote 1- Local - UINT8 IotEnabled; // To indicate if IOT is enabled - UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring - UINT8 Attr; - UINT8 tgtGranularity; // Interleave mode for target list - UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index. - UINT8 HostBridgeGran; // Host bridge interleaving granularity. - UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD. - CXL_INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm) -} SAD_TABLE; - -typedef struct socket { - UINT8 SocketEnabled; - UINT32 IioStackBitmap; - BOOLEAN HbmIoEn[MAX_HBM_IO]; // Flag indicates if HBM IO is enabled. TRUE: HBM IO is Enabled, FALSE: HBM IO is disabled. - UINT8 imcEnabled[MAX_IMC]; - UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list - UINT32 SktTotMemMapSPA; // Total memory mapped to SPA - UINT32 SktMemSize2LM; // Total memory excluded from Limit - SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table - struct memcontroller imc[MAX_IMC]; - struct ChannelDevice ChannelInfo[MAX_CH]; -} MEMMAP_SOCKET; - -typedef struct { - UINT8 Enabled; // Indicates if this EDC is enabled - UINT32 MemAsCache; // Memory used as Cache, in 64MB units - UINT32 MemAsFlat; // Memory used as Flat memory, in 64MB units -} EDC_INFO; - -typedef struct SystemMemoryMapElement { - UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region - UINT8 NodeId; // Node ID of the HA Owning the memory - UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA - UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets - UINT16 ImcInterBitmap; // IMC interleave bitmap for this memory - UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved - UINT32 BaseAddress; // Base Address of the element in 64MB chunks - UINT32 ElementSize; // Size of this memory element in 64MB chunks -} SYSTEM_MEMORY_MAP_ELEMENT; - -typedef struct SystemMemoryMapHob { - // - // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters. - // All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1). - // - UINT8 TotalClusters; - - UINT8 reserved1[FSP_RESERVED1_LEN]; // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure - UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. - UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. - UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. - UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. - UINT32 memSize; // Total physical memory size - UINT16 memFreq; // Mem Frequency - UINT16 HbmFreq; // HBM Frequency in MHz. - UINT8 memMode; // 0 - Independent, 1 - Lockstep - UINT8 volMemMode; // 0 - 1LM, 1 - 2LM - UINT8 CacheMemType; // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM - UINT16 DramType; - UINT8 DdrVoltage; - BOOLEAN SupportedPMemPresent; // TRUE if at least one PMem is present and supported by BIOS - BOOLEAN EkvPresent; // Set if EKV controller on system - BOOLEAN BwvPresent; // Set if BWV controller on system - BOOLEAN CwvPresent; // Set if CWV controller on system - UINT8 XMPProfilesSup; - UINT8 XMPCapability; - // - // HBM Specific Info. - // - UINT16 HbmInstances[MAX_SOCKET]; // Total HBM instances - UINT32 HbmFlatMemSize; // Total HBM memory size in 64MB units, if HBM used as Flat memory - UINT32 HbmCacheMemSize; // Total HBM memory used as cache, if HBM used as Cache memory - UINT16 HbmSpeed; // Configured HBM (i.e OPIO channel) speed in MT/s. - UINT16 MaxHbmSpeed; // Max HBM (i.e OPIO channel) speed in MT/s. - UINT8 SystemRasType; - UINT8 RasModesEnabled; // RAS modes that are enabled - UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled - UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration - UINT8 NumOfCluster; - UINT8 NumChPerMC; - UINT8 numberEntries; // Number of Memory Map Elements - SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved2[FSP_RESERVED2_LEN]; // struct memSetup MemSetup; - UINT8 reserved3[FSP_RESERVED3_LEN]; // MEM_DFXMEMVARS DfxMemVar; - MEMMAP_SOCKET Socket[MAX_SOCKET]; - UINT8 reserved4[FSP_RESERVED4_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES]; - - UINT8 reserved5[FSP_RESERVED5_LEN]; // RASMEMORYINFO RasMeminfo; - UINT8 LatchSystemShutdownState; - BOOLEAN IsWpqFlushSupported; - UINT8 EadrSupport; - UINT8 EadrCacheFlushMode; - UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH - UINT8 reserved6[FSP_RESERVED6_LEN]; // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH]; - UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity) - BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules - UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW) - UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW) - UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power - UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW). - UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW). - UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power - UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant - UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant - UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant - UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon) - UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters - BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA - UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster) -} SYSTEM_MEMORY_MAP_HOB; - -#pragma pack() - -#endif // _MEMORY_MAP_DATA_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h deleted file mode 100644 index f1d55542c3a..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h +++ /dev/null @@ -1,85 +0,0 @@ -/** @file - -Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _PREV_BOOT_ERR_SRC_HOB_H_ -#define _PREV_BOOT_ERR_SRC_HOB_H_ - -#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \ -{ 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } - -#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000 - -#pragma pack(1) - -typedef struct { -UINT16 Length; // Actual size of the error sources used in the HOB -UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO -}PREV_BOOT_ERR_SRC_HOB; - -typedef struct{ -UINT8 Type; // McBankType = 1; -UINT8 Segment; -UINT8 Socket; -UINT16 ApicId; // ApicId is Needed only if it a core McBank. -UINT16 McBankNum; -UINT64 McBankStatus; -UINT64 McbankAddr; -UINT64 McBankMisc; -} MCBANK_ERR_INFO; - -typedef struct { -UINT8 Type; // PciExType =2 ; -UINT8 Segment; -UINT8 Bus; -UINT8 Device; -UINT8 Function; -UINT32 AerUncErrSts; -UINT8 AerHdrLogData[16]; -} PCI_EX_ERR_INFO; - -typedef struct { -UINT8 Type; // Other Csr error type =3 ; -UINT8 Segment; -UINT8 Bus; -UINT8 Device; -UINT8 Function; -UINT16 offset; -UINT32 Value; -} CSR_ERR_INFO; - -typedef enum { - McBankType = 1, - PciExType, - CsrOtherType -} ERROR_ACCESS_TYPE; - -#pragma pack() - -#endif //_PREV_BOOT_ERR_SRC_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h deleted file mode 100644 index b6d88f5c304..00000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h +++ /dev/null @@ -1,283 +0,0 @@ -/** @file - -Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - -**/ - -#ifndef _SYSTEM_INFO_HOB_H_ -#define _SYSTEM_INFO_HOB_H_ - -#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }} - -#ifndef MAX_SOCKET -#define MAX_SOCKET 4 -#endif - -#ifndef MAX_IIO_STACK -#define MAX_IIO_STACK 12 -#endif - -#define MAX_LOGIC_IIO_STACK 14 - -#ifndef MAX_IMC -#define MAX_IMC 4 // Maximum memory controllers per socket -#endif - -#ifndef MAX_MC_CH -#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP) -#endif - -#ifndef MAX_CH -#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16) -#endif - -#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure -#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD - -#pragma pack(1) - -#ifndef MMIO_BARS_ENUM -#define MMIO_BARS_ENUM -typedef enum { - TYPE_SCF_BAR = 0, - TYPE_PCU_BAR, - TYPE_MEM_BAR0, - TYPE_MEM_BAR1, - TYPE_MEM_BAR2, - TYPE_MEM_BAR3, - TYPE_MEM_BAR4, - TYPE_MEM_BAR5, - TYPE_MEM_BAR6, - TYPE_MEM_BAR7, - TYPE_SBREG_BAR, - TYPE_MAX_MMIO_BAR -} MMIO_BARS; -#endif - -typedef enum { - ReservedMemSs, - Ddr4MemSs = 1, - Ddr5MemSs = 2, - LpDdr4MemSs = 3, - LpDdr5MemSs = 4, - Hbm2MemSs = 5, - MrcMstMax, - MrcMstDelim = MAX_INT32 -} MRC_MST; - -typedef enum BootMode { - NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc. - // Some of these MRC specific init routines can be skipped based on MRC input params - // in addition to the sub-boot type (WarmBoot, WarmBootFast, etc). - S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3 - // init and be optimized for speed. -} BootMode; - -// -// This is used to determine what type of die is connected to a UPI link -// -typedef enum { - UpiConnectionTypeCpu, - UpiConnectionTypePcieGen4, - UpiConnectionTypeFpga, - UpiConnectionTypeMax -} UPI_CONNECTION_TYPE; - -// -// VSEC info for HPM -// The HPM_INFO struct contains info collected from the VSEC structure for the HPM. -// VSEC Structure is defined as below: -// -// ------------------------VSEC Structure------------------------ -// | Next Cap Offset(12b) | Cap Version(4b) | PCIe Cap ID(16b) | -// -------------------------------------------------------------- -// | VSEC_LEN(12b) | VSEC_REV(4b) | VSEC_ID(16b) | -// -------------------------------------------------------------- -// | EntrySize(8b) | NumEntries(8b) | Rsvd(16b) | -// -------------------------------------------------------------- -// | Address(29b) | tBIR(3b) | -// -------------------------------------------------------------- -// -// -typedef struct { - UINT8 NumEntries; // The number of PM feature interface instances in this VSEC space - UINT8 EntrySize; // The entry size for each PM interface instance in 32-bit DWORDs - UINT32 Address; // The offset from the BAR register which is used for HPM to point to the base of the discovery entry. i.e. the PFS (PM Feature Structure) - UINT8 tBIR; // Which one of he function's BAR is used for the PFS offset -} HPM_INFO; - -// -//-------------------------------- - PFS Entry-------------------------------- -//| EntrySize(16b) | NumEntries(8b) | VSEC_SubID(8b) | -//---------------------------------------------------------------------------- -//| RSVD(14b) | Attr(2b) | CapOffset(16b) | -//---------------------------------------------------------------------------- -// -typedef struct { - UINT32 TpmiId : 8; - UINT32 NumEntries : 8; - UINT32 EntrySize : 16; - UINT32 CapOffset : 16; - UINT32 Attribute : 2; - UINT32 EntryBitMap : 8; - UINT32 Rsvd : 6; -} PFS_ENTRY; - -// -// HPM (Hierarchical Power Management) VSEC resource allocation info -// -typedef struct { - BOOLEAN HpmEnabled; // HPM enabled or not in BIOS knob - BOOLEAN HpmInfraReady; // All the HPM infrastructure data is buffered - UINT32 OobMsmHpmBarBase; // The base of OOBMSM BAR1 for HPM PFS and LUT tables - UINT32 OobMsmHpmBarLimit; // The limit of OOBMSM BAR1 from where the required size will be allocated - UINT32 OobMsmHpmBarMmcfgAddress; // The OOBMSM BAR1 MMCFG address - UINT32 OobMsmHpmBarRequiredSize; // The required size of OOBMSM BAR1 - - HPM_INFO HpmVsecInfo; // For now, single VSEC is assumed - PFS_ENTRY Pfs[MAX_HPM_PFS_ENTRY_NUM]; // The buffered PFS structure - -} HPM_VSEC_RESOURCE; - -// -// Stack id swap information, which includes stack swap flag and the new stack id swap array. -// -typedef struct { - BOOLEAN StackSwapFlag; - UINT8 StackIdSwapArray[MAX_IIO_STACK]; -} STACKID_SWAP_INFO; - -typedef struct { - UINT64 Cxl1p1RcrbBase; - BOOLEAN Cxl1p1RcrbValid; -} CXL_1P1_RCRB; - -typedef struct { - UINT32 StackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket - UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack - UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK]; ///< mmiol of each IIO stack, if it works as CXL, the mmiol base is RCRBBAR - UINT8 SocketFirstBus[MAX_SOCKET]; - UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only - UINT8 TotIoDie[MAX_SOCKET]; //GNR & SRF CPU use only - UINT8 TotCmpDie[MAX_SOCKET]; //GNR & SRF CPU use only - UINT8 SocketLastBus[MAX_SOCKET]; - UINT8 segmentSocket[MAX_SOCKET]; - UINT8 KtiPortCnt; - UINT32 socketPresentBitMap; - UINT32 SecondaryNodeBitMap; - UINT32 FpgaPresentBitMap; - UINT32 mmCfgBase; - UINT64 SocketMmCfgBase[MAX_SOCKET]; - UINT8 DdrMaxCh; - UINT8 DdrMaxImc; ///< Logical number of IMC count, ignoring logical holes - UINT8 DdrPhysicalMaxImc; ///< Physical number of IMC count from Capid - UINT8 DdrNumChPerMc; - UINT8 DdrNumPseudoChPerCh; - UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; - UINT8 mcId[MAX_SOCKET][MAX_CH]; - MRC_MST MemSsType[MAX_SOCKET]; ///< MemSsType global identifier for DDR vs. HBM - UINT32 MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR]; - UINT8 HbmMaxCh; - UINT8 HbmMaxIoInst; - UINT8 HbmNumChPerMc; - UINT8 HbmNumChPerIo; - UINT32 LastCsrAddress[2]; - UINT32 LastCsrMmioAddr; - UINT8 CsrCachingEnable; - UINT32 LastCsrMcAddress[2]; - UINT32 LastCsrMcMmioPhyAddr; - UINT8 CsrPciBarCachingEnable; - UINT32 LastCsrPciBarAddr[2]; - UINT64 LastCsrPciBarPhyAddr; - UINT32 LastSBPortId[MAX_SOCKET]; - UPI_CONNECTION_TYPE UpiConnectionType[MAX_SOCKET]; - BOOLEAN PostedCsrAccessAllowed; // SW is allowed to use posted CSR writes method when TRUE - BOOLEAN PostedWritesEnabled; // All CSR writes use posted method when TRUE, non-posted when FALSE - BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE - HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET]; // HPM VSEC info for all sockets - BOOLEAN HbmSku; - UINT8 HcxType[MAX_SOCKET]; - STACKID_SWAP_INFO StackIdSwapInfo[MAX_SOCKET]; //StackID sync after do StackId swap,including Stack swap table and whether do stack swap - CXL_1P1_RCRB Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack - UINT32 DmiRcrb[MAX_SOCKET]; // DMI RCRB region, one per socket - UINT8 FabricType; //Compute die 10x6, 10x5, and 6x5 type is stored - UINT8 ChopType; //Compute Die Chop Type - UINT8 MdfInstCount; -} CPU_CSR_ACCESS_VAR; - -typedef struct { - UINT32 MeRequestedSizeNv; - UINT32 MeRequestedAlignmentNv; - UINT8 SbspSocketIdNv; -} SYS_INFO_VAR_NVRAM; - -typedef struct _CPUID_REGISTER_INFO { - UINT32 Eax; - UINT32 Ebx; - UINT32 Ecx; - UINT32 Edx; -} CPUID_REGISTER_INFO; - -typedef struct _PROCESSOR_COMMON_INFO { - UINT32 capid0; - UINT32 capid1; - UINT32 capid2; - UINT32 capid3; - UINT32 capid4; - UINT32 capid5; - UINT32 capid6lo; - UINT32 capid6hi; - CPUID_REGISTER_INFO ExtCpuid7; - CPUID_REGISTER_INFO ExtCpuid1B; -} PROCESSOR_COMMON_INFO; - -typedef struct { - UINT32 MeRequestedSize; - UINT32 MeRequestedAlignment; - UINT32 CheckPoint; - UINT8 ResetRequired; - UINT8 Emulation; - BootMode SysBootMode; - CPU_CSR_ACCESS_VAR CpuCsrAccessVarHost; // Common resource for CsrAccessRoutines - UINT64 CpuFreq; - UINT8 SocketId; - SYS_INFO_VAR_NVRAM SysInfoVarNvram; - BOOLEAN UsraTraceControl; - UINT16 UsraTraceConfiguration; // Bit 7 6 5 4 3:0 - // Write, Modify, GetAddr, Long/Short, Trace 0x5 as signature - // Bit 15 14:11 10 9 8 - // DumpCpuCsrAccessVar, TBD, CSR, PCIE, Read - BOOLEAN CpuCsrAccessVarInfoDumped; - PROCESSOR_COMMON_INFO ProcessorCommonInfo[MAX_SOCKET]; - EFI_PHYSICAL_ADDRESS SocAddrMapData; - UINTN UsraPpiPtr; -} SYSTEM_INFO_VAR; - - -#pragma pack () - -#endif //#ifndef _SYSTEM_INFO_HOB_H_ diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 15b67703152..47444d38c1b 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -862,7 +862,7 @@ static void print_event_type(uint32_t event_type) printf("%s", tpm_event_types[event_type]); } -static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log) +static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log, size_t size) { const uint8_t zero_block[sizeof(struct tcpa_spec_entry)] = {0}; @@ -883,6 +883,13 @@ static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log) uint32_t len; struct tcpa_log_entry *log_entry = (void *)current; uint32_t event_type = le32toh(log_entry->event_type); + current += sizeof(struct tcpa_log_entry); + len = le32toh(log_entry->event_data_size); + + if (current + len >= (uintptr_t)spec_log + size) { + fprintf(stderr, "Invalid TPM1.2 log entry overflowing cbmem area\n"); + break; + } printf("TCPA log entry %u:\n", ++counter); printf("\tPCR: %d\n", le32toh(log_entry->pcr)); @@ -891,8 +898,6 @@ static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log) printf("\n"); printf("\tDigest: "); print_hex_line(log_entry->digest, SHA1_DIGEST_SIZE); - current += sizeof(struct tcpa_log_entry); - len = le32toh(log_entry->event_data_size); if (len != 0) { current += len; printf("\tEvent data: "); @@ -947,7 +952,7 @@ static uint32_t print_tpm2_digests(struct tcg_pcr_event2_header *log_entry) return current - (uintptr_t)&log_entry->digest_count; } -static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log) +static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log, size_t size) { const uint8_t zero_block[12] = {0}; /* Only PCR index, event type and digest count */ @@ -990,6 +995,12 @@ static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log) /* Now event size and event are left to be parsed */ len = le32toh(*(uint32_t *)current); current += sizeof(uint32_t); + + if (current + len >= (uintptr_t)tpm2_log + size) { + fprintf(stderr, "Invalid TPM2.0 log entry overflowing cbmem area\n"); + break; + } + if (len != 0) { printf("\tEvent data: %.*s\n", len, (const char *)current); current += len; @@ -1017,7 +1028,7 @@ static void dump_tpm_std_log(uint64_t addr, size_t size) tspec_entry->spec_version_minor == 2 && tspec_entry->spec_errata >= 1 && le32toh(tspec_entry->entry.event_type) == EV_NO_ACTION) { - parse_tpm12_log(tspec_entry); + parse_tpm12_log(tspec_entry, size); } else { fprintf(stderr, "Unknown TPM1.2 log specification\n"); } @@ -1030,7 +1041,7 @@ static void dump_tpm_std_log(uint64_t addr, size_t size) if (tcg_spec_entry->spec_version_major == 2 && tcg_spec_entry->spec_version_minor == 0 && le32toh(tcg_spec_entry->event_type) == EV_NO_ACTION) { - parse_tpm2_log(tcg_spec_entry); + parse_tpm2_log(tcg_spec_entry, size); } else { fprintf(stderr, "Unknown TPM2 log specification.\n"); } diff --git a/util/dasharo/tag-with-changelog b/util/dasharo/tag-with-changelog new file mode 100755 index 00000000000..7573ec96c6a --- /dev/null +++ b/util/dasharo/tag-with-changelog @@ -0,0 +1,459 @@ +#!/usr/bin/env bash +# +# SPDX-License-Identifier: GPL-2.0-only + +# This script creates a list of commits between two releases, broken out into +# fairly inexact categories, based on the directories that files are in. If +# a commit touched anything in the path that is checked earlier, it's counted +# as being in that category. +# +# Don't run this in your current working tree, it checks out different versions +# and can lose things. + +# set -x # uncomment for debug + +if ! { cdup="$(git rev-parse --show-cdup 2>/dev/null)" && [ -z "${cdup}" ]; } +then + echo "ERROR: This is not the top directory of a git repo. Exiting." >&2 + exit 1 +fi + +# Verify the command line arguments +if [ "$1" == "--help" ] || [ -z "$1" ] || [ -z "$2" ]; then + echo + echo "Usage: $0 [release notes file]" + echo "Old version should be a tag (4.1), a branch (origin/4.1), or a commit id" + echo "New version must be a name of a new tag, this script fails if it exists" + echo "Logfile can be omitted or it can be a new file name. In the latter case" + echo "a copy of the full logfile (not the final tag description) with comments" + echo "removed is preserved." + echo "Example: \"$0 origin/4.1 4.2 rnotes.txt\"" + echo + echo "Note that the script starts at the commit AFTER the old version." + echo + exit 1 +else + OLD_GIT_VERSION="$1" + # This avoids detached HEAD after this script is run. If the tree is + # already in such state, the command below returns HEAD, which is tested + # below. + NEW_GIT_VERSION="$(git rev-parse --abbrev-ref HEAD)" + NEW_TAG_NAME="$2" + if [[ "$OLD_GIT_VERSION" = "HEAD" ]]; then + echo "Error: using HEAD as a reference doesn't work" >&2 + echo + exit 1 + fi + if [[ "$NEW_GIT_VERSION" = "HEAD" ]]; then + echo "Error: tree is in detached HEAD state" >&2 + echo + exit 1 + fi + + # Try to verify that the repo is clean before losing state. + if ! git diff --quiet HEAD; then + echo "ERROR: repo is not clean. Exiting." >&2 + exit 1 + fi + + TOTAL_COMMITS=$(git log --pretty=oneline \ + "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | wc -l) +fi + +TOP=$(pwd) + +if [ -n "$3" ]; then + LOGFILE="${TOP}/$3" +else + LOGFILE="${TOP}/relnotes.txt" +fi + +# Print and log the versions +log_versions() { + echo "Log of commit $1 to commit $2" + echo "# Log of commit $1 to commit $2" >> "$LOGFILE" + echo "Total commits: ${TOTAL_COMMITS}" + echo "# Total commits: ${TOTAL_COMMITS}" >> "$LOGFILE" + echo +} + +# Get the first commit id in the current tree +get_latest_commit_id() { +( + cd "$1" || exit 1 + git log -n 1 2>/dev/null | grep '^commit ' | head -1 | sed 's/commit //' | sed 's/ .*//' +) +} + +# Main get log function +_get_log() { + local oldver="$1" + local newver="$2" + local title="$3" + local paths="$4" + local keywords="$5" + + # Leave ${paths} unquoted in the git commands + # shellcheck disable=SC2086 + { \ + if [ -n "$paths" ]; then \ + git log --abbrev-commit --pretty=tformat:"- %s" \ + "${oldver}..${newver}" -- ${paths} \ + 2>/dev/null; \ + fi; \ + if [ -n "$keywords" ]; then \ + git log --abbrev-commit --pretty=tformat:"- %s" \ + "${oldver}..${newver}" 2>/dev/null \ + | grep -i "$keywords"; \ + fi \ + } | sort -t ' ' -k 2 | uniq +} + +# Output to a new log, then compare to the first logfile, and only output +# non duplicated lines to the final file. +get_log_dedupe() { + local title="$1" + local paths="$2" + local keywords="$3" + local log + local commits + + dedupe_tmpfile="$(mktemp "LOGFILE.XXXX")" + + log=$(_get_log "$OLD_GIT_VERSION" "$NEW_GIT_VERSION" \ + "$title" "$paths" "$keywords") + + echo "$log" > "$dedupe_tmpfile" + + log=$(grep -Fxv -f "$LOGFILE" "$dedupe_tmpfile") + commits=$(echo "$log" | wc -l) + + if [ -n "$log" ]; then + #echo "$title: $paths $keywords" >> "$LOGFILE" + printf "%s\n%s\n#\n" "##### $title ($commits commits) #####" \ + "$log" >> "$LOGFILE" + fi + + rm "$dedupe_tmpfile" +} + +# get logs for the submodules +get_log_submodule() { + local old_version="$1" + local new_version="$2" + local submodule_dir="$3" + local log + local commits + + printf "Submodule %s\n" "$submodule_dir" + printf "commit %s to commit %s\n\n" "$old_version" "$new_version" + + if ! ( + cd "${TOP}/$submodule_dir" || exit 1 + log="$(_get_log "$old_version" "$new_version" "$submodule_dir" "." "")" || exit 1 + commits=$(echo "$log" | wc -l) + + if [ -n "$log" ]; then + printf -- "- %s: Update from commit id %s to %s (%s commits)\n" "${submodule_dir}" "${old_version:0:10}" "${new_version:0:10}" "${commits}" >> "$LOGFILE" + ( + IFS=$'\n' + for l in $log; do + printf -- " %s\n" "$l" >> "$LOGFILE" + done + ) + fi + ); then + version_ctrl_c + fi +} + +# Make sure things get cleaned up if ctl-c is pressed while the old version +# is checked out and files are renamed. This can be a real mess to clean +# up manually. +version_ctrl_c() { + printf "\n Cleaning up and exiting.\n" >&2 + git checkout "$NEW_GIT_VERSION" > /dev/null 2>&1 + git submodule update --init --checkout > /dev/null 2>&1 + rm "$LOGFILE" + exit 1; +} + +# Start collecting data from the old and new revisions. +# This is relatively disruptive to the tree, so trap on ctl-c so that +# things can be put back to normal +trap version_ctrl_c SIGINT + +#check out old version and get information +echo "Finding old submodule versions..." >&2 +git checkout "$OLD_GIT_VERSION" > /dev/null 2>&1 +echo "Git version: $(git log --oneline -n 1)" +git submodule update --init --checkout > /dev/null 2>&1 +for module in $(git submodule --quiet foreach pwd); do + name="$(basename "$module" | sed 's/-/_/g')" + version="${name^^}_OLD_VERSION" + declare "$version"="$(get_latest_commit_id "$module")" +done +OLD_EDK2_GIT_VERSION=$(grep -A1 EDK2_TAG_OR_REV payloads/external/edk2/Kconfig.dasharo | tail -n1) +OLD_EDK2_GIT_VERSION=${OLD_EDK2_GIT_VERSION#*\"} +OLD_EDK2_GIT_VERSION=${OLD_EDK2_GIT_VERSION%\"} + +#check out new version and get information +printf -- "\nFinding new submodule versions...\n" >&2 +git checkout "$NEW_GIT_VERSION" > /dev/null 2>&1 +echo "Git version: $(git log --oneline -n 1)" +git submodule update --init --checkout > /dev/null 2>&1 + +for module in $(git submodule --quiet foreach pwd); do + name="$(basename "$module" | sed 's/-/_/g')" + version="${name^^}_NEW_VERSION" + declare "$version"="$(get_latest_commit_id "$module")" +done +NEW_EDK2_GIT_VERSION=$(grep -A1 EDK2_TAG_OR_REV payloads/external/edk2/Kconfig.dasharo | tail -n1) +NEW_EDK2_GIT_VERSION=${NEW_EDK2_GIT_VERSION#*\"} +NEW_EDK2_GIT_VERSION=${NEW_EDK2_GIT_VERSION%\"} + +git checkout "$NEW_GIT_VERSION" > /dev/null 2>&1 +git submodule update --init --checkout > /dev/null 2>&1 +trap "" SIGINT + +# Done collecting data from the old and new versions + +# Start outputting to logfile +echo "Generating release notes from version ${OLD_GIT_VERSION} to ${NEW_GIT_VERSION}" +echo; echo "Main repo" +echo "# This is full changelog based on commit subjects. Entries that are not" > "$LOGFILE" +echo "# related to the release can be removed. Lines starting with # are comments" >> "$LOGFILE" +echo "# and will not be included in the tag description." >> "$LOGFILE" +echo "#" >> "$LOGFILE" +echo "###################" >> "$LOGFILE" +echo "#### Main repo ####" >> "$LOGFILE" +echo "###################" >> "$LOGFILE" +log_versions "$(git log --pretty=%H \ + "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | tail -1)" \ + "$(git log --pretty=%H \ + "${OLD_GIT_VERSION}..${NEW_GIT_VERSION}" 2>/dev/null | head -1 )" +echo "#" >> "$LOGFILE" + +### SPECIFIC AREAS FOR RELEASE ### +get_log_dedupe "Documentation" "Documentation README" + +get_log_dedupe "cleanup" "" "add missing\|fix typo\|clean up\|spelling\|Use tabs\|space [around\|before]\|code formatting\|commented code\|code cleanup\|capitalize\|[unnecessary\|unneeded\|trailing] whitespace\|checkpatch\|remove [unused\|dead\|unneeded\|duplicated\|not used]\|[transition away from\|get rid of\|don't use] device_t" + +get_log_dedupe "ACPI Changes" "" "ASL 2.0 syntax" + +get_log_dedupe "Dasharo Hardkernel Odroid H4" "src/mainboard/hardkernel/odroid-h4" +get_log_dedupe "Dasharo MSI PRO Z690-A" "src/mainboard/msi/ms7d25" +get_log_dedupe "Dasharo MSI PRO Z790-P" "src/mainboard/msi/ms7e06" +get_log_dedupe "Dasharo NovaCustom" "src/mainboard/novacustom" "novacustom" +get_log_dedupe "Dasharo PC Engines" "src/mainboard/pcengines/apu2" "apu2" +get_log_dedupe "Dasharo Protectli" "src/mainboard/protectli" "protectli" + +get_log_dedupe "Google Kahlee / AMD Gardenia" "src/mainboard/google/kahlee src/mainboard/amd/gardenia" "kahlee\|gardenia" +get_log_dedupe "AMD Stoney Ridge" "src/soc/amd/stoneyridge" "stoney" + +get_log_dedupe "Google Zork / AMD Mandolin / AMD Bilby" "src/mainboard/amd/mandolin src/mainboard/google/zork src/mainboard/amd/bilby" "mandolin\|zork\|bilby" +get_log_dedupe "AMD Picasso" "src/soc/amd/picasso" "picasso" + +get_log_dedupe "Google Guybrush / AMD Majolica" "src/mainboard/google/guybrush src/mainboard/amd/majolica" "majolica\|guybrush" +get_log_dedupe "AMD cezanne" "src/soc/amd/cezanne" "cezanne" + +get_log_dedupe "AMD chausie / Google Skyrim" "src/mainboard/amd/chausie src/mainboard/google/skyrim" "chausie\|skyrim" +get_log_dedupe "AMD sabrina" "src/soc/amd/sabrina" "sabrina" + +get_log_dedupe "Google Brya / Intel adlrvp" "src/mainboard/intel/adlrvp src/mainboard/google/brya" "brya\|adlrvp" +get_log_dedupe "Intel Alder Lake" "src/soc/intel/alderlake" "alderlake\|adl\|alder lake" + +get_log_dedupe "intel Elkhart Lake" "src/soc/intel/elkhartlake" "elkhartlake\|ehl\|elkhart lake" + +get_log_dedupe "Google Dedede" "src/mainboard/google/dedede" "dedede" +get_log_dedupe "intel Jasper Lake" "src/soc/intel/jasperlake" "jasperlake\|jsl\|jasper lake" + +get_log_dedupe "Intel Tiger Lake" "src/soc/intel/tigerlake" "tigerlake\|tgl\|tiger lake" + +get_log_dedupe "Google Hatch" "src/mainboard/google/hatch" "hatch" +get_log_dedupe "Intel Comet Lake" "src/soc/intel/cometlake" "cometlake\|cml\|comet lake" + +get_log_dedupe "Google Eve / Poppy / Fizz / Soraka / Nautilus / Intel KblRvp" "src/mainboard/google/eve src/mainboard/google/poppy src/mainboard/google/fizz src/mainboard/intel/kblrvp" "eve[ :]\|poppy\|fizz\|soraka\|nautilus\|kblrvp" + +get_log_dedupe "Intel Kunimitsu / Google Chell / Lars / Glados" "src/mainboard/google/lars src/mainboard/google/chell src/mainboard/google/glados src/mainboard/intel/kunimitsu" "chell\|lars\|kunimitsu" +get_log_dedupe "Purism SKL" "src/mainboard/purism/librem_skl" "librem13v2\|librem_skl" +get_log_dedupe "Intel Skylake / Kabylake" "src/soc/intel/skylake" "skylake\|sky.lake\|kabylake\|kaby.lake" + +get_log_dedupe "Intel Glkrvp / Google Octopus / Bip / Yorp" "src/mainboard/google/octopus src/mainboard/intel/glkrvp" "octopus\|glkrvp|\bip\|yorp" + +get_log_dedupe "Google Cyan / Intel Strago" "src/mainboard/google/cyan src/mainboard/intel/strago" "cyan\|strago" +get_log_dedupe "Intel Braswell" "src/soc/intel/braswell" "braswell" + +get_log_dedupe "Google Kevin / Gru / Bob / Scarlet / Nefario" "src/mainboard/google/gru" "kevin\|gru[^b]" +get_log_dedupe "Rockchip rk3399" "src/soc/rockchip/rk3399" "rk3399" + +get_log_dedupe "Google Reef / Pyro / Sand / Snappy / Nasher" "src/mainboard/google/reef" "reef\|pyro\|sand[ :]\|snappy\|nasher" +#get_log_dedupe "Intel apollolake_rvp leafhill minnow3" "src/mainboard/intel/apollolake_rvp src/mainboard/intel/leafhill src/mainboard/intel/minnow3" "apollolake_rvp\|leafhill\|minnow3" +get_log_dedupe "Siemens mc_apl1" "src/mainboard/siemens/mc_apl1" "mc_apl1" +get_log_dedupe "Intel Apollolake/ Geminilake" "src/soc/intel/apollolake" "apollolake\|apollo.lake\|geminilake\|gemini.lake\|apl\|glk" + +get_log_dedupe "Google Zoombini / Intel cannonlake_rvp" "src/mainboard/google/zoombini src/mainboard/intel/cannonlake_rvp" "zoombini\|cannonlake_rvp" +get_log_dedupe "Intel CannonLake" "src/soc/intel/cannonlake src/mainboard/intel/cannonlake_rvp" "cannonlake" + +get_log_dedupe "Google Kuki" "src/mainboard/google/kukui" "kukui" +get_log_dedupe "mediatek/mt8183" "src/soc/mediatek/mt8183" "mt8183" + +get_log_dedupe "Google Cheza" "src/mainboard/google/cheza" "cheza" +get_log_dedupe "Qualcomm sdm845" "src/soc/qualcomm/sdm845" "sdm845" + +get_log_dedupe "Prodrive Hermes / Google Sarien / Intel coffeelake_rvp" "src/mainboard/intel/coffeelake_rvp src/mainboard/google/sarien src/mainboard/prodrive/hermes" +get_log_dedupe "Intel Coffeelake" "soc/intel/coffeelake" + +get_log_dedupe "Cavium" "src/soc/cavium src/mainboard/cavium src/mainboard/opencellular/elgon " +get_log_dedupe "Scaleway Tagada" "src/mainboard/scaleway/tagada" "tagada" + +get_log_dedupe "Intel Galileo" "src/mainboard/intel/galileo" "galileo" +get_log_dedupe "Intel Quark" "src/soc/intel/quark" "quark" + +get_log_dedupe "Intel Baytrail" "src/soc/intel/baytrail" "baytrail" +get_log_dedupe "Google Gale / Qualcomm QX ipq40xx" "src/mainboard/google/gale src/soc/qualcomm/ipq40xx" "gale\|ipq40" +get_log_dedupe "Google Rotor / Marvell Mvmap2315" "src/soc/marvell/mvmap2315 src/mainboard/google/rotor" "marvell\|mvmap\|rotor" + +get_log_dedupe "Gigabyte ga-g41m-es2l" "src/mainboard/gigabyte/ga-g41m-es2l" "es2l" +get_log_dedupe "Intel x4x northbridge / LGA775" "src/northbridge/intel/x4x src/cpu/intel/socket_LGA775" "x4x\|lga775" + +get_log_dedupe "Intel Haswell / Broadwell" "src/northbridge/haswell" "haswell" +get_log_dedupe "Intel Lynxpoint" "src/southbridge/intel/lynxpoint" "lynxpoint" + +get_log_dedupe "Intel Sandybridge / Ivybridge" "src/southbridge/intel/bd82x6x src/southbridge/intel/fsp_bd82x6x src/northbridge/intel/sandybridge src/northbridge/intel/fsp_sandybridge src/cpu/intel/fsp_model_206ax src/cpu/intel/model_206ax" "sandybridge\|ivybridge\|bd82x6x" + +get_log_dedupe "Google Herbrine" "src/mainboard/google/herobrine" "herobrine" +get_log_dedupe "Qualcomm SC7280" "src/soc/qualcomm/sc2780" "sc2780" + +get_log_dedupe "Google Corsola" "src/mainboard/google/corsola" "corsola" +get_log_dedupe "Mediatek MT8186" "src/soc/mediatek/mt8186" "mt8186" + +get_log_dedupe "Intel Common" "src/soc/intel/common src/southbridge/intel/common src/northbridge/intel/common" "" +get_log_dedupe "Amd Common" "src/soc/amd/common src/southbridge/amd/common" "" + +get_log_dedupe "Nvidia" "src/southbridge/nvidia" "" +get_log_dedupe "Via" "src/northbridge/via src/southbridge/via" "" +get_log_dedupe "Broadcom" "src/southbridge/broadcom" "" +get_log_dedupe "Qualcomm" "src/soc/qualcomm" "" +get_log_dedupe "Mediatek" "src/soc/mediatek" "" + +get_log_dedupe "Intel vendorcode / FSP" "src/drivers/intel/fsp* src/vendorcode/intel" "" +get_log_dedupe "AMD vendorcode / AGESA / PI" "src/vendorcode/amd" "agesa\|binarypi" +get_log_dedupe "Google vendorcode" "src/vendorcode/google" +get_log_dedupe "Cavium vendorcode" "src/vendorcode/cavium" + +get_log_dedupe "Security" "src/drivers/i2c/tpm src/security" "tpm" +get_log_dedupe "Vboot" "src/vboot" "vboot" + + +### GENERAL AREAS FOR RELEASE ### +# shellcheck disable=SC2013 +{ + +get_log_dedupe "X86 intel" \ + "src/cpu/intel src/soc/intel src/northbridge/intel \ + src/southbridge/intel src/include/intel src/drivers/intel" + +get_log_dedupe "X86 AMD" \ + "src/cpu/amd src/northbridge/amd src/southbridge/amd src/include/amd src/soc/amd" \ + "agesa\|binarypi\|binary.pi" + +get_log_dedupe "X86 common" \ + "src/arch/x86 src/cpu/x86 src/include/x86 src/include/pc80" + +get_log_dedupe "ARM" \ + "$(for codedir in $(grep -rl "_ARM" --include=Kconfig | \ + grep -v 'src/mainboard\|payloads/\|drivers/\|vendorcode/\|console' ); \ + do dirname "$codedir"; done | grep -v '^src$')" + +get_log_dedupe "RISC-V" \ + "$(for codedir in $(grep -rl "_RISCV" --include=Kconfig | grep -v 'payloads/\|drivers/\|vendorcode/\|console' ); do dirname "$codedir"; done | grep -v '^src$')" \ + "riscv\|risc-v\|lowrisc\|sifive" +} + +get_log_dedupe "Google Mainboards" "src/mainboard/google" +get_log_dedupe "Intel Mainboards" "src/mainboard/intel" +get_log_dedupe "AMD Mainboards" "src/mainboard/amd" +get_log_dedupe "Mainboards" "src/mainboard/" + +# Next, print all the rest of the specific areas +get_log_dedupe "ACPI" "src/acpi/" +get_log_dedupe "Console" "src/console src/include/console" +get_log_dedupe "SuperIO" "src/superio src/include/superio" +get_log_dedupe "EC" "src/ec" +get_log_dedupe "Drivers" "src/drivers" +get_log_dedupe "Devices" "src/device src/include/device" + +# 5th, print the generic areas - This goes late so that the specific +# area changes will catch any commits in these areas first. +get_log_dedupe "Toolchain" "util/crossgcc" +get_log_dedupe "cbfstool" "util/cbfstool" +get_log_dedupe "Lint tools" "util/lint" +get_log_dedupe "Lib" "src/lib" +get_log_dedupe "Commonlib" "src/commonlib" +get_log_dedupe "Include" "src/include" +get_log_dedupe "Utilities" "util" +get_log_dedupe "Payloads" "payloads" +get_log_dedupe "Vendorcode" "src/vendorcode" + +# Then look at areas that are usually outside the mainboards and architectures +get_log_dedupe "Build system" \ + "Makefile Makefile.mk toolchain.mk src/Kconfig src/cpu/Makefile.mk build.sh" + +get_log_dedupe "Submodules" "3rdparty util/nvidia/cbootimage" + +get_log_dedupe "Maintainers" "MAINTAINERS" "" + +# Finally, get anything that was missed above +get_log_dedupe "MISC" "." + +# Log submodules +echo "####################" >> "$LOGFILE" +echo "#### Submodules ####" >> "$LOGFILE" +echo "####################" >> "$LOGFILE" +for module in $(git submodule --quiet foreach pwd); do + name=$(basename "$module") + module="$(realpath "${module}")" + workingdir="$(realpath "${PWD}")" + # shellcheck disable=SC2001 + path=${module#"$workingdir"} + old_version=$(echo "${name^^}_OLD_VERSION" | sed 's/-/_/g') + new_version=$(echo "${name^^}_NEW_VERSION" | sed 's/-/_/g') + get_log_submodule "${!old_version}" "${!new_version}" "${path}" +done + +echo "##############" >> "$LOGFILE" +echo "#### EDK2 ####" >> "$LOGFILE" +echo "##############" >> "$LOGFILE" +# Hardcoded, probably won't ever change +URL="https://github.com/Dasharo/edk2" +# This is the first digest from common Kconfig option. While it could be pointed +# to by previous release (in which case the changelog would be complete), it +# isn't trivial to differentiate between such case and use as placeholder value. +PREHISTORY="f0459dff1425c0c02d0736de5737eb23a1b671ec" + +if [ -z "$OLD_EDK2_GIT_VERSION" ]; then + echo "# Old EDK2 version couldn't be obtained, changelog may be incomplete!" >> "$LOGFILE" + echo "# Commits older than ${PREHISTORY:0:10} won't be shown" >> "$LOGFILE" + OLD_EDK2_GIT_VERSION="$PREHISTORY" +fi + +git clone --reference-if-able payloads/external/edk2/workspace/Dasharo/ --bare "$URL" edk2 || version_ctrl_c +get_log_submodule "$OLD_EDK2_GIT_VERSION" "$NEW_EDK2_GIT_VERSION" "edk2" +rm -rf edk2 + +# Create signed tag, use LOGFILE as message, open editor, or fail if tag exists +git tag -s -F "$LOGFILE" -e "$NEW_TAG_NAME" || version_ctrl_c +echo "New tag has been created. To push it:" +echo +echo " git push origin tag $NEW_TAG_NAME" +echo + +# If log file name was given, strip comments, otherwise remove temporary file +if [ -n "$3" ]; then + sed -i "/^#/d" "$LOGFILE" +else + rm -f "$LOGFILE" +fi + +printf "Done.\n" diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index b381ab27767..5a456cf88b7 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -79,6 +79,11 @@ printf "/* timesource: %s */\n" "${TIMESOURCE}" printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "${DATE}" printf "#define COREBOOT_ORIGIN_GIT_REVISION \"%s\"\n" "${GITREV}" +printf "#define DASHARO_VERSION \"%s\"\n" "$DASHARO_VERSION" +printf "#define DASHARO_MAJOR_VERSION %d\\n" "$DASHARO_MAJOR_VERSION" +printf "#define DASHARO_MINOR_VERSION %d\\n" "$DASHARO_MINOR_VERSION" +printf "#define DASHARO_PATCH_VERSION %d\\n" "$DASHARO_PATCH_VERSION" + printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "${COREBOOT_EXTRA_VERSION}" printf "#define COREBOOT_MAJOR_VERSION %s\n" "${MAJOR_VER:-0}" printf "#define COREBOOT_MINOR_VERSION %s\n" "${MINOR_VER:-0}" diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index ace05e22652..cf726feacae 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -794,19 +794,220 @@ static void dump_fcba(const struct fcba *fcba, const struct fpsba *fpsba) } } +static int ifd2_platform_get_hap_location(const struct fpsba *fpsba) +{ + switch (platform) { + case PLATFORM_SKLKBL: + /* No exceptions, always strap 0 */ + return 0; + case PLATFORM_IFD2: + printf("To change the AltMeDisable/HAP bit please provide the platform as parameter\n"); + return -1; + case PLATFORM_CNL: + /* + * This gets little tricky here. + * 1. CNL/CFL/CML-LP strap 106 (FPSBA + 0x70), but + * FSPBA + 0x70 bits 15:4 set to 0x1b + * FPSBA + 0x80 strap has configurable bits, + * FPSBA + 0x82/0x83 bytes are set to zeros, + * FPSBA + 0x00 is set to zeros, + * 2. CML-V strap 0 (FPSBA + 0x00) with bits 15:2 set to 0x00, but + * FSPBA + 0x00 bits 15:2 must be set to 0, + * FPSBA + 0x00 bits 23:22 must be set to 0x2, + * FPSBA + 0x70 is set to all zeros, + * FPSBA + 0x80 byte has configurable bits, + * FPSBA + 0x81/0x82 bytes are set to zeros. + * 3. CML-H/S strap 123 (FPSBA + 0x80), but + * FSPBA + 0x80 bits 15:4 set to 0x1b + * FPSBA + 0x00/0x70 is set to all zeros. + * + * So we do like this: + * + * 1. Prioritize CML-V detection as strap 0 cannot be all zeros. + * 2. Then heck if FSPBA + 0x70 is zero for CML-H/S, CNL/CFL/CML-LP + * cannot have FPSBA + 0x70 all zeros. + */ + if (fpsba->pchstrp[0] != 0) { + /* CML-V, one more safetycheck ot exclude other SKUs */ + if (fpsba->pchstrp[0x70 / 4] == 0) { + printf("Detected Comet Lake V platform flash descriptor\n"); + return 0; + } + } else { + /* Do safety check for CML-H/S to be sure */ + if (fpsba->pchstrp[0x70 / 4] == 0) { + printf("Detected Comet Lake H/S platform flash descriptor\n"); + return 0x80 / 4; + } + /* Do safety check for CNL/CFL/CML-LP to be sure */ + if (((fpsba->pchstrp[0x70 / 4] >> 4) & 0xfff) == 0x1b) { + printf("Detected Cannon Lake/Coffee Lake/Comet Lake LP " + "platform flash descriptor\n"); + return 0x70 / 4; + } + } + printf("Unusual Cannon Lake/Coffee Lake/Comet Lake flash descriptor detected\n" + "Not modifying flash descriptor\n"); + return -1; + case PLATFORM_TGL: + /* + * RKL-H/TGL-H strap 141 (FPSBA + 0x94), but + * FPSBA + 0x94 bits 8:1 set to 0x18. + * FPSBA + 0x7c must be zero. + * TGL-LP has non-zero FPSBA + 0x7c. + */ + if ((((fpsba->pchstrp[0x94 / 4] >> 1) & 0xff) == 0x18) && + (fpsba->pchstrp[0x7c / 4] == 0)) { + printf("Detected Rocket Lake H/Tiger Lake H platform " + "flash descriptor\n"); + return 0x94 / 4; + } + /* + * TGL-LP strap 114 (FPSBA + 0x7c), but + * FSPBA + 0x7c bits 8:1 set to 0x18 + * FPSBA + 0x92/0x93/0x94/0x95 must be all zeros. + * TGL-H has non-zero FPSBA + 0x94/0x95. + */ + if ((((fpsba->pchstrp[0x7c / 4] >> 1) & 0xff) == 0x18) && + (((fpsba->pchstrp[0x94 / 4] >> 16) & 0xffff) == 0)) { + printf("Detected Tiger Lake LP platform flash descriptor\n"); + return 0x7c / 4; + } + + printf("Unusual Tiger Lake flash descriptor detected\n" + "Not modifying flash descriptor\n"); + return -1; + case PLATFORM_ADL: + /* + * This gets little tricky here. + * 1. RPL-P/ADL-N/P strap 114 (FSPBA + 0x7c), but + * FPSBA + 0x7c bits 8:1 set to 0x18, + * FPSBA + 0xdc strap has configurable bits, + * FPSBA + 0xd0 must be set to 0x00000300. + * 2. ADL-S B0 step/RPL-S strap 193 (FSPBA + 0xdc), but + * FPSBA + 0xdc bits 8:1 set to 0x58, + * FPSBA + 0x7c strap has configurable bits, + * FPSBA + 0xd0 must be set to 0x10081008. + * 3. ADL-S A0 step strap 183 (FSPBA + 0xd0), but + * FPSBA + 0xd0 bits 8:1 set to 0x58, + * FPSBA + 0x7c/0xdc straps have configurable bits, however + * analogically to 0xdc vs. 0xd0, the FPSBA + (0xd0 - 0x0c) + * must be 0x10081008. + * + * So we do like this: + * + * 1. Prioritize ADL-S detection by checking 0xd0/0xdc bits 8:1 + * and 0xd0/0xc4 straps are set to 0x10081008. + * 2. ADL-S and ADL-N/P is mutually exclusive due to 0xd0 + * reserved values. SO 0xd0 can be used to distinguish all + * SKUs. + */ + if (fpsba->pchstrp[0xd0 / 4] == 0x10081008) { + /* ADL-S B0 step/RPL-S, do safety check to be sure */ + if (((fpsba->pchstrp[0xdc / 4] >> 1) & 0xff) == 0x58) { + printf("Detected Raptor Lake S/Alder Lake S B0" + " step platform flash descriptor\n"); + return 0xdc / 4; + } + } else if (fpsba->pchstrp[0xd0 / 4] == 0x00000300) { + /* RPL-P/ADL-N/P, do safety check to be sure */ + if (((fpsba->pchstrp[0x7c / 4] >> 1) & 0xff) == 0x18) { + printf("Detected Raptor Lake P/Alder Lake P/N" + " platform flash descriptor\n"); + return 0x7c / 4; + } + } else if (((fpsba->pchstrp[0xd0 / 4] >> 1) & 0xff) == 0x58) { + /* ADL-S A0 step, do safety check to be sure */ + if (fpsba->pchstrp[0xc4 / 4] == 0x10081008) { + printf("Detected Alder Lake S A0 step platform" + " flash descriptor\n"); + return 0xd0 / 4; + } + } + printf("Unusual Alder Lake flash descriptor detected\n" + "Not modifying flash descriptor\n"); + return -1; + case PLATFORM_MTL: + /* MTL-U/H strap 225 (FPSBA + 0x11c) */ + return 0x11c / 4; + case PLATFORM_ICL: + /* + * ICX-D strap 56 (FPSBA + 0xe0), unconfirmed. + * ICX-D FPSBA + 0x78 must be zero. + */ + if ((((fpsba->pchstrp[0xe0 / 4] >> 1) & 0xff) == 0x98) && + (fpsba->pchstrp[0x78 / 4] == 0)) { + printf("Detected Ice Lake D platform flash descriptor\n"); + return 0xe0 / 4; + } + /* + * ICL-LP strap 113 (FPSBA + 0x78), but + * FSPBA + 0x78 bits 9:1 set to 0x98. + * FPSBA + 0xe0 must be 0x68070000. + */ + if ((((fpsba->pchstrp[0x78 / 4] >> 1) & 0xff) == 0x98) && + (fpsba->pchstrp[0xe0 / 4] == 0x68070000)) { + printf("Detected Ice Lake LP platform flash descriptor\n"); + return 0x94 / 4; + } + + printf("Unusual Ice Lake flash descriptor detected\n" + "Not modifying flash descriptor\n"); + return -1; + case PLATFORM_LBG: + /* LBG strap 53 (FPSBA + 0xd4) */ + return 0xd4 / 4; + case PLATFORM_DNV: + /* DNV strap 14 (FPSBA + 0x38) */ + return 0x38 / 4; + case PLATFORM_APL: + case PLATFORM_GLK: + /* + * Strap 10 (FPSBA + 0x2c), but can be only set through SMIP? + * Couldn't get it to work on GLK. + */ + return 0x2c / 4; + case PLATFORM_JSL: + /* JSL strap 113 (FSPBA + 0x68) */ + return 0x68 / 4; + case PLATFORM_EHL: + /* EHL strap 122 (FSPBA + 0x84) */ + return 0x84 / 4; + default: + printf("HAP bit location unknown for selected platform\n" + "Not modifying flash descriptor\n"); + return -1; + } +} + static void dump_fpsba(const struct fdbar *fdb, const struct fpsba *fpsba) { unsigned int i; /* SoC Straps, aka PSL, aka ISL */ unsigned int SS = (fdb->flmap1 >> 24) & 0xff; + int loc; + bool hap_state; printf("Found PCH Strap Section\n"); for (i = 0; i < SS; i++) printf("PCHSTRP%-3u: 0x%08x\n", i, fpsba->pchstrp[i]); if (ifd_version >= IFD_VERSION_2) { + loc = ifd2_platform_get_hap_location(fpsba); + + if (loc == -1) { + printf("\n"); + return; + } + + /* Special case for APL/GLK */ + if (platform == PLATFORM_APL || platform == PLATFORM_GLK) + hap_state = !!(fpsba->pchstrp[loc] & (1 << 7)); + else + hap_state = !!(fpsba->pchstrp[loc] & (1 << 16)); + printf("HAP bit is %sset\n", - fpsba->pchstrp[0] & (1 << 16) ? "" : "not "); + hap_state ? "" : "not "); } else if (chipset >= CHIPSET_ICH8 && chipset <= CHIPSET_ICH10) { printf("ICH_MeDisable bit is %sset\n", fpsba->pchstrp[0] & 1 ? "" : "not "); @@ -1890,14 +2091,29 @@ static void set_pchstrap(struct fpsba *fpsba, const struct fdbar *fdb, const int /* Set the AltMeDisable (or HAP for >= IFD_VERSION_2) */ static void fpsba_set_altmedisable(struct fpsba *fpsba, struct fmsba *fmsba, bool altmedisable) { + int loc; + if (ifd_version >= IFD_VERSION_2) { + loc = ifd2_platform_get_hap_location((const struct fpsba *)fpsba); + + if (loc == -1) + return; + printf("%sting the HAP bit to %s Intel ME...\n", altmedisable ? "Set" : "Unset", altmedisable ? "disable" : "enable"); - if (altmedisable) - fpsba->pchstrp[0] |= (1 << 16); - else - fpsba->pchstrp[0] &= ~(1 << 16); + /* Special case for APL/GLK */ + if (platform == PLATFORM_APL || platform == PLATFORM_GLK) { + if (altmedisable) + fpsba->pchstrp[loc] |= (1 << 7); + else + fpsba->pchstrp[loc] &= ~(1 << 7); + } else { + if (altmedisable) + fpsba->pchstrp[loc] |= (1 << 16); + else + fpsba->pchstrp[loc] &= ~(1 << 16); + } } else { if (chipset >= CHIPSET_ICH8 && chipset <= CHIPSET_ICH10) { printf("%sting the ICH_MeDisable, MCH_MeDisable, " diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 21e40c6aa46..e7566c9b618 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -1347,8 +1347,8 @@ sub print_wholeconfig { sub check_if_file_referenced { my $filename = $File::Find::name; if ( ( $filename =~ /Kconfig/ ) - && ( !$filename =~ /\.orig$/ ) - && ( !$filename =~ /~$/ ) + && ( !($filename =~ /\.orig$/) ) + && ( !($filename =~ /~$/) ) && ( !exists $loaded_files{$filename} ) ) { show_warning("'$filename' is never referenced"); diff --git a/util/msi/Makefile.mk b/util/msi/Makefile.mk new file mode 100644 index 00000000000..6079cbf24d8 --- /dev/null +++ b/util/msi/Makefile.mk @@ -0,0 +1,39 @@ +TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h + +MSIROMHOLETOOL:= $(objutil)/msi/romholetool + +$(MSIROMHOLETOOL): $(dir)/romholetool/romholetool.c + printf " HOSTCC Creating MSI ROMHOLE tool\n" + mkdir -p $(objutil)/msi + $(HOSTCC) $(TOOLCPPFLAGS) $< -o $@ + +ifeq ($(CONFIG_VENDOR_MSI)$(CONFIG_BOARD_HAS_MSI_ROMHOLE),yy) + +ifeq ($(CONFIG_MSI_ROMHOLE_IN_CBFS),y) + +$(obj)/mainboard/$(MAINBOARDDIR)/romhole.bin: $(MSIROMHOLETOOL) + printf " TOOL Creating MSI ROMHOLE blob\n" + $(MSIROMHOLETOOL) -a $(CONFIG_MSI_ROMHOLE_ADDRESS_IN_CBFS) \ + -s $(CONFIG_MSI_ROMHOLE_SIZE_IN_CBFS) -o $@ + + +cbfs-files-y += msi_romhole.bin + +msi_romhole.bin-file := $(obj)/mainboard/$(MAINBOARDDIR)/romhole.bin +msi_romhole.bin-type := raw +msi_romhole.bin-compression := none +msi_romhole.bin-position := $(CONFIG_MSI_ROMHOLE_ADDRESS_IN_CBFS) + +else + +$(obj)/mainboard/$(MAINBOARDDIR)/romhole.bin: $(MSIROMHOLETOOL) $(obj)/fmap_config.h + printf " TOOL Creating MSI ROMHOLE blob\n" + $(MSIROMHOLETOOL) -l $(obj)/fmap_config.h -o $@ + +build_complete:: $(obj)/mainboard/$(MAINBOARDDIR)/romhole.bin + @printf " WRITE MSI ROMHOLE\n" + $(CBFSTOOL) $(obj)/coreboot.rom write -u -i 255 -r ROMHOLE -f $< + +endif + +endif diff --git a/util/msi/description.md b/util/msi/description.md new file mode 100644 index 00000000000..46305865bd4 --- /dev/null +++ b/util/msi/description.md @@ -0,0 +1,3 @@ +Tools for MSI platforms + +* _romholetool_ - Generates default MSI ROMHOLE blob for BIOS updates `C` diff --git a/util/msi/romholetool/romholetool.c b/util/msi/romholetool/romholetool.c new file mode 100644 index 00000000000..4fa8a2341ff --- /dev/null +++ b/util/msi/romholetool/romholetool.c @@ -0,0 +1,469 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MiB (1024*1024) + +// TODO: take it as an input +#define ROMHOLE_MAGIC 0x10012501 +#define NUM_PWD_ENTRIES 2 +#define PWD_SIZE 40 +#define NUM_GD_ENTRIES 8 +#define GD_SIZE 48 +#define NUM_US_ENTRIES 8 +#define US_SIZE 0x3851 +#define TYPE2_SIZE 256 +#define FTB_SIZE 105 +#define FIB_SIZE 512 +#define FDP_SIZE 1024 +#define BUV_SIZE 1024 +#define NUM_VOLUMES 7 + +struct uuid_structure { + uint8_t magic0[4]; // always sSiD + uint16_t length; // structure length, always 0x1a + uint8_t magic1[3]; // awlays $uD + uint8_t space; // always 0x1 + uint8_t uuid[16]; // SMBIOS type 1 UUID +} __packed; + +struct pwd_entry { + uint8_t magic[3]; // always $s$ + uint8_t number; // ordinal number + uint8_t length; // length of pwd + uint8_t pwd[PWD_SIZE]; // password? +} __packed; + +struct pwd_structure { + uint8_t magic[4]; // always spWd + uint16_t length; // structure length + struct pwd_entry entries[NUM_PWD_ENTRIES]; +} __packed; + +struct gd_entry { + uint8_t magic[3]; // always $gD + uint8_t number; // ordinal number + uint16_t length; // length of gd + uint8_t gd[GD_SIZE]; // global data? +} __packed; + +struct gpdt_structure { + uint8_t magic[4]; // always gPdT + uint16_t length; // structure length + uint8_t num_entries; // number of entries + uint8_t space; // awlays zero + struct gd_entry entries[NUM_GD_ENTRIES]; +} __packed; + +struct us_entry { + uint8_t magic[3]; // always $uS + uint8_t number; // ordinal number + uint16_t length; // length of us + uint8_t us[US_SIZE]; // user data? +} __packed; + +struct ucsc_structure { + uint8_t magic[4]; // always uCsC + uint16_t length; // structure length + struct us_entry entries[NUM_US_ENTRIES]; +} __packed; + +struct type2_rw { + uint8_t magic0[4]; // always t2Rw + uint16_t length; // structure length + uint8_t magic1[3]; // always $tW + uint8_t space; // always 0x1 + uint8_t smbios_type2[TYPE2_SIZE]; // SMBIOS type2 table +} __packed; + +struct ftb_structure { + uint8_t magic0[4]; // always $FTB + uint16_t length; // structure length + uint8_t magic1[4]; // always $DIB + uint16_t space0; // always 0x2 + uint16_t size; // size of data field, always 105 + uint16_t space1; // always 0x0 + uint8_t magic2[4]; // always MFTD + uint8_t data[FTB_SIZE]; // default 0xfe +} __packed; + +struct fib_structure { + uint8_t magic0[4]; // always $FIB + uint16_t length; // structure length + uint16_t size; // size of data field, always 512 + uint8_t magic1[4]; // always $MFX + uint8_t data[FIB_SIZE]; // default 0xfa +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P since A.40/1.40 */ +struct fdp_structure { + uint8_t magic0[4]; // always $FDP + uint16_t length; // structure length + uint8_t magic1[3]; // always $Fd + uint8_t number; // always 0x1 + uint8_t data[FDP_SIZE]; // default 0xff +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P A.40/1.40 */ +struct buv_structure { + uint8_t magic0[4]; // always $BuV + uint16_t length; // structure length + uint8_t magic1[3]; // always $Bv + uint8_t number; // always 0x1 + uint8_t data[BUV_SIZE]; // default 0xff +} __packed; + +struct volume_entry { + uint8_t number; // ordinal number in ascii + uint32_t address; // volume base address + uint32_t size; // volume size + uint8_t space; // always 0xff +} __packed; + +struct ris_structure { + uint8_t magic0[4]; // always $RiS + uint16_t length; // structure length + uint8_t magic1[4]; // always $RiT + /* Array below keep the addresses and sizes of UEFI Firmware Volumes */ + struct volume_entry volumes[NUM_VOLUMES]; +} __packed; + +/* Place the following struct in the ROMHOLE flash region with 64K/128K alignment */ +struct msi_romhole { + uint32_t magic0; // 0x10012501 + uint16_t length; // length of the structure + char magic1[4]; // always SYSD + uint32_t address; // romhole address in flash + uint32_t size; // romhole total size + uint8_t pad0[48]; // always 0xff + struct uuid_structure uuid; + struct pwd_structure pwd; + struct gpdt_structure gpdt; + struct ucsc_structure ucsc; + struct type2_rw t2rw; + struct ftb_structure ftb; + struct fib_structure fib; + struct fdp_structure fdp; + struct buv_structure buv; + struct ris_structure ris; + // the rest is padded with 0xff by cbfstool +} __packed; + +static const char *optstring = "i:a:s:l:o:h"; + +static struct option long_options[] = { + {"layout", required_argument, 0, 'l' }, + {"address", required_argument, 0, 'a' }, + {"size", required_argument, 0, 's' }, + {"output", required_argument, 0, 'o' }, + {"help", no_argument, 0, 'h' }, +}; + +static void usage(void) +{ + printf("romholetool: Create ROMHOLE for MSI BIOS updates compatibility\n"); + printf("Usage: romholetool [options] -i build.h -l fmap_config.h -o \n"); + printf(" romholetool [options] -i build.h -a 0xff7c0000 -s 0x20000 -o \n"); + printf("-l | --layout The fmap_config.h file to parse\n"); + printf("-a | --address The address of ROMHOLE in CBFS\n"); + printf("-s | --size The size of ROMHOLE in CBFS\n"); + printf("-o | --output The file to generate\n"); + printf("-h | --help Print this help\n"); +} + +static int bcd2int(int hex) +{ + if (hex > 0xff) + return -1; + return ((hex & 0xF0) >> 4) * 10 + (hex & 0x0F); +} + +static char *get_line(char *fn, char *match) +{ + ssize_t read; + char *line = NULL; + char *ret = NULL; + size_t len = 0; + + FILE *fp = fopen(fn, "r"); + if (fp == NULL) { + fprintf(stderr, "E: Couldn't open file '%s'\n", fn); + return NULL; + } + + while ((read = getline(&line, &len, fp)) != -1) { + if (strstr(line, match) != NULL) { + ret = strdup(strstr(line, match) + strlen(match)); + break; + } + } + + if (!ret) + fprintf(stderr, "E: %s not found in %s\n", match, fn); + + fclose(fp); + return ret; +} + +static int get_line_as_int(char *fn, char *match, int bcd) +{ + int ret = -1; + char *s = get_line(fn, match); + if (s && strlen(s) > 0) { + char *endptr; + ret = strtol(s, &endptr, 0); + if (*endptr != '\0' && *endptr != '\n') { + fprintf(stderr, "E: Couldn't parse number for key '%s'\n", match); + return -1; + } + if (bcd) + ret = bcd2int(ret); + free(s); + } else { + fprintf(stderr, "E: Got invalid line for key '%s'\n", match); + } + + return ret; +} + +int main(int argc, char **argv) +{ + int c, i; + int ret = 1; + char *filename = NULL; + char *layoutfile = NULL; + char *addr_param = NULL; + char *size_param = NULL; + uint32_t flash_start, flash_size, romhole_addr, romhole_size; + struct msi_romhole *romhole = NULL; + + while (1) { + int optindex = 0; + + c = getopt_long(argc, argv, optstring, long_options, &optindex); + + if (c == -1) + break; + + switch (c) { + case 'a': + addr_param = strdup(optarg); + break; + case 's': + size_param = strdup(optarg); + break; + case 'l': + layoutfile = strdup(optarg); + break; + case 'o': + filename = strdup(optarg); + break; + case 'h': + ret = 0; /* fallthrough */ + case '?': + usage(); + goto out; + default: + break; + } + } + if (!layoutfile && (!addr_param || !size_param)) { + fprintf(stderr, "E: Must specify either a fmap_config.h filename or address and size\n"); + goto out; + } + if (!filename) { + fprintf(stderr, "E: Must specify a destination filename\n"); + goto out; + } + + if (layoutfile) { + flash_start = get_line_as_int(layoutfile, "FMAP_SECTION_FLASH_START", 0); + flash_size = get_line_as_int(layoutfile, "FMAP_SECTION_FLASH_SIZE", 0); + romhole_addr = get_line_as_int(layoutfile, "FMAP_SECTION_ROMHOLE_START", 0); + romhole_size = get_line_as_int(layoutfile, "FMAP_SECTION_ROMHOLE_SIZE", 0); + + // If flash is greater than 16 MiB, we have to adjust the start offset. + // Only 16MiB long BIOS region is mapped under 4G. + romhole_addr -= flash_start; + if ((flash_size > 16*MiB) && (romhole_addr > 16*MiB)) + romhole_addr -= 16*MiB; + + // The ROMHOLE structure needs the 32bit flash base address in host memory + romhole_addr += 0xff000000; + } else if (addr_param && size_param) { + romhole_addr = strtol(addr_param, NULL, 16); + romhole_size = strtol(size_param, NULL, 16); + } else { + fprintf(stderr, "E: Incorrect input parameters\n"); + goto out; + } + + if (romhole_size < 0x20000) { + fprintf(stderr, "E: The romhole flash region should be at least 128K\n"); + goto out; + } + + romhole = (struct msi_romhole *)malloc(romhole_size); + if (!romhole) { + fprintf(stderr, "E: Failed to allocate memory for the romhole\n"); + goto out; + } + + // Generate the table + + // Header + romhole->magic0 = ROMHOLE_MAGIC; + strncpy(romhole->magic1, "SYSD", 4); + romhole->address = romhole_addr; + romhole->size = romhole_size; + memset(romhole->pad0, 0xff, 48); + romhole->length = (uint16_t)sizeof(*romhole); + + // For some reason the actual data size is reduced by 64K + if (romhole_size > 0x10000) + romhole->length -= 0x10000; + + // Structures + + // UUID + strncpy(romhole->uuid.magic0, "sSiD", 4); + romhole->uuid.length = (uint16_t)sizeof(struct uuid_structure); + strncpy(romhole->uuid.magic1, "$uD", 3); + romhole->uuid.space = 1; + memset(romhole->uuid.uuid, 0xff, 16); + + // PWD + strncpy(romhole->pwd.magic, "spWd", 4); + romhole->pwd.length = (uint16_t)sizeof(struct pwd_structure); + for (i = 0; i < NUM_PWD_ENTRIES; i++) { + strncpy(romhole->pwd.entries[i].magic, "$s$", 3); + romhole->pwd.entries[i].number = i + 1; + romhole->pwd.entries[i].length = 0; + memset(romhole->pwd.entries[i].pwd, 0, 20); + } + + // GPDT + strncpy(romhole->gpdt.magic, "gPdT", 4); + romhole->gpdt.length = (uint16_t)sizeof(struct gpdt_structure); + romhole->gpdt.num_entries = NUM_GD_ENTRIES; + romhole->gpdt.space = 0; + for (i = 0; i < NUM_GD_ENTRIES; i++) { + strncpy(romhole->gpdt.entries[i].magic, "$gD", 3); + romhole->gpdt.entries[i].number = i + 1; + romhole->gpdt.entries[i].length = GD_SIZE; + memset(romhole->gpdt.entries[i].gd, 0xff, GD_SIZE); + } + + // UCSC + strncpy(romhole->ucsc.magic, "uCsC", 4); + romhole->ucsc.length = (uint16_t)sizeof(struct ucsc_structure); + for (i = 0; i < NUM_US_ENTRIES; i++) { + strncpy(romhole->ucsc.entries[i].magic, "$uS", 3); + // The first 6 entries are in order + if (i <= 5) + romhole->ucsc.entries[i].number = i + 1; + // The 7th entry and later start numeration from 'A' ascii + else + romhole->ucsc.entries[i].number = 0x41 + i - 6; + + romhole->ucsc.entries[i].length = US_SIZE; + memset(romhole->ucsc.entries[i].us, 0xff, US_SIZE); + } + + // T2RW + strncpy(romhole->t2rw.magic0, "t2Rw", 4); + romhole->t2rw.length = (uint16_t)sizeof(struct type2_rw); + strncpy(romhole->t2rw.magic1, "$tW", 3); + romhole->t2rw.space = 1; + memset(romhole->t2rw.smbios_type2, 0xff, TYPE2_SIZE); + + // FTB + strncpy(romhole->ftb.magic0, "$FTB", 4); + romhole->ftb.length = (uint16_t)sizeof(struct ftb_structure); + strncpy(romhole->ftb.magic1, "$DIB", 4); + romhole->ftb.space0 = 2; + romhole->ftb.size = FTB_SIZE; + romhole->ftb.space1 = 0; + strncpy(romhole->ftb.magic2, "MFTD", 4); + memset(romhole->ftb.data, 0xfe, FTB_SIZE); + + // FIB + strncpy(romhole->fib.magic0, "$FIB", 4); + romhole->fib.length = (uint16_t)sizeof(struct fib_structure); + romhole->fib.size = FIB_SIZE; + strncpy(romhole->fib.magic1, "$MFX", 4); + memset(romhole->fib.data, 0xfa, FIB_SIZE); + + // FDP + strncpy(romhole->fdp.magic0, "$FDP", 4); + romhole->fdp.length = (uint16_t)sizeof(struct fdp_structure); + strncpy(romhole->fdp.magic1, "$Fd", 3); + romhole->fdp.number = 1; + memset(romhole->fdp.data, 0xff, FDP_SIZE); + + // BUV + strncpy(romhole->buv.magic0, "$BuV", 4); + romhole->buv.length = (uint16_t)sizeof(struct buv_structure); + strncpy(romhole->buv.magic1, "$Bv", 3); + romhole->buv.number = 1; + memset(romhole->buv.data, 0xff, BUV_SIZE); + + // RIS + strncpy(romhole->ris.magic0, "$RiS", 4); + romhole->ris.length = (uint16_t)sizeof(struct ris_structure); + strncpy(romhole->ris.magic1, "$RiT", 4); + // We don't need to cary much about the UEFI volumes. The MSI BIOS update + // utilities will just copy the right values from the currently running BIOS. + memset(romhole->ris.volumes, 0xff, sizeof(romhole->ris.volumes)); + for (i = 0; i < NUM_VOLUMES; i++) { + // It seems there can be up to 8 volumes in total depending on the UEFI image + // layout, but last 8th entry did not match any of the UEFI volume addresses + // and additionally 7th entry is skipped. + if (i == NUM_VOLUMES - 1) + romhole->ris.volumes[i].number = 0x31 + NUM_VOLUMES; // ascii + else + romhole->ris.volumes[i].number = 0x31 + i; // ascii + romhole->ris.volumes[i].space = 0xff; + } + + // write the table + FILE *fd = fopen(filename, "wb"); + if (!fd) { + fprintf(stderr, "E: %s open failed: %s\n", filename, strerror(errno)); + goto out; + } + + if (fwrite(romhole, 1, sizeof(*romhole), fd) != sizeof(*romhole)) { + fprintf(stderr, "E: %s write failed: %s\n", filename, strerror(errno)); + fclose(fd); + goto out; + } + + if (fclose(fd)) { + fprintf(stderr, "E: %s close failed: %s\n", filename, strerror(errno)); + goto out; + } + + ret = 0; +out: + if (ret > 0) + fprintf(stderr, "E: Error creating '%s'\n", filename); + + free(filename); + + if (romhole) + free(romhole); + + exit(ret); + + return 0; +} diff --git a/util/smmstore_debug/.gitignore b/util/smmstore_debug/.gitignore new file mode 100644 index 00000000000..879ecdfdd2b --- /dev/null +++ b/util/smmstore_debug/.gitignore @@ -0,0 +1 @@ +smmstore_debug diff --git a/util/smmstore_debug/Makefile b/util/smmstore_debug/Makefile new file mode 100644 index 00000000000..dc350491410 --- /dev/null +++ b/util/smmstore_debug/Makefile @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +PRG := smmstore_debug + +CC ?= $(CROSS_COMPILE)gcc +HOSTCC ?= $(CC) +INSTALL ?= /usr/bin/env install +PREFIX ?= /usr/local + +HOSTCFLAGS ?= $(CFLAGS) +HOSTCFLAGS += -Wall -Wextra -MMD -MP -O3 + +HOSTLDFLAGS ?= $(LDFLAGS) + +# there files are in this directory +SRC := smmstore_debug.c + +OBJ := $(SRC:.c=.o) +DEP := $(SRC:.c=.o.d) + +.PHONY: all debug clean install + +all: $(PRG) + +debug: HOSTCFLAGS += -O0 -g +debug: HOSTLDFLAGS += -g +debug: all + +install: $(PRG) + $(INSTALL) -d $(DESTDIR)$(PREFIX)/bin/ + $(INSTALL) $^ $(DESTDIR)$(PREFIX)/bin/ + +clean: + -$(RM) $(PRG) $(OBJ) $(DEP) + +$(PRG): $(OBJ) + $(HOSTCC) -o $@ $^ $(HOSTLDFLAGS) + +%.o: %.c + $(HOSTCC) $(HOSTCFLAGS) -c -o $@ -MF $@.d $< + +-include $(DEP) diff --git a/util/smmstore_debug/description.md b/util/smmstore_debug/description.md new file mode 100644 index 00000000000..dc15307e4ac --- /dev/null +++ b/util/smmstore_debug/description.md @@ -0,0 +1 @@ +Debug tool for low-level interactions with SMMSTORE `C` diff --git a/util/smmstore_debug/smmstore_debug.c b/util/smmstore_debug/smmstore_debug.c new file mode 100644 index 00000000000..8e7cfde6d4f --- /dev/null +++ b/util/smmstore_debug/smmstore_debug.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STR(x) _STR(x) +#define _STR(x) #x + +#define APM_CNT 0xb2 +#define SMMSTORE_CMD 0xed +#define SMMSTORE_PARAMS_SIZE 0x1000 +#define SMMSTORE_COMBUF_SIZE 0x10000 + +/* Size is doubled to account for page alignment required for mmap() */ +static unsigned char tmpbuf[2 * SMMSTORE_PARAMS_SIZE]; + +static inline unsigned int call_smm (unsigned int cmd, unsigned int arg) +{ + unsigned int res = 0; + asm volatile ( + "outb %b0, $" STR(APM_CNT) "\n\t" + "nop; nop; nop\n\t" + : "=a" (res) + : "a" (cmd), + "b" (arg) + : "memory"); + return res; +} + +static int usage (char *name) +{ + printf ("Usage:\n" + "\t%s --tmp_buf --com_buf --command \n" + "\t%*s [--in_file ] [--out_file ] param1 ...\n" + "\t%s -t -b -c \n" + "\t%*s [-i ] [-o ] param1 ...\n\n", + name, (int)strlen(name), "", name, (int)strlen(name), ""); + printf ("--tmp_buf, -t - physical address of a buffer in low 4GB of RAM. Up to 8KB\n" + " after this address will be overwritten with params and then\n" + " restored. Point it to something that won't break because of\n" + " such temporary modification (e.g. part of CONSOLE in CBMEM,\n" + " **after** the header - so SMI handler can still print to\n" + " the CBMEM console).\n" + "--com_buf, -b - physical address of SMM COMBUFFER, can be read from\n" + " `cbmem -l`. It must be aligned to a page size.\n" + "--command, -c - command to execute, see `coreboot/src/include/smmstore.h`.\n" + " For SMMSTOREv2 this is 5 for read, 6 for write, 7 for\n" + " clear.\n" + "param1 ... - params passed to SMI handler, as set of uint32_t values.\n" + " Numbers are parsed as hexadecimal values, even without '0x'\n" + " prefix. Expected structure depends on the command, refer to\n" + " `smmstore_params_raw*` structure definitions in\n" + " `coreboot/src/include/smmstore.h` file. At least one\n" + " parameter must be specified.\n" + "--in_file, -i - optional, binary file which content is written to com_buf\n" + " before SMM call.\n" + "--out_file, -o - optional, path to binary file (it is created if doesn't exist)\n" + " to which the content of com_buf after SMM call is saved.\n\n" + "Some of the combinations don't make sense (e.g. writing to COMBUFFER before\n" + "read command), but the tool doesn't check this. It is supposed to help\n" + "with testing and debugging, hence it allows for sending garbage to SMMSTORE\n" + "handler, with the assumption that the user knows what he's doing.\n\n" + "The utility must be run with CAP_SYS_RAWIO privilege (e.g. as root)\n" + "and with no kernel_lockdown in place (i.e. without SecureBoot).\n"); + return -1; +} + +static struct option long_options[] = { + {"tmp_buf", required_argument, 0, 't'}, + {"com_buf", required_argument, 0, 'b'}, + {"command", required_argument, 0, 'c'}, + {"out_file", required_argument, 0, 'o'}, + {"in_file", required_argument, 0, 'i'}, + {0, 0, 0, 0 } +}; + +int main (int argc, char *argv[]) +{ + int fd; + void *combuf; + unsigned long combuf_addr = 0; + unsigned char *params; + unsigned long params_phys = 0; + unsigned long params_phys_aligned; + unsigned int command = (unsigned int)-1; + char *in_file = NULL; + char *out_file = NULL; + char *end; + + while (1) { + int idx = 0; + int opt; + + opt = getopt_long (argc, argv, "t:b:c:o:i:", long_options, &idx); + + if (opt == -1) + break; + + switch (opt) { + case 't': + params_phys = strtoul (optarg, &end, 16); + if (params_phys == 0 || params_phys == ULONG_MAX) return usage(argv[0]); + break; + case 'b': + combuf_addr = strtoul (optarg, &end, 16); + if (combuf_addr == 0 || combuf_addr == ULONG_MAX) return usage(argv[0]); + break; + case 'c': + command = strtoul (optarg, &end, 16); + if (command == 0 || command == UINT_MAX) return usage(argv[0]); + break; + case 'o': + out_file = optarg; + break; + case 'i': + in_file = optarg; + break; + default: + return usage(argv[0]); + } + } + + /* Check if all required options were given */ + if (!combuf_addr || !params_phys || command == (unsigned int)-1 || optind == argc) + return usage(argv[0]); + + params_phys_aligned = params_phys & ~((unsigned long)(getpagesize() - 1)); + + /* Map COMBUF and temporary buffer for params */ + fd = open ("/dev/mem", O_SYNC | O_RDWR); + if (fd < 0) { + perror ("Can't access physical memory"); + printf ("This tool must be run as root with SecureBoot disabled.\n"); + return -1; + } + combuf = mmap (NULL, SMMSTORE_COMBUF_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED | MAP_POPULATE, fd, combuf_addr); + params = mmap (NULL, 2 * SMMSTORE_PARAMS_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED | MAP_POPULATE, fd, params_phys_aligned); + close (fd); + + /* Fill COMBUF from in_file */ + if (in_file) { + fd = open (in_file, O_RDONLY); + if (fd < 0) { + perror ("Error opening in_file"); + return -1; + } + read (fd, combuf, SMMSTORE_COMBUF_SIZE); + close (fd); + } + + /* Request IO access to APM_CNT port */ + if (ioperm (APM_CNT, 1, 1) < 0) { + perror ("Can't access IO port"); + printf ("This tool must be run as root with SecureBoot disabled.\n"); + return -1; + } + + /* Backup temporary buffer and fill params */ + memcpy (tmpbuf, params, sizeof(tmpbuf)); + for (int i = 0; i < (argc - optind) && i < (int)(SMMSTORE_PARAMS_SIZE / sizeof (unsigned int)); i++) { + unsigned int *param = (unsigned int *)(params + (params_phys - params_phys_aligned)); + param[i] = strtoul (argv[i + optind], &end, 16); + } + + printf ("SMI handler returned %#x\n", call_smm ((command << 8) | SMMSTORE_CMD, params_phys)); + + /* Restore original contents of memory used for params */ + memcpy (params, tmpbuf, sizeof(tmpbuf)); + + /* Store COMBUF to out_file */ + if (out_file) { + fd = creat (out_file, 0666); + if (fd < 0) { + perror ("Error opening out_file"); + return -1; + } + write (fd, combuf, SMMSTORE_COMBUF_SIZE); + close (fd); + } + + return 0; +} diff --git a/util/smmstoretool/data.c b/util/smmstoretool/data.c index 41d3b75aba8..b4c6c0aa73d 100644 --- a/util/smmstoretool/data.c +++ b/util/smmstoretool/data.c @@ -116,6 +116,7 @@ void *make_data(const char source[], size_t *data_size, enum data_type type) bool boolean; uint64_t uint; bool failed; + FILE *f; case DATA_TYPE_BOOL: if (str_eq(source, "true")) { @@ -174,8 +175,22 @@ void *make_data(const char source[], size_t *data_size, enum data_type type) case DATA_TYPE_UNICODE: return to_uchars(source, data_size); case DATA_TYPE_RAW: - fprintf(stderr, "Raw data type is output only\n"); - return NULL; + f = fopen(source, "rb"); + if (!f) { + perror(source); + return NULL; + } + fseek(f, 0, SEEK_END); + *data_size = ftell(f); + fseek(f, 0, SEEK_SET); + data = xmalloc(*data_size); + if (fread(data, 1, *data_size, f) != *data_size) { + fprintf(stderr, "Error reading data from '%s', aborting\n", source); + free(data); + data = NULL; + } + fclose(f); + return data; } return NULL; diff --git a/util/smmstoretool/main.c b/util/smmstoretool/main.c index 89d58d619aa..b7fa5c49eec 100644 --- a/util/smmstoretool/main.c +++ b/util/smmstoretool/main.c @@ -128,7 +128,7 @@ static void print_types(FILE *f) fprintf(f, " * uint64 (0..2^64-1)\n"); fprintf(f, " * ascii (NUL-terminated)\n"); fprintf(f, " * unicode (widened and NUL-terminated)\n"); - fprintf(f, " * raw (output only; raw bytes on output)\n"); + fprintf(f, " * raw (file name on input; raw bytes on output)\n"); } static void help_set(FILE *f, const struct subcommand_t *info) diff --git a/util/txesbmantool/.gitignore b/util/txesbmantool/.gitignore new file mode 100644 index 00000000000..ed281d79ba6 --- /dev/null +++ b/util/txesbmantool/.gitignore @@ -0,0 +1 @@ +txesbmantool diff --git a/util/txesbmantool/Makefile b/util/txesbmantool/Makefile new file mode 100644 index 00000000000..2888361620d --- /dev/null +++ b/util/txesbmantool/Makefile @@ -0,0 +1,35 @@ +# txesbmantool - Utility for generating TXE Secure Boot manifests +# SPDX-License-Identifier: GPL-2.0-only + +CC ?= gcc +INSTALL ?= /usr/bin/env install +PREFIX ?= /usr/local + +HOSTCC ?= $(CC) +HOSTCFLAGS ?= $(CFLAGS) +top := ../.. +objutil ?= .. + +ifneq ($(PKG_CONFIG),) +HOSTPKGCONFIG ?= $(PKG_CONFIG) +else +HOSTPKGCONFIG ?= pkg-config +endif +HOSTCFLAGS += $(shell $(HOSTPKGCONFIG) --cflags wolfssl) +LDFLAGS ?= $(shell $(HOSTPKGCONFIG) --libs wolfssl) + +include Makefile.mk + +PROGRAM=$(objutil)/txesbmantool/txesbmantool + +all: $(PROGRAM) + +clean: + rm -f $(PROGRAM) *.o *~ .dependencies +distclean: clean + +install: $(PROGRAM) + $(INSTALL) -d $(DESTDIR)$(PREFIX)/bin + $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin + +.PHONY: all clean distclean install diff --git a/util/txesbmantool/Makefile.mk b/util/txesbmantool/Makefile.mk new file mode 100644 index 00000000000..ad03419ad70 --- /dev/null +++ b/util/txesbmantool/Makefile.mk @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: BSD-3-Clause + +txesbmantoolsrc = txesbmantool.c + +TXESBMANTOOLCFLAGS = -Wall -Wextra -Wmissing-prototypes -Werror +TXESBMANTOOLCFLAGS += $(shell $(HOSTPKGCONFIG) --libs wolfssl) + +$(objutil)/txesbmantool/txesbmantool: $(addprefix $(top)/util/txesbmantool/,$(txesbmantoolsrc)) + printf " TXESBMANTOOL\n" + mkdir -p $(objutil)/txesbmantool + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< $(TXESBMANTOOLCFLAGS) diff --git a/util/txesbmantool/README.md b/util/txesbmantool/README.md new file mode 100644 index 00000000000..2f095244f10 --- /dev/null +++ b/util/txesbmantool/README.md @@ -0,0 +1,247 @@ +# txesbmantool + +`txesbmantool` - utility generating the TXE Secure Boot manifests +(abbreviation of TXE Secure Boot Manifest Tool). The utility aims to help +develop, sign, and automate the creation process of TXE Secure Boot-supported +images. + +## Suported commands + +The txesbmantool supports the following commands: + +```txt +txesbmantool: Utility for generating TXE Secure Boot manifests +USAGE: + ./txesbmantool FILE COMMAND + + ./txesbmantool --help + + ./txesbmantool --version + +COMMANDs: + print + keyhash + verify --sbm-key-file [--km-key-file ] + generate-km --sbm-key-file --km-key-file [--km-id ] [--svn ] [-o ] + generate-sbm --sbm-key-file [--oem-data ] [--svn ] [-o ] + +OPTIONS: + -o : Output manifest file (optional) + --sbm-key-file : Secure Boot (SB) Manifest key file + --km-key-file : Key Manifest key file + --km-id : Key Manifest ID number (default 1) + --oem-data : Optional OEM data file to be included in SB Manifest + --svn : Security Version Number for the manifest (default 2), + Key Manifest SVN range 1-15, SB Manifest SVN range 0-63 +``` + +### `print` + +`print` - parses the input `FILE` and prints Key Manifest and Secure Boot +Manifest if found. Example output: + +```txt +./txesbmantool coreboot.rom print +Key Manifest: + Magic: $SKM + Version: 1 + Size: 1024 + Svn: 2 + Key Manifest ID: 0x01 + SB Key hash: E671B83E4BB9AAC11D1578D10999922EB4EBFCFB0A1E30A7A37DAF33163FA2BB + Key modulus: + 45 40 DC B5 21 AF 0A ED A0 1F DF 15 66 92 98 E1 + D6 3E 08 61 3E BC 45 8B 9B E7 A7 66 F3 56 DC 56 + 94 12 D1 D3 CB D1 F7 25 60 DA C9 DC 3C 8A 94 68 + 73 59 AB 99 CE 5F B8 CE F9 FD 9F 2B 5C FB FA B7 + 35 0C 5B 23 68 64 81 44 AB F3 BE 27 A3 10 A2 2E + F7 A1 F4 31 6A 59 17 6A A0 89 4B 6C 39 58 1F 4D + 97 6A 62 05 48 1C 21 22 A5 35 1A 64 A7 A0 A3 42 + 20 0E CC C7 71 99 24 83 DD 8F 4B 14 61 1A E0 2E + 70 52 2C 82 00 22 08 02 C7 17 0B 4D 9B DD BB A7 + 66 63 12 E7 74 4C 5E 9B C0 0C BC EC 49 D3 5B 6D + 49 E5 E0 20 96 8E 4B 39 74 28 DA 7A 7F 20 95 E4 + 7F 5C 4D 38 C9 57 12 49 04 BC B7 0B ED ED A2 69 + 12 83 0C C8 CE 56 3B 8D 04 A2 27 EA D1 05 52 51 + E4 A6 E8 3B 00 58 1D 9E 4D 33 00 9D 91 B6 36 AC + AA 48 C9 24 AD 50 59 E2 E4 00 B7 A5 9C 0E BC 0A + DF CB 47 A1 B7 F1 20 38 09 F2 BF EE 34 CA 52 C9 + Key exponent: 0x10001 + Signature: + 4C 00 31 A2 E6 DB 99 EC C6 B3 84 AE 9E 28 BC AE + 18 1A F8 09 B9 5A 38 6F A4 15 93 D5 F6 E6 C2 A5 + FC 9D 37 3E 80 41 0B AB 44 C7 86 33 26 1A CB AF + BC FD D6 8B 18 CA 65 75 15 5D 32 75 85 0B AB 86 + 82 B4 24 67 2C FE DD 2E BB 69 9F B8 4B 1D 80 84 + DE 09 C6 80 8B 46 0D D8 4C 4C 75 EC F2 61 67 CA + 6B A5 39 20 20 D3 29 72 65 98 82 A0 41 ED FF 9E + 68 44 CE 47 5D 90 DC C1 8E 7F 19 C6 A9 9A 27 DE + 16 B7 12 A5 5D EA 61 53 4B 17 E7 E3 5E 71 04 FE + 29 DE D4 0C 44 B2 19 1E A3 41 29 C6 C6 AE 4D C0 + CA 97 A0 53 B2 55 D5 CE E6 B1 45 5B 38 34 2A C1 + 16 5F 56 F4 66 87 8D 8C 75 89 D1 6F 2D 9E 0B FC + BF 16 C1 2F 53 DD AA 0A 0B 46 14 A5 0D 68 8F 24 + 45 F4 FB 4E 4A 99 8F 33 B6 D0 F9 70 42 ED F5 F6 + 63 87 BB 8C EB DD 6C 8E B5 62 EE EB C5 CC 94 DA + E5 B6 BF 1F 4A CA F6 F1 E8 D7 7C 79 AF 3B 6A C7 +Secure Boot Manifest: + Magic: $VBM + Version: 1 + Size: 1024 + Svn: 2 + IBB hash: C27838A5EB12A57CE3880896C83E7E437EF6D4DF94B8808A36C2779B0B3DE731 + OEM Data: + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + Key modulus: + 59 8E 0E 9C 78 BA 84 9E 08 70 A0 2E 03 C9 EC 60 + 51 AD 75 77 6A BD D8 51 1E 2A B4 2C 3E 14 8C A9 + 5A AF 36 0F 6F 17 8C E3 C2 E6 40 0F 8A DF E0 1F + FC 31 74 31 A6 D3 E0 D5 01 4A D6 40 11 A5 CB 3A + 19 01 D6 4C 52 E0 47 B2 2E C2 3F CD E0 1B 53 51 + 9D C0 7D 6E D8 8D D7 D9 8E C3 FE 85 19 19 29 92 + 11 C3 B4 53 63 E6 61 12 C4 8B F9 0D 5F DB D1 50 + 64 CD 78 CB 10 0B 84 92 42 AE 1E 81 4E 57 CF 9F + D9 85 CA 4A F4 CE DA 03 BC 5E 0D 7C BD E9 EB 13 + C3 C3 C2 4D EF 21 08 15 5A EC EA E8 F8 CD C0 DE + 9B 57 55 DF B8 C4 40 27 18 29 A5 98 85 09 5C EF + DE 39 B5 A8 F5 69 D7 D2 1F A9 A4 9F D2 61 C5 82 + 1D 5E D0 3B 69 CA DF 8B A0 3F E4 C4 85 15 2D EB + F6 32 5F 70 1E DF 93 21 AD F7 65 40 E2 4B B0 26 + D2 DA F1 3C F0 9A A9 80 3C E6 F9 71 46 C1 5F 50 + 65 BE 70 80 3A 1A DA 51 79 75 04 B3 3F 17 FF AF + Key exponent: 0x10001 + Signature: + DF 5F B8 66 76 0F CC A9 93 C7 28 0F EF 32 14 7A + 1A 23 04 2A 75 85 24 0A 85 7F E5 B8 CE 24 44 C1 + D6 73 5B D6 30 BD A3 66 15 85 6A 3A 8E FC 8F 56 + 75 71 28 86 0F F3 E3 1C 20 A4 2E 33 15 45 E5 24 + 1A BB 69 A0 FD D8 7A A1 34 2E 7A 40 60 E1 4C 51 + D3 BB 73 BC 1A A5 43 E5 6F B6 54 4F 31 2A 65 9B + DD 1A BE 45 5A 7A E5 15 44 76 EC 94 89 33 14 11 + C6 18 39 ED 02 D7 B3 5C 56 23 2A 58 18 87 EE 2A + 0A F5 FD E9 5F 94 B3 92 17 21 59 3E A4 0F CF 4A + 99 95 33 FB AD 73 CF 1C 7F 1F CB 31 EC 2D 57 0D + 8B 3E DB CF D4 F0 62 26 26 0F D9 17 DD BC 3C 1F + 28 76 E4 81 D5 CF 04 BB 5D 33 82 D8 EB DA 64 45 + 14 A9 24 90 5D 93 E8 D6 34 1C 0C 2B 6F 18 4F DF + 45 6E EE 2A FB 00 D2 B7 BC 36 9D D9 91 FF A7 39 + 39 4D 96 48 DD 7C 43 29 73 7F 6A 8A 73 F2 B0 57 + E4 B7 2A 34 A1 F1 83 A5 7F A7 17 6C 1A E2 EC 26 +``` + +### `verify` + +`verify` - parses the input `FILE` and verifies whether the input `FILE` has +been correctly signed for TXE Secure Boot. Additional input parameters are +paths to the private signing keys to perform verification. If the image is +expected to have a Key Manifest, one must also pass the key used to sign Key +Manifest. The tool will also print the expected TXE image configuration. +Example output: + +```txt +./txesbmantool coreboot.rom verify \ + --sbm-key-file sb_privkey_sample.pem \ + --km-key-file oem_privkey_sample.pem +Verifying Key Manifest... +Key Manifest verification successful! + +TXE image should be provisioned with the following key hash: +AE6491B401B639DB9FA6E86D22FACE37F846E506328FDBF4327802C271FFE6FF +TXE should be provisioned with the following Key Manifest ID: 0x01 + +Verifying Secure Boot Manifest... +Secure Boot Manifest verification is successful! +``` + +If the Key Manifest is found in the binary but the `--km-key-file` was not +passed with a valid key, the tool will output an error: + +```txt +ERROR: Key Manifest key file not given, but Key Manifest found in the input file +ERROR: Can not verify Key Manifest! +``` + +### `generate-km` + +`generate-km` - creates a signed Key Manifest and injects it into the input +`FILE`. Secure Boot Manifest key is taken as `--sbm-key-file ` parameter +and Key Manifest key as `--km-key-file ` parameter. Key Manifest is used +to authorize a Secure Boot Manifest key that will be eligible to sign Secure +Boot Manifests. One may optionally provide a custom Key Manifest ID +(`--km-id`), SVN (`--svn`), and save the resulting Key Manifest as a separate +file with `-o` parameter. Example: + +```txt +./txesbmantool coreboot.rom generate-km \ + --sbm-key-file sb_privkey_sample.pem \ + --km-key-file oem_privkey_sample.pem \ + --km-id 1 --svn 2 +SHA256 of the Secure Boot Manifest Key (Little Endian): +E671B83E4BB9AAC11D1578D10999922EB4EBFCFB0A1E30A7A37DAF33163FA2BB + +Key Manifest generated successfully +``` + +### `generate-sbm` + +`generate-sbm` - creates a signed Secure Boot Manifest and injects it to the +input `FILE`. Secure Boot Manifest key is taken as `--sbm-key-file ` +parameter. The Secure Boot Manifest contains the hash of the IBB that is being +verified by TXE. One may optionally provide a custom SVN (`--svn`) and save +the resulting Key Manifest as a separate file with `-o` parameter. Example: + +```txt +./txesbmantool coreboot.rom generate-sbm \ + --sbm-key-file sb_privkey_sample.pem \ + --svn 2 +SHA256 of the IBB (Little Endian): +C27838A5EB12A57CE3880896C83E7E437EF6D4DF94B8808A36C2779B0B3DE731 + +Secure Boot Manifest generated successfully +``` + +The utility may also take an additional max 400 bytes block of data as +`--oem-data` parameter. It is not used by hardware, however, it is verified as +a part of the manifest verification and can be used for any purpose. +Currently, coreboot does not use it at all, as there is no need for it. + +### `keyhash` + +`keyhash` - takes a key as an input `FILE` and prints out the SHA256 of the +key modulus+exponent. It is useful when preparing the TXE image for Secure +Boot, where one needs to provide the SHA256 of the key to be set in the +fuses/emulated fuses. Example: + +```txt +./txesbmantool oem_privkey_sample.pem keyhash +SHA256 of RSA key 'oem_privkey_sample.pem': +AE6491B401B639DB9FA6E86D22FACE37F846E506328FDBF4327802C271FFE6FF +``` + +In the above example, the hash corresponds to the key used to sign the Key +Manifest. The same hash can be found in the example output of `verify` +command. diff --git a/util/txesbmantool/description.md b/util/txesbmantool/description.md new file mode 100644 index 00000000000..f16c10f2d00 --- /dev/null +++ b/util/txesbmantool/description.md @@ -0,0 +1 @@ +Generates Secure Boot Manifests for TXE Secure Boot `C` diff --git a/util/txesbmantool/txesbmantool.c b/util/txesbmantool/txesbmantool.c new file mode 100644 index 00000000000..22b001ff425 --- /dev/null +++ b/util/txesbmantool/txesbmantool.c @@ -0,0 +1,1455 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#ifndef WOLFSSL_USER_SETTINGS + #include +#endif + +#include +#include +#include +#include +#include + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#endif + +#define WARN(...) fprintf(stderr, "WARNING: " __VA_ARGS__) +#define ERROR(...) fprintf(stderr, "ERROR: " __VA_ARGS__) + +#define RSA_KEY_SIZE 2048 +#define RSA_KEY_EXPONENT 0x10001 +#define DER_FILE_BUFFER 2048 /* max DER size */ + +#define MANIFEST_SIZE 1024 + +#define SB_MANIFEST_MAGIC 0x4d425624 /* $VBM in LE */ +#define SB_MANIFEST_VERSION 0x1 +#define SB_MANIFEST_SIZE MANIFEST_SIZE + +#define KEY_MANIFEST_MAGIC 0x4d4b5324 /* $SKM in LE */ +#define KEY_MANIFEST_VERSION 0x1 +#define KEY_MANIFEST_PAD_SIZE (4096 - MANIFEST_SIZE) +#define KEY_MANIFEST_RESERVED_SIZE 456 +#define KEY_MANIFEST_SIZE (MANIFEST_SIZE + KEY_MANIFEST_PAD_SIZE) + +#define IBB_SIZE (0x20000 - SB_MANIFEST_SIZE) + +static const char tool_version[] = "0.1"; + +struct manifest_header { + uint32_t magic; + uint32_t version; + uint32_t size; + uint32_t svn; +} __attribute__((packed)); + +struct key_signature { + uint8_t modulus[256]; + uint32_t exponent; + uint8_t signature[256]; +} __attribute__((packed)); + +struct manifest { + struct manifest_header header; + uint32_t km_id; /* Only for Key Manifest */ + uint8_t hash[WC_SHA256_DIGEST_SIZE]; /* IBB hash of SBM, Key hash for KM */ + union { + struct { + uint32_t reserved1; + uint32_t reserved2[8]; + uint8_t oem_data[400]; + uint8_t reserved3[20]; + } sb; + uint8_t reserved[KEY_MANIFEST_RESERVED_SIZE]; + }; + struct key_signature key_sig; +} __attribute__((packed)); + +_Static_assert(sizeof(struct manifest) == MANIFEST_SIZE, "Wrong size of Manifest structure"); + +static struct params { + const char *output; + const char *file_name; + const char *oem_data_file; + const char *sbm_key_file; + const char *km_key_file; + bool override_km_id; + uint32_t km_id; + bool override_svn; + uint32_t svn; +} params; + +static off_t get_file_size(FILE *f) +{ + off_t fsize; + fseek(f, 0, SEEK_END); + fsize = ftell(f); + fseek(f, 0, SEEK_SET); + return fsize; +} + +static bool mem_is_zero(const byte *memory, word32 size) +{ + for (word32 i = 0; i < size; i++) { + if (memory[i] == 0) + continue; + else + return false; + } + + return true; +} + +static void hexdump(const void *buffer, word32 len, byte cols, word32 indent) +{ + word32 i, j; + + if (len > 0) { + for (j = 0; j < indent; j++) + printf("\t"); + } + + for (i = 0; i < len + ((len % cols) ? (cols - len % cols) : 0); i++) + { + /* print hex data */ + if (i < len) { + printf("%02X ", ((byte*)buffer)[i] & 0xFF); + } + + if (i % cols == (word32)(cols - 1)) { + printf("\n"); + if (i != (len - 1)) { + for (j = 0; j < indent; j++) + printf("\t"); + } + } + } +} + +static void print_sha256(const byte *buffer) +{ + for (word32 i = 0; i < WC_SHA256_DIGEST_SIZE; i++) + printf("%02X", buffer[i]); + + printf("\n"); +} + +static void print_magic(uint32_t magic) +{ + printf("%c%c%c%c\n", + (unsigned char)(magic & 0xff), + (unsigned char)((magic >> 8) & 0xff), + (unsigned char)((magic >> 16) & 0xff), + (unsigned char)((magic >> 24) & 0xff)); +} + +static int swap_bytes(byte *buffer, word32 len) +{ + byte *tmp; + + if (len <= 0 || buffer == NULL) + return EXIT_FAILURE; + + tmp = malloc(len); + + if (!tmp) + return EXIT_FAILURE; + + memcpy(tmp, buffer, len); + + for (word32 i = 0; i < len; i++) { + buffer[i] = tmp[len - 1 - i]; + } + + free(tmp); + + return 0; +} + +static int rsa_load_key_file(const char *keyFile, RsaKey *rsaKey) +{ + int ret = EXIT_FAILURE; + FILE *file; + byte *buffer = NULL; + word32 bufSize = DER_FILE_BUFFER; + byte *derBuffer = NULL; + word32 derBufSize = DER_FILE_BUFFER; + word32 bytes = 0; + word32 idx = 0; + + file = fopen(keyFile, "rb"); + if (file) { + buffer = malloc(bufSize); + if (buffer) { + bytes = fread(buffer, 1, bufSize, file); + } + fclose(file); + } + + derBuffer = malloc(derBufSize); + + if (buffer != NULL && bytes > 0 && derBuffer != NULL) { + ret = wc_KeyPemToDer(buffer, bytes, derBuffer, derBufSize, NULL); + + if (ret < 0) { + free(derBuffer); + } else { + free(buffer); + buffer = derBuffer; + bytes = (word32)ret; + } + + ret = wc_RsaPrivateKeyDecode(buffer, &idx, rsaKey, (word32)bytes); + } + + if (buffer) { + free(buffer); + } + + return ret; +} + +static int calculate_key_hash(RsaKey *rsaKey, byte *key_hash) +{ + int ret; + wc_Sha256 sha256; + uint8_t modulus[256]; + uint32_t exponent = 0; + word32 e_size = sizeof(exponent); + word32 n_size = sizeof(modulus); + + ret = wc_RsaFlattenPublicKey(rsaKey, (byte *)&exponent, &e_size, + (byte *)&modulus, &n_size); + if (ret != 0) { + ERROR("Failed to extract Secure Boot Manifest Key exponent and modulus!\n"); + return ret; + } + + if (swap_bytes(modulus, n_size)) { + ERROR("Failed to change RSA key modulus endianess!\n"); + return EXIT_FAILURE; + } + + ret = wc_InitSha256(&sha256); + if (ret != 0) { + ERROR("Failed to initialize SHA256 context\n"); + return ret; + } + + ret = wc_Sha256Update(&sha256, modulus, n_size); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + /* e_size returned is 3, but we have to take whole uint32_t */ + ret = wc_Sha256Update(&sha256, (byte *)&exponent, sizeof(exponent)); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + ret = wc_Sha256Final(&sha256, key_hash); + if (ret != 0) { + ERROR("Failed to generate SHA256 hash\n"); + return ret; + } + + if (swap_bytes(key_hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Failed to change SHA256 hash endianess!\n"); + return EXIT_FAILURE; + } + + return ret; +} + +static int calculate_ibb_hash(const byte *buffer, byte *ibb_hash) +{ + int ret; + wc_Sha256 sha256; + + ret = wc_InitSha256(&sha256); + if (ret != 0) { + ERROR("Failed to initialize SHA256 context\n"); + return ret; + } + + ret = wc_Sha256Update(&sha256, buffer, IBB_SIZE); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + ret = wc_Sha256Final(&sha256, ibb_hash); + if (ret != 0) { + ERROR("Failed to generate SHA256 hash\n"); + return ret; + } + + if (swap_bytes(ibb_hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Failed to change SHA256 hash endianess!\n"); + return EXIT_FAILURE; + } + + return ret; +} + +static int create_sb_manifest(struct manifest *man, byte* romBuf, word32 romLen, byte* oemData, + word32 oemDataLen, word32 manifestSVN) +{ + int ret; + byte *sha256_buffer; + size_t file_size = IBB_SIZE + SB_MANIFEST_SIZE; + + if (romLen < file_size) { + ERROR("ROM file too small\n"); + return EXIT_FAILURE; + } + + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != 32) { + ERROR("Hash type SHA256 not supported!\n"); + return EXIT_FAILURE; + } + + memset((byte *)man, 0, MANIFEST_SIZE); + + man->header.magic = SB_MANIFEST_MAGIC; + man->header.version = SB_MANIFEST_VERSION; + man->header.svn = manifestSVN; + man->header.size = MANIFEST_SIZE; + + if (oemData != NULL && oemDataLen > 0) { + if (oemDataLen <= sizeof(man->sb.oem_data)) + memcpy((byte *)man->sb.oem_data, oemData, oemDataLen); + else + WARN("OEM Data file length too big, ignoring it.\n"); + } + + ret = calculate_ibb_hash(&romBuf[romLen - IBB_SIZE], man->hash); + if (ret != 0) { + ERROR("Failed to calcualte IBB hash!\n"); + return ret; + } + + sha256_buffer = man->hash; + printf("SHA256 of the IBB (Little Endian):\n"); + print_sha256(sha256_buffer); + printf("\n"); + + return ret; +} + +static int create_key_manifest(struct manifest *man, word32 romLen, word32 manifestSVN) +{ + int ret; + RsaKey sbmKey; + size_t file_size = IBB_SIZE + SB_MANIFEST_SIZE + KEY_MANIFEST_SIZE; + + if (romLen < file_size) { + ERROR("ROM file too small\n"); + return EXIT_FAILURE; + } + + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != 32) { + ERROR("Hash type SHA256 not supported!\n"); + return EXIT_FAILURE; + } + + memset((byte *)man, 0, MANIFEST_SIZE); + + man->header.magic = KEY_MANIFEST_MAGIC; + man->header.version = KEY_MANIFEST_VERSION; + man->header.svn = manifestSVN; + man->header.size = MANIFEST_SIZE; + + if (params.override_km_id) + man->km_id = params.km_id; + else + man->km_id = 1; + + ret = wc_InitRsaKey(&sbmKey, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + return ret; + } + + ret = rsa_load_key_file(params.sbm_key_file, &sbmKey); + if (ret != 0) { + ERROR("Failed to load Secure Boot Manifest Key!\n"); + return ret; + } + + ret = calculate_key_hash(&sbmKey, man->hash); + if (ret != 0) { + ERROR("Failed to calcualte Secure Boot key hash!\n"); + wc_FreeRsaKey(&sbmKey); + return ret; + } + + printf("SHA256 of the Secure Boot Manifest Key (Little Endian):\n"); + print_sha256(man->hash); + printf("\n"); + + wc_FreeRsaKey(&sbmKey); + return ret; +} + +static int rsa_sign_manifest(struct manifest *man, const char *key_path) +{ + int ret; + RsaKey rsaKey; + WC_RNG rng; + byte *sigBuf = NULL; + word32 sigLen; + word32 e_size, n_size; + struct key_signature *key_struct = &man->key_sig; + + ret = wc_InitRng(&rng); + if (ret != 0) { + ERROR("Init RNG failed! %d\n", ret); + goto exit; + } + + ret = wc_InitRsaKey(&rsaKey, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + goto exit; + } + + ret = rsa_load_key_file(key_path, &rsaKey); + if (ret != 0) { + ERROR("Failed to load RSA key %s! (%d)\n", key_path, ret); + goto exit; + } + + e_size = sizeof(key_struct->exponent); + n_size = sizeof(key_struct->modulus); + + ret = wc_RsaFlattenPublicKey(&rsaKey, (byte *)&key_struct->exponent, &e_size, + (byte *)key_struct->modulus, &n_size); + + if (ret != 0) { + ERROR("Failed to write key modulus and exponent! %d\n", ret); + goto exit; + } + + /* Change endianess of the modulus to LE */ + if (swap_bytes((byte *)key_struct->modulus, n_size)) { + ERROR("Failed to change RSA Key modulus endianess!\n"); + goto exit; + } + + if (n_size * 8 != RSA_KEY_SIZE) { + ERROR("Incorrect RSA key size! %d != 2048\n", n_size * 8); + ret = EXIT_FAILURE; + goto exit; + } + + if (key_struct->exponent != RSA_KEY_EXPONENT) { + ERROR("Incorrect RSA key size! 0x%x != 0x10001\n", key_struct->exponent); + ret = EXIT_FAILURE; + goto exit; + } + + /* Verify hash type is supported */ + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != 32) { + ERROR("Hash type SHA256 not supported!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + sigLen = wc_SignatureGetSize(WC_SIGNATURE_TYPE_RSA_W_ENC, &rsaKey, sizeof(rsaKey)); + if (sigLen != sizeof(key_struct->signature)) { + ERROR("RSA Signature size check fail! %d\n", sigLen); + ret = EXIT_FAILURE; + goto exit; + } + + sigBuf = malloc(sigLen); + if (!sigBuf) { + ERROR("RSA Signature malloc failed!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + ret = wc_SignatureGenerate(WC_HASH_TYPE_SHA256, WC_SIGNATURE_TYPE_RSA_W_ENC, + (byte *)man, + MANIFEST_SIZE - sizeof(struct key_signature), + sigBuf, &sigLen, + &rsaKey, sizeof(rsaKey), + &rng); + if (ret < 0) { + ERROR("RSA signature generation failed (%d)!\n", ret); + goto exit; + } + + ret = wc_SignatureVerify(WC_HASH_TYPE_SHA256, WC_SIGNATURE_TYPE_RSA_W_ENC, + (byte *)man, + MANIFEST_SIZE - sizeof(struct key_signature), + sigBuf, sigLen, + &rsaKey, sizeof(rsaKey)); + if (ret < 0) { + ERROR("RSA Signature Verification failed: (%d)\n", ret); + goto exit; + } + + if (swap_bytes(sigBuf, sigLen)) { + ERROR("Failed to change RSA Signature endianess!\n"); + goto exit; + } + + memcpy(key_struct->signature, sigBuf, sigLen); +exit: + if (sigBuf) { + free(sigBuf); + } + wc_FreeRsaKey(&rsaKey); + wc_FreeRng(&rng); + + return ret; +} + +static int save_buffer_to_file(const char *filename, byte *buffer, word32 bufLen) +{ + int ret = 0; + FILE* file = NULL; + + file = fopen(filename, "wb"); + if (file == NULL) { + ERROR("Failed to create file %s!\n", filename); + ret = EXIT_FAILURE; + goto exit; + } + + if (fwrite(buffer, 1, bufLen, file) != bufLen) { + ERROR("Error writing %s file! %d", filename, ret); + ret = EXIT_FAILURE; + goto exit; + } + +exit: + if (file) { + fclose(file); + } + + return ret; +} + +static int load_file_to_buffer(const char *filename, byte **fileBuf, word32 *fileLen) +{ + int ret = 0; + FILE *file = NULL; + + file = fopen(filename, "rb"); + if (file == NULL) { + ERROR("File %s does not exist!\n", filename); + ret = EXIT_FAILURE; + goto exit; + } + + *fileLen = get_file_size(file); + /* + * To avoid undefined behavior when reading from potentially unaligned + * pointer, check that the file size is divisible by 4 bytes. Both manifests + * have such sizes (see SB_MANIFEST_SIZE and KEY_MANIFEST_SIZE), so this + * wouldn't fail for valid manifests. In case of coreboot.rom, the offsets are + * calculated relatively to the end of file, so the result may be misaligned if + * file size is misaligned. Instead of repeating checks for proper alignment in + * cmd_verify() and cmd_print(), do it here. + */ + if (*fileLen % sizeof(uint32_t)) { + ERROR("File size isn't a multiple of 4 bytes!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + *fileBuf = malloc(*fileLen); + if (!*fileBuf) { + ERROR("File buffer malloc failed!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (fread(*fileBuf, 1, *fileLen, file) != *fileLen) { + ERROR("Error reading file! %d", ret); + ret = EXIT_FAILURE; + goto exit; + } + +exit: + if (file) { + fclose(file); + } + + return ret; +} + +static int inject_manifest_to_binary(const char *filename, byte *fileBuf, word32 fileLen, + struct manifest *man) +{ + word32 file_size, offset; + + file_size = IBB_SIZE + SB_MANIFEST_SIZE; + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE; + + if (man->header.magic == KEY_MANIFEST_MAGIC) { + file_size += KEY_MANIFEST_SIZE; + offset -= KEY_MANIFEST_SIZE; + /* Key Manifest is 4K big with 3K padded with zeros after the manifest */ + memset(&fileBuf[offset], 0, KEY_MANIFEST_SIZE); + } else if (man->header.magic != SB_MANIFEST_MAGIC) { + ERROR("Invalid manifest type\n"); + return EXIT_FAILURE; + } + + if (fileLen < file_size) { + ERROR("ROM file too small to fit IBB and manifest(s)\n"); + return EXIT_FAILURE; + } + + memcpy(&fileBuf[offset], (byte *)man, MANIFEST_SIZE); + + return save_buffer_to_file(filename, fileBuf, fileLen); +} + +static int cmd_generate_sbm(void) +{ + int ret = 0; + word32 fileLen; + byte *fileBuf = NULL; + word32 oemDataFileLen = 0; + byte *oemDataFileBuf = NULL; + word32 manifest_svn = params.override_svn ? params.svn : 2; + struct manifest man; + + if (params.oem_data_file) { + ret = load_file_to_buffer(params.oem_data_file, &oemDataFileBuf, &oemDataFileLen); + if (ret < 0) { + ERROR("Failed to load OEM Data file\n"); + goto exit; + } + } + + if (params.file_name) { + ret = load_file_to_buffer(params.file_name, &fileBuf, &fileLen); + if (ret < 0) { + goto exit; + } + } else { + ERROR("coreboot image file not given\n"); + return -1; + } + + if (!params.sbm_key_file) { + ERROR("Secure Boot Manifest key file not given\n"); + return -1; + } + + if (manifest_svn > 63) { + ERROR("Secure Boot Manifest SVN %d invalid, allowed range: 0-63\n", manifest_svn); + ret = EXIT_FAILURE; + goto exit; + } + + ret = create_sb_manifest(&man, fileBuf, fileLen, oemDataFileBuf, oemDataFileLen, manifest_svn); + if (ret < 0) { + goto exit; + } + + ret = rsa_sign_manifest(&man, params.sbm_key_file); + if (ret < 0) { + goto exit; + } + + ret = inject_manifest_to_binary(params.file_name, fileBuf, fileLen, &man); + if (ret < 0) { + goto exit; + } + + printf("Secure Boot Manifest generated successfully\n"); + + if (params.output) { + printf("Saving Secure Boot Manifest as %s\n", params.output); + ret = save_buffer_to_file(params.output, (byte *)&man, MANIFEST_SIZE); + } else { + printf("Not saving Secure Boot Manifest as a file, not requested to\n"); + } + +exit: + if (fileBuf) { + free(fileBuf); + } + + if (oemDataFileBuf) { + free(oemDataFileBuf); + } + + return ret; +} + +static int cmd_generate_km(void) +{ + int ret = 0; + word32 fileLen; + byte *fileBuf = NULL; + word32 manifest_svn = params.override_svn ? params.svn : 2; + struct manifest man; + + if (params.file_name) { + ret = load_file_to_buffer(params.file_name, &fileBuf, &fileLen); + if (ret < 0) { + goto exit; + } + } else { + ERROR("coreboot image file not given\n"); + return EXIT_FAILURE; + } + + if (!params.km_key_file) { + ERROR("Key Manifest key file not given\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (!params.sbm_key_file) { + ERROR("Secure Boot Manifest key file not given\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (manifest_svn > 15 || manifest_svn == 0) { + ERROR("Key Manifest SVN %d invalid, allowed range: 1-15\n", manifest_svn); + ret = EXIT_FAILURE; + goto exit; + } + + if (params.override_km_id) { + if (params.km_id == 0 || params.km_id > 15) { + ERROR("Key Manifest ID %d invalid, allowed range: 1-15\n", + params.km_id); + ret = EXIT_FAILURE; + goto exit; + } + } + + ret = create_key_manifest(&man, fileLen, manifest_svn); + if (ret < 0) { + goto exit; + } + + ret = rsa_sign_manifest(&man, params.km_key_file); + if (ret < 0) { + goto exit; + } + + ret = inject_manifest_to_binary(params.file_name, fileBuf, fileLen, &man); + if (ret < 0) { + goto exit; + } + + printf("Key Manifest generated successfully\n"); + + if (params.output) { + printf("Saving Key Manifest as %s\n", params.output); + ret = save_buffer_to_file(params.output, (byte *)&man, MANIFEST_SIZE); + } else { + printf("Not saving Key Manifest as a file, not requested to\n"); + } + +exit: + /* Free */ + if (fileBuf) { + free(fileBuf); + } + + return ret; +} + +static int print_key_hash_from_manifest(const struct manifest *man) +{ + int ret; + wc_Sha256 sha256; + const struct key_signature *key_struct; + uint8_t key_hash[WC_SHA256_DIGEST_SIZE]; + + key_struct = &man->key_sig; + + ret = wc_InitSha256(&sha256); + if (ret != 0) { + ERROR("Failed to initialize SHA256 context\n"); + return ret; + } + + ret = wc_Sha256Update(&sha256, key_struct->modulus, sizeof(key_struct->modulus)); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + ret = wc_Sha256Update(&sha256, (byte *)&key_struct->exponent, + sizeof(key_struct->exponent)); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + ret = wc_Sha256Final(&sha256, key_hash); + if (ret != 0) { + ERROR("Failed to generate SHA256 hash\n"); + return ret; + } + + if (swap_bytes(key_hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Failed to change SHA256 hash endianess!\n"); + return EXIT_FAILURE; + } + + print_sha256(key_hash); + + return ret; +} + +static void print_manifest_header(const struct manifest_header *mh) +{ + printf("\tMagic: "); + print_magic(mh->magic); + printf("\tVersion: %d\n", mh->version); + printf("\tSize: %d\n", mh->size); + printf("\tSvn: %d\n", mh->svn); +} + + +static void print_key_signature(const struct key_signature *ks) +{ + printf("\tKey modulus:\n"); + hexdump(ks->modulus, sizeof(ks->modulus), 16, 2); + printf("\tKey exponent: 0x%x\n", ks->exponent); + printf("\tSignature:\n"); + hexdump(ks->signature, sizeof(ks->signature), 16, 2); +} + +static void print_key_manifest(const struct manifest *km) +{ + printf("Key Manifest:\n"); + print_manifest_header(&km->header); + printf("\tKey Manifest ID: 0x%02x\n", km->km_id); + printf("\tSB Key hash: "); + print_sha256(km->hash); + print_key_signature(&km->key_sig); + printf("\n"); + printf("\tFYI: Secure Boot Key Manifest Key SHA256 hash:\n\n\t"); + print_key_hash_from_manifest(km); + printf("\n\n"); +} + +static void print_sb_manifest(const struct manifest *sbm) +{ + printf("Secure Boot Manifest:\n"); + print_manifest_header(&sbm->header); + printf("\tIBB hash: "); + print_sha256(sbm->hash); + printf("\tOEM Data:\n"); + hexdump(sbm->sb.oem_data, sizeof(sbm->sb.oem_data), 16, 2); + print_key_signature(&sbm->key_sig); + printf("\n"); + printf("\tFYI: Secure Boot Manifest Key SHA256 hash:\n\n\t"); + print_key_hash_from_manifest(sbm); + printf("\n\n"); +} + +static int cmd_print(void) +{ + int ret = 0; + word32 fileLen; + byte *fileBuf = NULL; + bool sbm_found = false; + bool km_found = false; + word32 offset; + + if (params.file_name) { + ret = load_file_to_buffer(params.file_name, &fileBuf, &fileLen); + if (ret < 0) { + goto exit; + } + } else { + ERROR("Image file not given\n"); + return EXIT_FAILURE; + } + + /* Maybe it is SB manifest or KM manifest file (with IBB or not) */ + if (fileLen == MANIFEST_SIZE || fileLen == (IBB_SIZE + SB_MANIFEST_SIZE)) { + if (*(uint32_t *)fileBuf == SB_MANIFEST_MAGIC) { + printf("Input file seems to be a Secure Boot Manifest\n\n"); + print_sb_manifest((struct manifest *)fileBuf); + } else if (*(uint32_t *)fileBuf == KEY_MANIFEST_MAGIC) { + printf("Input file seems to be a Key Manifest\n\n"); + print_key_manifest((struct manifest *)fileBuf); + } else { + ERROR("Input file invalid size\n"); + ret = EXIT_FAILURE; + } + } else if (fileLen == KEY_MANIFEST_SIZE || + fileLen == (IBB_SIZE + SB_MANIFEST_SIZE + KEY_MANIFEST_SIZE)) { + if (*(uint32_t *)fileBuf == KEY_MANIFEST_MAGIC) { + printf("Input file seems to be a Key Manifest\n\n"); + print_key_manifest((struct manifest *)fileBuf); + if (fileLen > KEY_MANIFEST_SIZE && + *(uint32_t *)&fileBuf[KEY_MANIFEST_SIZE] == SB_MANIFEST_MAGIC) { + print_sb_manifest((struct manifest *) + &fileBuf[KEY_MANIFEST_SIZE]); + } + } else { + ERROR("Input file invalid size\n"); + ret = EXIT_FAILURE; + } + } else if (fileLen > (IBB_SIZE + SB_MANIFEST_SIZE + KEY_MANIFEST_SIZE)) { + /* Treat it as a full binary */ + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE - KEY_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == KEY_MANIFEST_MAGIC) { + print_key_manifest((struct manifest *)&fileBuf[offset]); + km_found = true; + } + + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == SB_MANIFEST_MAGIC) { + print_sb_manifest((struct manifest *)&fileBuf[offset]); + sbm_found = true; + } + + if (!sbm_found && !km_found) { + ERROR("Input file invalid, manifests not found\n"); + ret = EXIT_FAILURE; + } + } else { + ERROR("Input file invalid size\n"); + ret = EXIT_FAILURE; + } + +exit: + if (fileBuf) { + free(fileBuf); + } + + return ret; +} + +static int rsa_verify_manifest_signature(const struct manifest *man, const char *key_path) +{ + int ret; + RsaKey rsaKey; + struct key_signature key_struct; + uint8_t modulus[256]; + uint32_t exponent = 0; + word32 e_size = sizeof(exponent); + word32 n_size = sizeof(modulus); + + memcpy(&key_struct, &man->key_sig, sizeof(key_struct)); + + ret = wc_InitRsaKey(&rsaKey, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + goto exit; + } + + ret = rsa_load_key_file(key_path, &rsaKey); + if (ret != 0) { + ERROR("Failed to load RSA key %s! (%d)\n", key_path, ret); + goto exit; + } + + ret = wc_RsaFlattenPublicKey(&rsaKey, (byte *)&exponent, &e_size, + (byte *)&modulus, &n_size); + if (ret != 0) { + ERROR("Failed to extract Secure Boot Manifest Key exponent and modulus!\n"); + return ret; + } + + if (swap_bytes(modulus, sizeof(modulus))) { + ERROR("Failed to change RSA Signature endianess!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (memcmp(modulus, key_struct.modulus, sizeof(modulus))) { + ERROR("RSA key modulus does not match the key used in manifest!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (exponent != key_struct.exponent) { + ERROR("RSA key exponent does not match the key used in manifest!\n"); + ERROR("%x != %x\n", exponent, key_struct.exponent); + ret = EXIT_FAILURE; + goto exit; + } + + if (swap_bytes(key_struct.signature, sizeof(key_struct.signature))) { + ERROR("Failed to change RSA Signature endianess!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + ret = wc_SignatureVerify(WC_HASH_TYPE_SHA256, WC_SIGNATURE_TYPE_RSA_W_ENC, + (byte *)man, + MANIFEST_SIZE - sizeof(struct key_signature), + key_struct.signature, sizeof(key_struct.signature), + &rsaKey, sizeof(rsaKey)); + + if (ret != 0) { + ERROR("Manifest signature verification failed!\n"); + goto exit; + } + +exit: + wc_FreeRsaKey(&rsaKey); + + return ret; +} + +static int verify_sb_key_hash(const struct manifest *man) +{ + int ret; + RsaKey rsaKey; + uint8_t key_hash[32]; + + ret = wc_InitRsaKey(&rsaKey, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + goto exit; + } + + ret = rsa_load_key_file(params.sbm_key_file, &rsaKey); + if (ret != 0) { + ERROR("Failed to load RSA key %s!\n", params.sbm_key_file); + goto exit; + } + + ret = calculate_key_hash(&rsaKey, key_hash); + if (ret != 0) { + ERROR("Failed to calculate RSA key hash %s!\n", params.sbm_key_file); + goto exit; + } + + if (memcmp(key_hash, man->hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Secure Boot Key SHA256 hash does not match the key hash in the Key" + " Manifest!\n"); + print_sha256(key_hash); + print_sha256(man->hash); + ret = EXIT_FAILURE; + } + +exit: + wc_FreeRsaKey(&rsaKey); + + return ret; +} + +static int verify_ibb_hash(const struct manifest *man, const byte *fileBuf, int fileLen) +{ + int ret; + uint8_t ibb_hash[32]; + + ret = calculate_ibb_hash(&fileBuf[fileLen - IBB_SIZE], ibb_hash); + if (ret != 0) { + ERROR("Failed to calcualte IBB hash!\n"); + return ret; + } + + if (memcmp(ibb_hash, man->hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Calculated IBB SHA256 hash does not match the IBB hash in Secure Boot" + " Manifest!\n"); + ret = EXIT_FAILURE; + } + + return ret; +} + +static int cmd_verify(void) +{ + int ret = 0; + word32 fileLen; + byte *fileBuf = NULL; + word32 offset; + const struct manifest *km = NULL; + const struct manifest *sbm = NULL; + + if (params.file_name) { + ret = load_file_to_buffer(params.file_name, &fileBuf, &fileLen); + if (ret < 0) { + goto exit; + } + } else { + ERROR("Image file not given\n"); + return EXIT_FAILURE; + } + + if (fileLen >= (IBB_SIZE + SB_MANIFEST_SIZE + KEY_MANIFEST_SIZE)) { + /* Treat it as a full binary */ + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE - KEY_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == KEY_MANIFEST_MAGIC) { + km = (struct manifest *)&fileBuf[offset]; + } + + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == SB_MANIFEST_MAGIC) { + sbm = (struct manifest *)&fileBuf[offset]; + } + + if (km == NULL && sbm == NULL) { + ERROR("Input file invalid, manifests not found\n"); + ret = EXIT_FAILURE; + goto exit; + } + } else if (fileLen == (IBB_SIZE + SB_MANIFEST_SIZE)) { + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == SB_MANIFEST_MAGIC) { + sbm = (struct manifest *)&fileBuf[offset]; + } + } else { + ERROR("Input file invalid size\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (!params.sbm_key_file) { + ERROR("Secure Boot Manifest key file not given\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (km != NULL && !params.km_key_file) { + ERROR("Key Manifest key file not given, but Key Manifest found in the input" + " file\n"); + ERROR("Can not verify Key Manifest!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (sbm == NULL) { + ERROR("Secure Boot Manifest not found in the input file, but is required!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + /* Verify hash type is supported */ + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != 32) { + ERROR("Hash type SHA256 not supported!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (km != NULL) { + printf("Verifying Key Manifest...\n"); + + ret = 0; + if (km->header.size != MANIFEST_SIZE) { + ERROR("Invalid Key Manifest size field! (%d != 1024)\n", + km->header.size); + ret--; + } + + if (km->km_id == 0 || km->km_id > 15) { + ERROR("Invalid Key Manifest ID field! (%d %s)\n", + km->km_id, km->km_id == 0 ? "== 0" : "> 15"); + ret--; + } + + if (km->key_sig.exponent != RSA_KEY_EXPONENT) { + ERROR("Incorrect RSA key exponent in the Key Manifest!" + " 0x%x != 0x10001\n", km->key_sig.exponent); + ret--; + } + + if (!mem_is_zero(km->reserved, sizeof(km->reserved))) { + ERROR("Key Manifest reserved space is not zeroed!\n"); + ret--; + } + + if (!mem_is_zero((byte *)(km + 1), KEY_MANIFEST_PAD_SIZE)) { + ERROR("Key Manifest is not zero-padded to 4KB!\n"); + ret--; + } + + ret -= verify_sb_key_hash(km); + ret -= rsa_verify_manifest_signature(km, params.km_key_file); + + if (ret == 0) { + printf("Key Manifest verification successful!\n\n"); + printf("TXE should be provisioned with the following key hash:\n"); + print_key_hash_from_manifest(km); + printf("TXE should be provisioned with the following Key Manifest ID:" + " 0x%02x\n\n", km->km_id); + } else { + printf("Key Manifest verification FAILED!\n\n"); + goto exit; + } + } + + printf("Verifying Secure Boot Manifest...\n"); + + ret = 0; + if (sbm->header.size != MANIFEST_SIZE) { + ERROR("Invalid Secure Boot Manifest size field! (%d != 1024)\n", + sbm->header.size); + ret--; + } + + if (sbm->key_sig.exponent != RSA_KEY_EXPONENT) { + ERROR("Incorrect RSA key exponent in the Secure Boot Manifest!" + " 0x%x != 0x10001\n", sbm->key_sig.exponent); + ret--; + } + + ret -= verify_ibb_hash(sbm, fileBuf, fileLen); + ret -= rsa_verify_manifest_signature(sbm, params.sbm_key_file); + + if (ret == 0) { + printf("Secure Boot Manifest verification successful!\n\n"); + if (km == NULL) { + printf("TXE should be provisioned with the following key hash:\n"); + print_key_hash_from_manifest(sbm); + } + } else { + printf("Secure Boot Manifest verification FAILED!\n\n"); + } + +exit: + if (fileBuf) { + free(fileBuf); + } + + return ret; +} + +static int cmd_keyhash(void) +{ + int ret; + RsaKey key; + byte keyhash[WC_SHA256_DIGEST_SIZE]; + + if (!params.file_name) { + ERROR("Key file not given\n"); + return EXIT_FAILURE; + } + + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != WC_SHA256_DIGEST_SIZE) { + ERROR("Hash type SHA256 not supported!\n"); + return EXIT_FAILURE; + } + + ret = wc_InitRsaKey(&key, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + return ret; + } + + ret = rsa_load_key_file(params.file_name, &key); + if (ret != 0) { + ERROR("Failed to load Secure Boot Manifest Key!\n"); + goto exit; + } + + ret = calculate_key_hash(&key, keyhash); + if (ret != 0) { + ERROR("Failed to calculate RSA key hash of '%s'!\n", params.file_name); + goto exit; + } + + printf("SHA256 of RSA key '%s':\n", params.file_name); + print_sha256(keyhash); + +exit: + wc_FreeRsaKey(&key); + return ret; +} + +static struct command { + const char *name; + const char *optstring; + int (*cb)(void); +} commands[] = { + { "print", "h?", cmd_print }, + { "keyhash", "h?", cmd_keyhash }, + { "verify", "h?", cmd_verify }, + { "generate-sbm", "o:h?", cmd_generate_sbm }, + { "generate-km", "o:h?", cmd_generate_km }, +}; + +enum { + LONGOPT_START = 256, + LONGOPT_SBM_KEY_FILE = LONGOPT_START, + LONGOPT_SBM_OEM_DATA, + LONGOPT_KM_KEY_FILE, + LONGOPT_KM_ID, + LONGOPT_MANIFEST_SVN, + LONGOPT_END, +}; + +static struct option long_options[] = { + {"help", 0, 0, 'h'}, + {"version", 0, 0, 'v'}, + {"output", required_argument, 0, 'o'}, + {"sbm-key-file", required_argument, 0, LONGOPT_SBM_KEY_FILE}, + {"oem-data", required_argument, 0, LONGOPT_SBM_OEM_DATA}, + {"km-key-file", required_argument, 0, LONGOPT_KM_KEY_FILE}, + {"km-id", required_argument, 0, LONGOPT_KM_ID}, + {"svn", required_argument, 0, LONGOPT_MANIFEST_SVN}, + {NULL, 0, 0, 0 } +}; + +static bool valid_opt(word32 i, int c) +{ + /* Check if it is one of the optstrings supported by the command. */ + if (strchr(commands[i].optstring, c)) + return true; + + /* + * Check if it is one of the non-ASCII characters. Currently, the + * non-ASCII characters are only checked against the valid list + * irrespective of the command. + */ + return c >= LONGOPT_START && c < LONGOPT_END; +} + +static void usage(const char *name) +{ + printf("txesbmantool: Utility for generating TXE Secure Boot manifests\n" + "USAGE:\n" + " %s FILE COMMAND\n\n" + " %s --help\n\n" + " %s --version\n\n" + "COMMANDs:\n" + " print\n" + " keyhash\n" + " verify --sbm-key-file [--km-key-file ]\n" + " generate-km --sbm-key-file --km-key-file [--km-id ] [--svn ] [-o ]\n" + " generate-sbm --sbm-key-file [--oem-data ] [--svn ] [-o ]\n" + "\nOPTIONS:\n" + " -o : Output manifest file (optional)\n" + " --sbm-key-file : Secure Boot (SB) Manifest key file\n" + " --km-key-file : Key Manifest key file\n" + " --km-id : Key Manifest ID number (default 1)\n" + " --oem-data : Optional OEM data file to be included in SB Manifest\n" + " --svn : Security Version Number for the manifest (default 2),\n" + " Key Manifest SVN range 1-15, SB Manifest SVN range 0-63\n" + "\n", + name, name, name); +} + +static int no_file_cmd_args(int argc, char **argv) +{ + int c; + int option_index; + + c = getopt_long(argc, argv, "?hv", long_options, &option_index); + + switch (c) { + case 'v': + printf("Version: %s\n", tool_version); + return 0; + case 'h': + case '?': + usage(argv[0]); + return 0; + default: + usage(argv[0]); + return 1; + } + + usage(argv[0]); + return 1; +} + +int main(int argc, char **argv) +{ + if (argc < 3) { + return no_file_cmd_args(argc, argv); + } + + const char *prog_name = argv[0]; + const char *file_name = argv[1]; + const char *cmd = argv[2]; + + word32 i; + params.file_name = file_name; + params.override_km_id = false; + params.override_svn = false; + + for (i = 0; i < ARRAY_SIZE(commands); i++) { + if (strcmp(cmd, commands[i].name)) + continue; + + int c; + int option_index; + + while (1) { + c = getopt_long(argc, argv, commands[i].optstring, + long_options, &option_index); + + if (c == -1) + break; + + if (!valid_opt(i, c)) { + if (c < LONGOPT_START) { + ERROR("Invalid option -- '%c'\n", c); + } else { + ERROR("Invalid option -- '%d'\n", c); + } + usage(prog_name); + return 1; + } + + switch (c) { + case 'o': + params.output = optarg; + break; + case LONGOPT_SBM_KEY_FILE: + params.sbm_key_file = optarg; + break; + case LONGOPT_SBM_OEM_DATA: + params.oem_data_file = optarg; + break; + case LONGOPT_KM_KEY_FILE: + params.km_key_file = optarg; + break; + case LONGOPT_KM_ID: + params.km_id = atoi(optarg); + params.override_km_id = true; + break; + case LONGOPT_MANIFEST_SVN: + params.svn = atoi(optarg); + params.override_svn = true; + break; + case 'h': + case '?': + default: + usage(prog_name); + return 1; + } + } + + break; + } + + if (i == ARRAY_SIZE(commands)) { + printf("No command matches %s!\n", cmd); + usage(prog_name); + return 1; + } + + if (commands[i].cb()) + return 1; + + return 0; +}